On Sun, 02 Jun 2002 21:39:52 -0600
Jens Owen [EMAIL PROTECTED] wrote:
Liam,
Did you see the flow chart at
http://dri.sourceforge.net/doc/control_flow_poster.jpg
Yeah - hes very kindly re-drawing them for my site redesign. ;-)
Michel Dänzer wrote:
I've reworked the patch a bit again to try and make the endianness
issues more explicit. It also attempts to fix r128 but I can't test
that.
http://penguinppc.org/~daenzer/DRI/endianness.diff
I'm going to commit this now, will the Mesa changes propagate to the
Hi,
First, I took a look at the current radeon source, but if someone could
explain me what the ringbuffer and the freelist are, i think i would at least
be able to imagine something of what's supposed to happen.
But that source is still 7500 only :-(
Anyway about the FireGL stuff :
On
Peter Soetens (Kaltan) wrote:
Hi,
[...]
Anyway about the FireGL stuff :
On Sunday 02 June 2002 20:45, Garry Reisky wrote:
If there are any 8500 owners out there that have been longing for 3d in
linux, you can download the firegl 8800 drivers and install them . They
will work . These were
On 3 Jun 2002, Michel [ISO-8859-1] Dänzer wrote:
On Mon, 2002-06-03 at 03:39, Vladimir Dergachev wrote:
For people who were interested in observing VSYNC/VBLANK interrupts from
userspace there is an experimental implementation for radeons on
http://gatos.sf.net/ in CVS - module km.
Howzit Jens?
Did you see the flow chart at
http://dri.sourceforge.net/doc/control_flow_poster.jpg
Yes, and I've worked through it.
I am referring to:
http://dri.sourceforge.net/doc/data_flow.jpg
IMHO it doesnt make it any clearer what happens once the 2D 3D data arrives at the X
Server
On Fri, 31 May 2002, Keith Whitwell wrote:
Also note that it actually asks for the pixcache to be flushed *twice* - once
by RADEON_PURGE_CACHE (which writes the RADEON_RB2D_DSTCACHE_CTLSTAT via the
ring) and once in radeon_do_pixcache_flush() which writes the register via MMIO.
Btw, why
Howzit?
A links page was requested and this is what I have so far, have I missed anything, is
anything unneccessary?
If so I think you know what to do about it.
Links to Projects Companies related to DRI:
Chromium Project (The)
http://chromium.sourceforge.net
FbDri
On Mon, 2002-06-03 at 23:39, Linus Torvalds wrote:
On Fri, 31 May 2002, Keith Whitwell wrote:
Also note that it actually asks for the pixcache to be flushed *twice* - once
by RADEON_PURGE_CACHE (which writes the RADEON_RB2D_DSTCACHE_CTLSTAT via the
ring) and once in
Hello,
I checked out the latest trunk update and found that the textures are broken,
now. They are mostly invisible and blue.
Maybe I have some compiler/optimization problems because I'm testing some
better gcc flags for the Athlon.
-O -mcpu=i686 -march=i686 -fno-gcse -fno-regmove
Thanks for digging into this problem.
Here are a few more things to try according to your feedback.
On Sun, 26 May 2002, hy0 wrote:
This one (VT switching lockup with DRI) has been haunting us for a
while. It appears to be hardware (Agp chipset) related.
Yes, and here is something a bit
On Tue, 4 Jun 2002, hy0 wrote:
What does the [agp] Mode... line say with ASUS A7M266-D motherboard?
On the ASUS A7M266-D motherboard (with Option AGPMode 4 in
/etc/X11/XF86Config), it says [agp] Mode 0x0f000217 [AGP 0x1022/0x700c;
Card 0x1002/0x5159]. This is the same as on the Tyan S2460.
12 matches
Mail list logo
