Jürgen Lambrecht wrote:
Hello,
In my view the CYG_HAL_STARTUP_RAM startup mode does not say what it
really is, in reality it is CYG_HAL_STARTUP_REDBOOTRAM: a RAM mode ecos
does not initialize the virtual vector table because it supposes that
RedBoot has done that. Indeed, when debugging
Hello,
In my view the CYG_HAL_STARTUP_RAM startup mode does not say what it
really is, in reality it is CYG_HAL_STARTUP_REDBOOTRAM: a RAM mode ecos
does not initialize the virtual vector table because it supposes that
RedBoot has done that. Indeed, when debugging with RedBoot, you want to
Hi All,
Have hit a problem where in debug builds the initialisation of the bss
section to zero takes so long that the chip watchdogs.
I'm using an MPC866 chip and one of the problems with it is that the
slowest I can set the watchdog to is just over 0.5secs. The bss section
is just under
On Fri, Oct 12, 2007 at 10:40:18AM -0700, Jay Foster wrote:
I'm having a problem using the cdl_interface CDL configury. I have a CDL
package where I have:
requires(CYGINT_XXX == 1)
cdl_interface CYGINT_XXX {
display
}
The interface should be
I'm having a problem using the cdl_interface CDL configury. I have a CDL
package where I have:
requires(CYGINT_XXX == 1)
cdl_interface CYGINT_XXX {
display
}
I (currently) do not have any implementations for this interface enabled. I
would
Will Wagner wrote:
Gary,
Yes that seems to work great.
Do you have any idea about whether the net memory pools need to be in
the bss section in the first place?
Probably not, but it would take some effort to get them into a different
section.
Gary Thomas wrote:
Will Wagner wrote:
Hi
Gary,
Yes that seems to work great.
Do you have any idea about whether the net memory pools need to be in
the bss section in the first place?
Thanks,
Will.
Gary Thomas wrote:
Will Wagner wrote:
Hi All,
Have hit a problem where in debug builds the initialisation of the bss
section to
On Fri, Oct 12, 2007 at 12:33:44PM +0200, ?yvind Harboe wrote:
I'm trying to use lwIP, but I run into problems because lwIP uses
macros, e.g. #define read(a,b,c), which screws things up. I've seen
some posts about people wishing for/thinking about making lwIP more
compatible with a standard
I'm trying to use lwIP, but I run into problems because lwIP uses
macros, e.g. #define read(a,b,c), which screws things up. I've seen
some posts about people wishing for/thinking about making lwIP more
compatible with a standard eCos TCP/IP stack.
Rather than try to adapt the code that is going
Hi All,
Been reviewing the memory buffers for networking on my board.
It seems like the default rules for memory buffer in freebsd_net.cdl is
wrong.
If you follow the default rules the total memory usage is
(256*1024)+(CYGPKG_NET_MAXSOCKETS*1024) and the net mempool ends up
being a quarter
I made 2 small modifications to the previous patch :
*) print time with more digits (to facilitate processing the output as
fixed-width columns)
*) if first clock tick not found, initialize time to 0 ms
diff to previously posted patch :
%--
---
Will Wagner wrote:
Hi All,
Have hit a problem where in debug builds the initialisation of the bss
section to zero takes so long that the chip watchdogs.
I'm using an MPC866 chip and one of the problems with it is that the
slowest I can set the watchdog to is just over 0.5secs. The bss
Andrew Lunn wrote:
On Fri, Oct 12, 2007 at 10:40:18AM -0700, Jay Foster wrote:
I'm having a problem using the cdl_interface CDL configury. I have a CDL
package where I have:
requires(CYGINT_XXX == 1)
cdl_interface CYGINT_XXX {
display
}
The
On 10/12/07, Andrew Lunn [EMAIL PROTECTED] wrote:
On Fri, Oct 12, 2007 at 12:33:44PM +0200, ?yvind Harboe wrote:
[stuff deleted]
So I take it the trick is to implement something equivalent to
freebsd_tcpip/current/src/sys/kern/sockio.c for lwIP then?
I've tinkered a bit w/lwIP FreeBSD:
-
14 matches
Mail list logo
