The PIC32MX chips have one or two shadow sets, on the systems with only
one shadow set it is hardcoded to the highest priority interrupt (7)
I have implemented detection of shadow register use, in this case the
registers do not get pushed on stack, that saves quite a few cpu-cycles
in that
Am 13.08.2016 um 18:57 schrieb Michael Ring:
> Hi!
>
> I am trying to bring interrupt handling routine size down (and speed up) for
> mipsel-embedded target.
>
> I need to use inline assembler routines like this one
>
> procedure TSystemCore.setCoreTimerComp(value : longWord); assembler;
>
I tried a small test program with -CfSoft or -CfMIPS2 or -CfMIPS3,
result is always the same, I did a grep on the *.s files.
I see allocations of float registers within the procedures, when they
are called only cpu registers are marked as allocated.
Michael
Output:
test.s:# Register
Am 21.08.2016 um 13:32 schrieb Michael Ring:
> Was getting high hopes for a moment...
>
> @Charlie: the last point you mention, this optimization is already there. As
> long as I do not call a
> procedure and directly include inline assembler in the interrupt routine all
> is fine, only really
On 13.08.2016 18:57, Michael Ring wrote:
As you can see I have added the used registers list for this procedure
so my expectation was that only the register declared does get added
to the list of used registers.
Just an additional comment:
There are MIPS CPUs (e.g. PIC32 series) that
21.08.2016 14:32, Michael Ring пишет:
Was getting high hopes for a moment...
@Sergej: I just started wondering on usage of fp registers, when I call a
routine that uses floating
point I see that the fp registers are not marked as reserved by the compiler,
what do you think?
The procedure
Was getting high hopes for a moment...
@Charlie: the last point you mention, this optimization is already
there. As long as I do not call a procedure and directly include inline
assembler in the interrupt routine all is fine, only really used
registers are in the list of registers that need
21.08.2016 13:25, Karoly Balogh (Charlie/SGR) пишет:
Well, one possible optimization would be to only save all volatiles if the
interrupt routine actually calls another function. Otherwise only save the
ones used by the current proc. This would allow some very small and very
fast interrupt
Hi,
On Sun, 21 Aug 2016, Sergei Gorelkin wrote:
> It is actually the opposite way around.
> g_save_registers/g_restore_registers methods are only used for first
> implemented targets (i386 and maybe m68k). All newer targets are written
> without calling them, since they are completely
21.08.2016 12:06, Karoly Balogh (Charlie/SGR) пишет:
Hi,
On Sun, 21 Aug 2016, Michael Ring wrote:
So unless there is a way to find out which registers get used by a procedure
the only thing I can do to make interrupt routines as lean as possible is to
not use procedures in them if possible.
Hi,
On Sun, 21 Aug 2016, Michael Ring wrote:
> So unless there is a way to find out which registers get used by a procedure
> the only thing I can do to make interrupt routines as lean as possible is to
> not use procedures in them if possible.
There is a way, of course. Seems like the MIPS CG
Thank you, your comments made me think (and write some more test code).
This is how I understand things right now:
The problem for Interrupt routines is that whenenever a procedure is
called the default list of Non-Volatile registers is allocated.
This is a no-issue in normal code as those
On 19/08/16 22:49, Michael Ring wrote:
Am 19.08.16 um 14:49 schrieb Jonas Maebe:
Michael Ring wrote on Sat, 13 Aug 2016:
I am trying to bring interrupt handling routine size down (and speed
up) for mipsel-embedded target.
I need to use inline assembler routines like this one
procedure
Am 19.08.2016 um 22:49 schrieb Michael Ring:
>
> Am 19.08.16 um 14:49 schrieb Jonas Maebe:
>>
>> Michael Ring wrote on Sat, 13 Aug 2016:
>>
>>> I am trying to bring interrupt handling routine size down (and speed up)
>>> for mipsel-embedded target.
>>>
>>> I need to use inline assembler routines
Am 19.08.16 um 14:49 schrieb Jonas Maebe:
Michael Ring wrote on Sat, 13 Aug 2016:
I am trying to bring interrupt handling routine size down (and speed
up) for mipsel-embedded target.
I need to use inline assembler routines like this one
procedure TSystemCore.setCoreTimerComp(value :
Michael Ring wrote on Sat, 13 Aug 2016:
I am trying to bring interrupt handling routine size down (and speed
up) for mipsel-embedded target.
I need to use inline assembler routines like this one
procedure TSystemCore.setCoreTimerComp(value : longWord); assembler;
nostackframe;
asm
Hi!
I am trying to bring interrupt handling routine size down (and speed up)
for mipsel-embedded target.
I need to use inline assembler routines like this one
procedure TSystemCore.setCoreTimerComp(value : longWord); assembler;
nostackframe;
asm
mtc0 $a1,$11,0
end ['a1'];
inside of the
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