[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2017-01-27 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #28 from Peter Bergner --- I totally agree, especially since the work in progress patch we did have to fix the glibc build had so much fallout.

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2017-01-27 Thread law at redhat dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 Jeffrey A. Law changed: What|Removed |Added Status|REOPENED|RESOLVED Resolution|---

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2017-01-24 Thread joseph at codesourcery dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #26 from joseph at codesourcery dot com --- As of r244815 I don't see the ICE building glibc. 193 FAILs in gcc.sum, 60 in g++.sum, which is comparable to the results I reported with the LRA patches. I don't get ICEs from either

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2017-01-23 Thread law at redhat dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 Jeffrey A. Law changed: What|Removed |Added Status|RESOLVED|REOPENED Resolution|FIXED

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2017-01-22 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #24 from Peter Bergner --- (In reply to Jeffrey A. Law from comment #23) > Fixed by patches on the trunk. We only have a fix for the ICE in the first comment. We still do not have a proper fix for the ICE in Comment 6. Since

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2017-01-22 Thread law at redhat dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 Jeffrey A. Law changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2017-01-20 Thread law at redhat dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 Jeffrey A. Law changed: What|Removed |Added Priority|P3 |P2 CC|

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2017-01-18 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #22 from Peter Bergner --- Author: bergner Date: Thu Jan 19 02:23:35 2017 New Revision: 244609 URL: https://gcc.gnu.org/viewcvs?rev=244609=gcc=rev Log: PR target/78516 * config/rs6000/spe.md (mov_si_e500_subreg0):

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-20 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #21 from Peter Bergner --- (In reply to Peter Bergner from comment #20) > Vlad, for the following change in the hunk above: > > > new_reg != NULL_RTX ? sreg : src, > > shouldn't that always be

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-20 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #20 from Peter Bergner --- (In reply to Peter Bergner from comment #19) > emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, > new_reg != NULL_RTX ? sreg : src, >

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-20 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #19 from Peter Bergner --- (In reply to Peter Bergner from comment #18) > With the patch Vlad attached minus the one unwanted line/typo, I'm getting > an ICE on a powerpc64le-linux bootstrap. Looking into it. Here's a minimal test

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-20 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #18 from Peter Bergner --- With the patch Vlad attached minus the one unwanted line/typo, I'm getting an ICE on a powerpc64le-linux bootstrap. Looking into it. /home/bergner/gcc/gcc-fsf-mainline-pr78516/libgcc/libgcc2.c: In

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-20 Thread joseph at codesourcery dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #17 from joseph at codesourcery dot com --- On Tue, 20 Dec 2016, bergner at gcc dot gnu.org wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 > > --- Comment #16 from Peter Bergner --- > (In reply to Vladimir Makarov

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-19 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #16 from Peter Bergner --- (In reply to Vladimir Makarov from comment #15) > Sorry, I applied your changes manually and did a typo. The line > > SET_SRC (curr_insn_set) = new_reg; > > should be removed. > > I tested this patch

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-19 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #15 from Vladimir Makarov --- (In reply to Peter Bergner from comment #13) > (In reply to Vladimir Makarov from comment #11) > > Created attachment 40372 [details] > > The proposed patch > > Agreed your additions to my change looks

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-19 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #14 from Peter Bergner --- (In reply to Joseph S. Myers from comment #12) > Created attachment 40373 [details] > fnmatch.i preprocessed source > > With that new LRA patch (plus the previous gcc-pr78516.v2.diff) I get an ICE >

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-19 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #13 from Peter Bergner --- (In reply to Vladimir Makarov from comment #11) > Created attachment 40372 [details] > The proposed patch Agreed your additions to my change looks good. However, I'm not so sure about this last hunk: -

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-19 Thread jsm28 at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #12 from Joseph S. Myers --- Created attachment 40373 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40373=edit fnmatch.i preprocessed source With that new LRA patch (plus the previous gcc-pr78516.v2.diff) I get an ICE

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-19 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #11 from Vladimir Makarov --- Created attachment 40372 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40372=edit The proposed patch

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-19 Thread vmakarov at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #10 from Vladimir Makarov --- (In reply to Peter Bergner from comment #8) > where "src" is the subreg:SI ..., so the new_reg mode will be SImode and we > then replace the whole SET_SRC (curr_insn_set) which is the subreg:SI >

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-16 Thread joseph at codesourcery dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #9 from joseph at codesourcery dot com --- That LRA patch (on top of the previous patch) allows the glibc build to complete. Now running gcc/g++/libstdc++ testsuites (I haven't run them with an unmodified copy of the same GCC

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-16 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 Peter Bergner changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org --- Comment

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-13 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #7 from Peter Bergner --- (In reply to Joseph S. Myers from comment #6) > With the "updated fix" gcc-pr78516.v2.diff applied I get an ICE building > glibc. Preprocessed source attached. Compile with: > powerpc-linux-gnuspe-gcc -S

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-13 Thread jsm28 at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #6 from Joseph S. Myers --- Created attachment 40329 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40329=edit Preprocessed source With the "updated fix" gcc-pr78516.v2.diff applied I get an ICE building glibc. Preprocessed

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-13 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 Peter Bergner changed: What|Removed |Added Attachment #40317|0 |1 is obsolete|

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-12 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #4 from Peter Bergner --- Created attachment 40317 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=40317=edit Potential fix to spe.md (In reply to Peter Bergner from comment #2) > So we're hitting this code in

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-12 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 Peter Bergner changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-09 Thread bergner at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 --- Comment #2 from Peter Bergner --- So we're hitting this code in lra-assigns.c:lra_assign():1612: if (flag_checking && !flag_ipa_ra) for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) if (lra_reg_info[i].nrefs != 0 &&

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-12-07 Thread aldyh at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 Aldy Hernandez changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/78516] [7 Regression] ICE in lra_assign for e500v2

2016-11-25 Thread rguenth at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78516 Richard Biener changed: What|Removed |Added Target Milestone|--- |7.0