[Bug target/81988] [7/8 regression] invalid std instruction with odd register

2017-09-08 Thread ebotcazou at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81988 Eric Botcazou changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|---

[Bug target/81988] [7/8 regression] invalid std instruction with odd register

2017-09-08 Thread ebotcazou at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81988 --- Comment #8 from Eric Botcazou --- Author: ebotcazou Date: Fri Sep 8 17:12:15 2017 New Revision: 251905 URL: https://gcc.gnu.org/viewcvs?rev=251905=gcc=rev Log: PR target/81988 * config/sparc/sparc.md (mulsi3): Rename into

[Bug target/81988] [7/8 regression] invalid std instruction with odd register

2017-09-08 Thread ebotcazou at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81988 --- Comment #7 from Eric Botcazou --- Author: ebotcazou Date: Fri Sep 8 17:09:16 2017 New Revision: 251904 URL: https://gcc.gnu.org/viewcvs?rev=251904=gcc=rev Log: PR target/81988 * config/sparc/sparc.md (mulsi3): Rename into

[Bug target/81988] [7/8 regression] invalid std instruction with odd register

2017-09-04 Thread ebotcazou at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81988 --- Comment #6 from Eric Botcazou --- > I've attached a reduced testcase which fails on GCC 7 and 8 with the same > kind of error. This issue is an STD instruction which tries to store an odd > numbered register which is not allowed: Can you

[Bug target/81988] [7/8 Regression] invalid std instruction with odd register

2017-08-29 Thread ebotcazou at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81988 Eric Botcazou changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned

[Bug target/81988] [7/8 Regression] invalid std instruction with odd register

2017-08-29 Thread ebotcazou at gcc dot gnu.org
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81988 Eric Botcazou changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|