https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85769
Tamar Christina changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|---
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85769
--- Comment #7 from Martin Liška ---
Tamar: Can you please update Known to work or close it?
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85769
Jakub Jelinek changed:
What|Removed |Added
Target Milestone|8.2 |8.3
--- Comment #6 from Jakub Jelinek
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85769
--- Comment #5 from Tamar Christina ---
Author: tnfchris
Date: Wed Jun 27 08:08:48 2018
New Revision: 262178
URL: https://gcc.gnu.org/viewcvs?rev=262178=gcc=rev
Log:
Add SIMD to REG pattern for movhf without armv8.2-a support for AArch64
This
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85769
--- Comment #4 from Tamar Christina ---
I have a patch to add the missing case, but that'll just mask the reload bug,
so I'm holding up on posting it while looking at reload.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85769
Wilco changed:
What|Removed |Added
CC||wilco at gcc dot gnu.org
--- Comment #3 from
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85769
Tamar Christina changed:
What|Removed |Added
Status|NEW |ASSIGNED
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85769
--- Comment #2 from Tamar Christina ---
It's not r250673, That was committed 2017-07-28 and a GCC built 2017-08-17
does the correct thing for non-Armv8.2-a. It promotes the fp16 values to 32
bits does the operations and converts them back to
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85769
Richard Biener changed:
What|Removed |Added
Target Milestone|--- |8.2
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85769
ktkachov at gcc dot gnu.org changed:
What|Removed |Added
Status|UNCONFIRMED |NEW
CC|
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