[Bug target/80799] [7/8 Regression] x86-32 bits generates MMX without EMMS

2017-05-19 Thread ubizjak at gmail dot com 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80799

Uroš Bizjak  changed:

   What|Removed |Added

 Status|ASSIGNED|RESOLVED
 Resolution|--- |FIXED
   Target Milestone|7.2 |5.5

--- Comment #10 from Uroš Bizjak  ---
Fixed everywhere.

[Bug target/80799] [7/8 Regression] x86-32 bits generates MMX without EMMS

2017-05-19 Thread uros at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80799

--- Comment #9 from uros at gcc dot gnu.org ---
Author: uros
Date: Fri May 19 18:08:19 2017
New Revision: 248297

URL: https://gcc.gnu.org/viewcvs?rev=248297=gcc=rev
Log:
Backport from mainline
2017-05-18  Uros Bizjak  

PR target/80799
* config/i386/mmx.md (*mov_internal): Enable
alternatives 11, 12, 13 and 14 also for 32bit targets.
Remove alternatives 15, 16, 17 and 18.
* config/i386/sse.md (vec_concatv2di): Change
alternative (!x, *y) to (x, ?!*Yn).

testsuite/ChangeLog:

Backport from mainline
2017-05-18  Uros Bizjak  

PR target/80799
* g++.dg/other/i386-11.C: New test.


Added:
branches/gcc-5-branch/gcc/testsuite/g++.dg/other/i386-11.C
Modified:
branches/gcc-5-branch/gcc/ChangeLog
branches/gcc-5-branch/gcc/config/i386/mmx.md
branches/gcc-5-branch/gcc/config/i386/sse.md
branches/gcc-5-branch/gcc/testsuite/ChangeLog

[Bug target/80799] [7/8 Regression] x86-32 bits generates MMX without EMMS

2017-05-19 Thread uros at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80799

--- Comment #8 from uros at gcc dot gnu.org ---
Author: uros
Date: Fri May 19 15:51:10 2017
New Revision: 248294

URL: https://gcc.gnu.org/viewcvs?rev=248294=gcc=rev
Log:
Backport from mainline
2017-05-18  Uros Bizjak  

PR target/80799
* config/i386/mmx.md (*mov_internal): Enable
alternatives 11, 12, 13 and 14 also for 32bit targets.
Remove alternatives 15, 16, 17 and 18.
* config/i386/sse.md (vec_concatv2di): Change
alternative (!x, *y) to (x, ?!*Yn).

testsuite/ChangeLog:

Backport from mainline
2017-05-18  Uros Bizjak  

PR target/80799
* g++.dg/other/i386-11.C: New test.


Added:
branches/gcc-6-branch/gcc/testsuite/g++.dg/other/i386-11.C
Modified:
branches/gcc-6-branch/gcc/ChangeLog
branches/gcc-6-branch/gcc/config/i386/mmx.md
branches/gcc-6-branch/gcc/config/i386/sse.md
branches/gcc-6-branch/gcc/testsuite/ChangeLog

[Bug target/80799] [7/8 Regression] x86-32 bits generates MMX without EMMS

2017-05-19 Thread uros at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80799

--- Comment #7 from uros at gcc dot gnu.org ---
Author: uros
Date: Fri May 19 14:09:45 2017
New Revision: 248284

URL: https://gcc.gnu.org/viewcvs?rev=248284=gcc=rev
Log:
Backport from mainline
2017-05-18  Uros Bizjak  

PR target/80799
* config/i386/mmx.md (*mov_internal): Enable
alternatives 11, 12, 13 and 14 also for 32bit targets.
Remove alternatives 15, 16, 17 and 18.
* config/i386/sse.md (vec_concatv2di): Change
alternative (!x, *y) to (x, ?!*Yn).

testsuite/ChangeLog:

Backport from mainline
2017-05-18  Uros Bizjak  

PR target/80799
* g++.dg/other/i386-11.C: New test.


Added:
branches/gcc-7-branch/gcc/testsuite/g++.dg/other/i386-11.C
Modified:
branches/gcc-7-branch/gcc/ChangeLog
branches/gcc-7-branch/gcc/config/i386/mmx.md
branches/gcc-7-branch/gcc/config/i386/sse.md
branches/gcc-7-branch/gcc/testsuite/ChangeLog

[Bug target/80799] [7/8 Regression] x86-32 bits generates MMX without EMMS

2017-05-18 Thread uros at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80799

--- Comment #6 from uros at gcc dot gnu.org ---
Author: uros
Date: Thu May 18 18:03:30 2017
New Revision: 248246

URL: https://gcc.gnu.org/viewcvs?rev=248246=gcc=rev
Log:
PR target/80799
* config/i386/mmx.md (*mov_internal): Enable
alternatives 11, 12, 13 and 14 also for 32bit targets.
Remove alternatives 15, 16, 17 and 18.
* config/i386/sse.md (vec_concatv2di): Change
alternative (!x, *y) to (x, ?!*Yn).

testsuite/ChangeLog:

PR target/80799
* g++.dg/other/i386-11.C: New test.


Added:
trunk/gcc/testsuite/g++.dg/other/i386-11.C
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/i386/mmx.md
trunk/gcc/config/i386/sse.md
trunk/gcc/testsuite/ChangeLog

[Bug target/80799] [7/8 Regression] x86-32 bits generates MMX without EMMS

2017-05-18 Thread ubizjak at gmail dot com 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80799

Uroš Bizjak  changed:

   What|Removed |Added

 Status|NEW |ASSIGNED
   Assignee|unassigned at gcc dot gnu.org  |ubizjak at gmail dot com

--- Comment #5 from Uroš Bizjak  ---
Created attachment 41381
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=41381=edit
Patch in testing

[Bug target/80799] [7/8 Regression] x86-32 bits generates MMX without EMMS

2017-05-18 Thread ubizjak at gmail dot com 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80799

--- Comment #4 from Uroš Bizjak  ---
(In reply to H.J. Lu from comment #3)
> This is caused by r243527.

Thanks.  FYI, the above revision just triggers the issue.

I have a patch.

[Bug target/80799] [7/8 Regression] x86-32 bits generates MMX without EMMS

2017-05-17 Thread hjl.tools at gmail dot com 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80799

H.J. Lu  changed:

   What|Removed |Added

 Blocks||70118

--- Comment #3 from H.J. Lu  ---
This is caused by r243527.


Referenced Bugs:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70118
[Bug 70118] UBSan claims misaligned access in SSE instrinsics

[Bug target/80799] [7/8 Regression] x86-32 bits generates MMX without EMMS

2017-05-17 Thread ubizjak at gmail dot com 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80799

--- Comment #2 from Uroš Bizjak  ---
There is something going on in the middle end, the problematic alternatives of
the relevant patterns:

movq(%ebx), %mm0# 6 *movv2si_internal/8 [length = 3]
movq2dq %mm0, %xmm1 # 13vec_concatv2di/7[length = 4]
pcmpeqd %xmm1, %xmm0# 17*sse2_eqv4si3/1 [length = 4]
pmovmskb%xmm0, %eax # 18sse2_pmovmskb   [length = 4]
cmpl$65535, %eax# 20*cmpsi_1/1  [length = 5]
je  .L2 # 21*jcc_1  [length = 2]
call_Z10dummy_callv # 23*call   [length = 5]
movq(%ebx), %mm0# 24*movv2si_internal/8 [length = 3]
.L2:
movq%mm0, TRXPOS# 29*movv2si_internal/9 [length = 8]

are all decorated with "!".

(define_insn "*mov_internal"
  [(set (match_operand:MMXMODE 0 "nonimmediate_operand"
"=r ,o ,r,r ,m ,?!y,!y,?!y,m  ,r   ,?!Ym,v,v,v,m,*x,*x,*x,m ,r
,Yi,!Ym,*Yi")
(match_operand:MMXMODE 1 "vector_move_operand"
"rCo,rC,C,rm,rC,C  ,!y,m  ,?!y,?!Yn,r   ,C,v,m,v,C ,*x,m ,*x,Yj,r
,*Yj,!Yn"))]

(define_insn "vec_concatv2di"
  [(set (match_operand:V2DI 0 "register_operand"
  "=Yr,*x,x ,v ,Yi,v ,!x,x,v ,x,x,v")
(vec_concat:V2DI
  (match_operand:DI 1 "nonimmediate_operand"
  "  0, 0,x ,Yv,r ,vm,*y,0,Yv,0,0,v")
  (match_operand:DI 2 "vector_move_operand"
  "*rm,rm,rm,rm,C ,C ,C ,x,Yv,x,m,m")))]

I'm afraid this is all target can do to avoid (but still allow) certain
alternative.  The testcase works for gcc-6, and those patterns were not touched
for a long time.

Can someone please do a reghunt here?

[Bug target/80799] [7/8 Regression] x86-32 bits generates MMX without EMMS

2017-05-17 Thread rguenth at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80799

Richard Biener  changed:

   What|Removed |Added

 Target||i?86-*-*
   Priority|P3  |P2
 Status|UNCONFIRMED |NEW
  Known to work||5.4.0, 6.3.1
   Keywords||wrong-code
   Last reconfirmed||2017-05-17
  Component|rtl-optimization|target
 Ever confirmed|0   |1
Summary|[7 Regression] x86-32 bits  |[7/8 Regression] x86-32
   |generates MMX without EMMS  |bits generates MMX without
   ||EMMS
   Target Milestone|--- |7.2

--- Comment #1 from Richard Biener  ---
Confirmed.  Note I think you are using xmm yourself via the intrinsics.  The IL
contains vector(2) int vectors.