Some testcases still had --param=riscv-autovec-preference=_,
update to use -mrvv-vector-bits=_. Also add missing period
in riscv.opt which caused a compiler driver error.
gcc/ChangeLog:
* config/riscv/riscv.opt: Add missing period
gcc/testsuite/ChangeLog:
*
On 4/11/2024 5:45 AM, Li, Pan2 wrote:
Thanks for reporting this. Just take a look from my test log that 930623-1.c is
all pass.
Thus I bet this difference comes from the build option --with-arch=rv32imac but
my test script take rv64gcv.
I've built the git revision f3fdcf4a37a with
On 4/4/2024 7:40 AM, Palmer Dabbelt wrote:
On Thu, 04 Apr 2024 07:37:56 PDT (-0700), ja...@redhat.com wrote:
On Thu, Apr 04, 2024 at 07:28:40AM -0700, Palmer Dabbelt wrote:
I'm not sure if we need release maintainer approval,
For cherry-picking one's own non-risky bugfixes for regression
We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and
there is nothing to advance, but that is not the case for (...) functions
returning by hidden reference which have one such artificial argument.
This causes gcc.dg/c23-stdarg-[68].c to fail
Fix the issue by checking if
On 3/18/2024 8:14 PM, Jeff Law wrote:
On 3/12/24 3:56 PM, Edwin Lu wrote:
Given the recent change with adding the scheduler pipeline descriptions,
many scan-dump failures emerged. Relax the expected assembler output
conditions on the affected tests to reduce noise.
gcc/testsuite/ChangeLog
On 3/18/2024 8:07 PM, Jeff Law wrote:
On 3/18/24 12:54 PM, Edwin Lu wrote:
We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named
arguments and
there is nothing to advance, but that is not the case for (...)
functions
returning by hidden reference which have one such artificial
We assume that TYPE_NO_NAMED_ARGS_STDARG_P don't have any named arguments and
there is nothing to advance, but that is not the case for (...) functions
returning by hidden reference which have one such artificial argument.
This causes gcc.dg/c23-stdarg-[68].c to fail
Fix the issue by checking if
: Ditto
Signed-off-by: Edwin Lu
---
V1: Change tests to scan for range of vsetvls instead of specific number
V2: Add -fno-schedule-insns and -fno-schedule-insns2 to testcases that
were missing them. Those that had disabled insn scheduling, update
testcases to match current outputs to pass
(slpeel_tree_duplicate_loop_to_edge_cfg):
Recalculate dominator info when adding new_preheader to cfg
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr114197.c: New test.
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.dg/vect/pr114197.c | 18 ++
gcc/tree-vect-loop-manip.cc | 17 -
2
/vlmax_switch_vtype-6.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: Ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: Ditto
Signed-off-by: Edwin Lu
---
.../costmodel/riscv/rvv/dynamic-lmul4-6.c
On 2/21/2024 10:57 AM, Robin Dapp wrote:
For calling-convention-*.c, LGTM but one nit about change log. Take
**Update** here may make others not easy to learn what you did about
the file. You can say similar to "Rearrange and adjust the
asm-checker times" or likewise. Of course, you can refine
Committed
Edwin
On 2/20/2024 5:36 PM, Kito Cheng wrote:
LGTM, thanks for fixing that issue :)
On Wed, Feb 21, 2024 at 6:03 AM Edwin Lu wrote:
The testcase pr113742.c is failing for 32 bit targets due to the following cc1
error:
cc1: error: ABI requries '-march=rv64'
Specify '-march=rv64gc
/ChangeLog:
* gcc.target/riscv/pr113742.c: change mcpu to mtune and add march
Signed-off-by: Edwin Lu
---
V1: use require-effective-target
V2: switch to specifying march and mtune
---
gcc/testsuite/gcc.target/riscv/pr113742.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
Thanks! Committed
Edwin
On 2/15/2024 9:27 AM, Mike Stump wrote:
On Feb 12, 2024, at 11:38 AM, Edwin Lu wrote:
There is currently no support for matching at least x lines of assembly
(only scan-assembler-times). This patch would allow setting upper or lower
bounds.
Use case: using different
On 2/15/2024 1:25 AM, Li, Pan2 wrote:
Sorry for late reply due to holiday. I double-checked the
calling-convernsion-*.c dump, it is safe to adjust the asm check to the number
as you mentioned.
Hi Pan,
I hope you had a good holiday! I already changed the numbers and added a
bit more checks
/binop_vx_constraint-8.c: ditto
* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: ditto
* gcc.target/riscv/rvv/vsetvl/avl_single-107.c: change expected vsetvl
Signed-off-by: Edwin Lu
---
V1-3:
- Patch did not exist
V4:
- New patch
- improve calling-convention testcases (calling-conventions
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: ditto
* gfortran.dg/vect/vect-8.f90: ditto
Signed-off-by: Edwin Lu
---
V2:
- New patch
V3/V4
(generic_ooo_vec_vesetvl): ditto
(generic_ooo_vec_setrm): ditto
(generic_ooo_vec_readlen): ditto
* config/riscv/riscv.md: include generic-vector-ooo
* config/riscv/generic-vector-ooo.md: New file. to here
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2:
- Remove
Enables assert that every typed instruction is associated with a
dfa reservation
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
Signed-off-by: Edwin Lu
---
V2:
- No changes
V3:
- Remove debug statements
V4:
- no changes
---
gcc/config/riscv
(sifive_p400_clmul): ditto
* config/riscv/sifive-p600.md (sifive_p600_clmul): ditto
* config/riscv/vector.md: change rdfrm to fmove
* config/riscv/zc.md: change pushpop to load/store
Signed-off-by: Edwin Lu
---
V2:
- Add insn reservations for HF fmul
- Remove/adjust insn types
V3
edule-insn -fno-schedule-insn2 to some test cases
V3:
- Separate vector pipelines to separate file which all tunes have access to
V4:
- Add insn reservations to sifive-p400 and sifive-p600 series
- Update test cases with new code generation
---
Edwin Lu (5):
RISC-V: Add non-vector types to dfa
On 2/14/2024 12:09 PM, Robin Dapp wrote:
On 2/14/24 20:46, Edwin Lu wrote:
The testcase pr113742.c is failing for 32 bit targets due to the following cc1
error:
cc1: error: ABI requries '-march=rv64'
I think we usually just add exactly this to the test options (so
it is always run rather
-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/pr113742.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target/riscv/pr113742.c
b/gcc/testsuite/gcc.target/riscv/pr113742.c
index ab8934c2a8a..9cea92ed97c 100644
--- a/gcc/testsuite/gcc.target/riscv/pr113742.c
+++ b/gcc/testsuite
ing
as granular towards specific cpu tuning.
gcc/ChangeLog:
* doc/sourcebuild.texi: add scan-assembler-bound
gcc/testsuite/ChangeLog:
* lib/scanasm.exp: add scan-assembler-bound
Signed-off-by: Edwin Lu
---
gcc/doc/sourcebuild.texi | 4 +++
gcc/testsuite/lib/scanasm.exp |
is enabled
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/abi-1.c: change selector
* gcc.target/riscv/rvv/base/pragma-2.c: ditto
* gcc.target/riscv/rvv/base/pragma-3.c: ditto
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c | 2 +-
gcc/testsuite
extension
* config/riscv/arch-canonicalize: ditto
Signed-off-by: Edwin Lu
---
gcc/common/config/riscv/riscv-common.cc | 7 +++
gcc/config/riscv/arch-canonicalize | 1 +
2 files changed, 8 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv
On 2/2/2024 11:10 PM, Li, Pan2 wrote:
Hi Edwin
I believe the only problematic failures are the 5 vls calling convention
ones where only 24 ld\\s+a[0-1],\\s*[0-9]+\\(sp\\) are found.
Does this "only 24" comes from calling-convention-1.c?
Oops sorry about that. I said I would include all the
On 2/1/2024 8:28 PM, Li, Pan2 wrote:
Hi Edwin,
Just rerun the newlib and there is no ICE but still 160 dump failures as below.
Pan
Hi Pan,
Thanks for confirming! Having dump failures is expected. There are
around 7 more unique failures than I expected
ilures are a result of now having a vector
scheduling pipeline.
Edwin
*From:* Edwin Lu <mailto:e...@rivosinc.com>
*Date:* 2024-02-01 14:13
*To:* juzhe.zh...@rivai.ai <mailto:juzhe.zh...@rivai.ai>;
gcc-patches <mailto:gcc-patches@gcc.gnu.org>
*CC:* Robin Dapp <
find anything unexpected.
Edwin
*From:*juzhe.zh...@rivai.ai
*Sent:* Thursday, February 1, 2024 3:06 PM
*To:* Edwin Lu ; gcc-patches
*Cc:* Robin Dapp ; kito.cheng
; jeffreyalaw ; palmer
; vineetg ; Patrick O'Neill
*Subject:* Re: Re: [COMMITTED V3 1/4] RISC-V: Add non-vector types to
dfa
runs using our full gcc postcommit testing configurations and
should have those results in tomorrow. Hopefully it was just a missed
config target I didn't test and wasn't tested on the precommit ci.
Edwin
On 1/31/2024 9:42 PM, Edwin Lu wrote:
Hi Juzhe,
I didn't see any ICEs when I tested
Hi Juzhe,
I didn't see any ICEs when I tested locally (tested on
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=8123f3ca3fd891034a8366518e756f161c4ff40d).
Can you tell me what config you're using?
Edwin
On 1/31/2024 6:57 PM, juzhe.zh...@rivai.ai wrote:
Hi, all.
I recently committed changes modifying the scheduling reservations. Some
things may need to be retested with the newly enabled asserts.
Edwin
On 1/31/2024 1:40 AM, Monk Chiang wrote:
Add sifive p600 series scheduler module. For more information
see
On 1/31/2024 12:28 PM, Robin Dapp wrote:
LGTM, thanks.
Regards
Robin
Committed!
Edwin
On 1/25/2024 9:06 AM, Robin Dapp wrote:
/* If we ever encounter an insn without an insn reservation, trip
an assert so we can find and fix this problem. */
-#if 0
+ if (! insn_has_dfa_reservation_p (insn)) {
+print_rtl(stderr, insn);
+fprintf(stderr, "%d", get_attr_type
On 1/25/2024 9:06 AM, Robin Dapp wrote:
Use default cost model scheduling on these test cases. All these tests
introduce scan dump failures with -mtune generic-ooo. Since the vector
cost models are the same across all three tunes, some of the tests
in PR113249 will be fixed with this patch
On 1/25/2024 9:06 AM, Robin Dapp wrote:
LGTM, thanks.
Regards
Robin
Committed!
Edwin
(generic_ooo_vec_vesetvl): ditto
(generic_ooo_vec_setrm): ditto
(generic_ooo_vec_readlen): ditto
* config/riscv/riscv.md: include generic-vector-ooo
* config/riscv/generic-vector-ooo.md: New file. to here
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2:
- Remove
/rvv/base/pragma-2.c: ditto
* gcc.target/riscv/rvv/base/pragma-3.c: ditto
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c| 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pragma-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pragma-3.c | 2 +-
3 files
On 1/25/2024 9:06 AM, Robin Dapp wrote:
/* If we ever encounter an insn without an insn reservation, trip
an assert so we can find and fix this problem. */
-#if 0
+ if (! insn_has_dfa_reservation_p (insn)) {
+print_rtl(stderr, insn);
+fprintf(stderr, "%d", get_attr_type
On 1/25/2024 9:06 AM, Robin Dapp wrote:
39 additional unique testsuite failures (scan dumps) will still be present.
I don't know how optimal the new output is compared to the old. Should I update
the testcase expected output to match the new scan dumps?
Currently, without vector op latency,
On 1/25/2024 9:06 AM, Robin Dapp wrote:
Thanks, that looks better IMHO.
+;; Copyright (C) 2011-2024 Free Software Foundation, Inc.
+;; Contributed by Andrew Waterman (and...@sifive.com).
+;; Based on MIPS target for GNU compiler.
You might want to change that, as well as the date. While at
On 1/16/2024 5:41 PM, juzhe.zh...@rivai.ai wrote:
Are you saying using glibc lib ? I do the testing with newlib, I didn't
anything wrong.
Yes, I'm seeing the problem using glibc. Looking at our postcommit ci
reports, it appears to only affect linux rv32gcv.
It seems that this patch triggers
Hi Juzhe,
I'm seeing that this patch introduces failures with rv32gcv-ilp32d as
seen here https://github.com/ewlu/gcc-precommit-ci/issues/1194. Digging
a little deeper, it appears that there's an illegal instruction in a
shared library which (at least for FAIL:
/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: ditto
* gfortran.dg/vect/vect-8.f90: ditto
Signed-off-by: Edwin Lu
---
gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C | 2 ++
gcc/testsuite/gcc.target/riscv/rvv
Enables assert that every typed instruction is associated with a
dfa reservation
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
Signed-off-by: Edwin Lu
---
V2:
- No changes
V3:
- No changes
---
gcc/config/riscv/riscv.cc | 6 --
1 file changed, 4
-by: Edwin Lu
Co-authored-by: Robin Dapp
---
V2:
- Remove unnecessary syntax changes in generic-ooo
- Add new vector crypto reservations and types to
pipelines
V3:
- Move all vector pipelines into separate file which defines all ooo vector
reservations.
- Add temporary attribute while cost
to fmove
* config/riscv/zc.md: change pushpop to load/store
Signed-off-by: Edwin Lu
---
V2:
- Add insn reservations for HF fmul
- Remove/adjust insn types
V3:
- No changes
---
gcc/config/riscv/generic-ooo.md | 15 +-
gcc/config/riscv/generic.md | 20 +--
gcc/config/riscv
types must be associated with a dfa pipeline
reservation
Edwin Lu (4):
RISC-V: Add non-vector types to dfa pipelines
RISC-V: Add vector related pipelines
RISC-V: Use default cost model for insn scheduling
RISC-V: Enable assert for insn_has_dfa_reservation
---
V2:
- Update non-vector insn types a
Since all the pipelines should be tuned to their cost model, they
would be different anyway. If it would be simpler for now, I could
separate the files out.
I think I'm getting a bit confused. Is there a reason why we would
want to exchange scheduler descriptions like the example you
provided?
Hi Robin,
On 1/10/2024 8:00 AM, Robin Dapp wrote:
Hi Edwin,
This patch copies the vector reservations from generic-ooo.md and
inserts them into generic.md and sifive.md. Creates new vector crypto related
insn reservations.
In principle, the changes look good to me but I wonder if we could
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: ditto
* gfortran.dg/vect/vect-8.f90: ditto
Signed-off-by: Edwin Lu
---
V2:
- New patch
---
gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C | 2 ++
gcc
to fmove
* config/riscv/zc.md: change pushpop to load/store
Signed-off-by: Edwin Lu
---
V2:
- Add insn reservations for HF fmul
- Remove/adjust insn types
---
gcc/config/riscv/generic-ooo.md | 15 +-
gcc/config/riscv/generic.md | 20 +--
gcc/config/riscv/riscv.md | 18
Enables assert that every typed instruction is associated with a
dfa reservation
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
Signed-off-by: Edwin Lu
---
V2:
- No changes
---
gcc/config/riscv/riscv.cc | 6 --
1 file changed, 4 insertions(+), 2
output of the test cases to
the output of the new cost model? I'm not fully sure which codegen is more
optimal. Please let me know if I should do so and I'll add a patch adjusting
the expected testcase output.
Edwin Lu (4):
RISC-V: Add non-vector types to dfa pipelines
RISC-V: Add vector related
(sifive_7_vec_ordered_reduction): ditto
(sifive_7_vec_idiv): ditto
(sifive_7_vec_float_divsqrt): ditto
(sifive_7_vec_mask): ditto
(sifive_7_vec_vesetvl): ditto
(sifive_7_vec_setrm): ditto
(sifive_7_vec_readlen): ditto
Signed-off-by: Edwin Lu
Co-authored
On 12/20/2023 2:55 PM, Edwin Lu wrote:
On 12/20/2023 10:57 AM, Jeff Law wrote:
On 12/15/23 11:53, Edwin Lu wrote:
This patch copies the vector reservations from generic-ooo.md and
inserts them into generic.md and sifive.md. The vector pipelines are
necessary to avoid an ICE from
On 12/20/2023 10:57 AM, Jeff Law wrote:
On 12/15/23 11:53, Edwin Lu wrote:
This patch copies the vector reservations from generic-ooo.md and
inserts them into generic.md and sifive.md. The vector pipelines are
necessary to avoid an ICE from the assert
gcc/ChangeLog:
* config/riscv
On 12/20/2023 10:50 AM, Jeff Law wrote:
On 12/15/23 11:53, Edwin Lu wrote:
This patch does not create vector related insn reservations for
generic.md and sifive-7.md. It updates/creates insn reservations
for all non-vector typed insns
gcc/ChangeLog:
* config/riscv/generic-ooo.md
Enables assert that every typed instruction is associated with a
dfa reservation
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.cc | 2 --
1 file changed, 2 deletions(-)
diff --git a/gcc/config
(sifive_7_vec_idiv): ditto
(sifive_7_vec_float_divsqrt): ditto
(sifive_7_vec_mask): ditto
(sifive_7_vec_vesetvl): ditto
(sifive_7_vec_setrm): ditto
(sifive_7_vec_readlen): ditto
Signed-off-by: Edwin Lu
Co-authored-by: Robin Dapp
---
gcc/config/riscv/generic-ooo.md
): ditto
* config/riscv/generic.md (generic_sfb_alu): ditto
* config/riscv/sifive-7.md (sifive_7_popcount): ditto
Signed-off-by: Edwin Lu
---
gcc/config/riscv/generic-ooo.md | 16 +---
gcc/config/riscv/generic.md | 13 +
gcc/config/riscv/sifive-7.md| 12
incorrect modeling assumptions. I created
PR113035 which has the full testsuite failures I saw (without the patches
applied).
Edwin Lu (3):
RISC-V: Add non-vector types to pipelines
RISC-V: Add vector related reservations
RISC-V: Enable assert for insn_has_dfa_reservation
gcc/config/riscv/generic
/pr65310.c: ditto
* gfortran.dg/vect/vect-8.f90: ditto
Signed-off-by: Edwin Lu
---
V2 changes:
- added attr-alloc_size-11.c and update-threading.c which were missed in
previous patch
- remove pr83232.f90 xfail since it was fixed in a recent trunk update
- adjust xfail on split-path-11.c
On 12/10/2023 9:37 PM, Kito Cheng wrote:
diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
b/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
index b8a2bd1ebbd..6f2fc56c82c 100644
--- a/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
+++ b/gcc/testsuite/g++.dg/tree-ssa/pr83518.C
@@ -24,4 +24,4 @@ unsigned
/pr65310.c: ditto
* gfortran.dg/vect/vect-8.f90: ditto
* lib/target-supports.exp: ditto
Signed-off-by: Edwin Lu
---
V2 changes:
- added attr-alloc_size-11.c and update-threading.c which were missed in
previous patch
- remove pr83232.f90 xfail since it was fixed in a recent trunk
* gcc.dg/vect/pr103116-1.c: ditto
* gcc.dg/vect/pr103116-2.c: ditto
* gfortran.dg/vect/pr83232.f90: ditto
* gfortran.dg/vect/vect-8.f90: ditto
Signed-off-by: Edwin Lu
---
gcc/testsuite/c-c++-common/vector-subscript-4.c | 3 ++-
gcc/testsuite/g++.dg/tree-ssa/pr83518.C
at all.
was introduced. The test did pass at that hash and has continued to
pass since
then. Remove the xfail
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/ssa-fre-3.c: Remove xfail
Signed-off-by: Edwin Lu
---
gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c | 2 +-
1 file changed, 1 insertion
Ran the test case at 122e7b4f9d0c2d54d865272463a1d812002d0a5c where the xfail
was introduced. The test did pass at that hash and has continued to pass since
then. Remove the xfail
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/ssa-fre-3.c: Remove xfail
Signed-off-by: Edwin Lu
---
gcc
Committed!
On 11/15/2023 11:34 PM, Kito Cheng wrote:
ohhh, thanks for fixing that, LGTM!
On Thu, Nov 16, 2023 at 7:31 AM Edwin Lu wrote:
Fix __riscv_unaligned_fast/slow/avoid macro name to
__riscv_misaligned_fast/slow/avoid to be consistent with the RISC-V API Spec
gcc/ChangeLog
-align-4.c: ditto
* gcc.target/riscv/predef-align-5.c: ditto
* gcc.target/riscv/predef-align-6.c: ditto
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv-c.cc | 6 +++---
gcc/testsuite/gcc.target/riscv/attribute-1.c| 10 +-
gcc/testsuite/gcc.target
On 11/1/2023 11:53 AM, Jeff Law wrote:
On 11/1/23 12:17, Edwin Lu wrote:
Now that all insns are guaranteed to have a type, ensure every insn
is associated with a cpu unit/insn reservation.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): add disabled
assert
OK
Now that all insns are guaranteed to have a type, ensure every insn
is associated with a cpu unit/insn reservation.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): add disabled
assert
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.cc | 6 ++
1 file
On 11/1/2023 8:07 AM, Vladimir Makarov wrote:
On 10/31/23 18:51, Edwin Lu wrote:
genattr.cc currently generates insn-attr.h with the following structure:
#if CPU_UNITS_QUERY
extern int get_cpu_unit_code (const char *);
extern int cpu_unit_reservation_p (state_t, int);
#endif
extern bool
is not associated
with a cpu unit or insn reservation through the TARGET_SCHED_VARIABLE_ISSUE
hook.
If there is a reason for insn_has_dfa_reservation_p being within the
conditional, please let me know!
gcc/Changelog:
* genautomata.cc (write_automata): move endif
Signed-off-by: Edwin
On 10/10/2023 10:11 AM, Jeff Law wrote:
On 10/9/23 15:02, Edwin Lu wrote:
Now that every insn is guaranteed a type, we want to ensure the types are
handled by the existing scheduling descriptions.
There are 2 approaches I see:
1. Create a new pipeline intended to eventually abort (sifive-7
* config/riscv/sifive-7.md (sifive_7): update pipeline
(sifive_7_other):
Signed-off-by: Edwin Lu
---
gcc/config/riscv/generic.md | 3 ++-
gcc/config/riscv/sifive-7.md | 7 +++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv
Hi Juzhe,
I was testing this patch and found it introduced a gfortran regression
in gfortran.dg/host_assoc_function_7.f90. More info here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111545
Edwin
On 9/20/2023 7:17 PM, Juzhe-Zhong wrote:
Support INT <-> FP VLS auto-vectorization patterns.
On 9/11/2023 5:49 PM, Jeff Law via Gcc-patches wrote:
On 9/11/23 16:52, Edwin Lu wrote:
Updates autovec instruction that was added after last patch and turns
on the
assert statement to ensure all new instructions have a type.
* config/riscv/autovec-opt.md: Update type
* config/riscv
Updates autovec instruction that was added after last patch and turns on the
assert statement to ensure all new instructions have a type.
* config/riscv/autovec-opt.md: Update type
* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
Signed-off-by: Edwin Lu
On 9/6/2023 4:23 PM, Kito Cheng via Gcc-patches wrote:
LGTM
Edwin Lu 於 2023年9月7日 週四 01:52 寫道：
This patch adds types to riscv instructions that were added or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
gcc/ChangeLog:
* config
On 9/7/2023 6:17 AM, Jeff Law via Gcc-patches wrote:
On 9/6/23 18:42, Tsukasa OI via Gcc-patches wrote:
Looks okay to me but will need to resolve merge conflicts after commit
af88776caa20 ("RISC-V: Add support for 'XVentanaCondOps' reusing
'Zicond' support").
Sure. We allow trival updates
On 9/8/2023 4:56 PM, Jeff Law via Gcc-patches wrote:
On 9/8/23 12:16, Edwin Lu wrote:
This patch adds types to vector instructions that were added after or
were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
gcc/ChangeLog:
* config/riscv
On 9/10/2023 8:37 AM, Jeff Law via Gcc-patches wrote:
On 8/31/23 11:36, Edwin Lu wrote:
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the THEAD instructions to ensure that no insn is left
without a type
This patch adds types to the untyped zc instructions. Creates a new
types "pushpop" and "mvpair" for now
gcc/ChangeLog:
* config/riscv/riscv.md: Add "csr" type
* config/riscv/zc.md: Update types
Signed-off-by: Edwin Lu
---
Changes in V2:
-
-by: Edwin Lu
---
Changes in V2:
- Add types to insns missed by prev version
---
gcc/config/riscv/autovec-opt.md | 72 ++---
gcc/config/riscv/autovec.md | 52
2 files changed, 83 insertions(+), 41 deletions(-)
diff --git a/gcc/config/riscv
/newlib multilib
Additional extensions tested:
gcv
gc_zba_zbb_zbc_zbs
Edwin Lu (5):
RISC-V: Update Types for Vector Instructions
RISC-V: Add Types for Un-Typed zc Instructions
RISC-V: Add Types to Un-Typed Zicond Instructions
RISC-V: Add Types to Un-Typed Zicond Instructions
RISC-V: Remove
On 9/7/2023 6:19 AM, Jeff Law wrote:
On 9/6/23 11:50, Edwin Lu wrote:
This patch turns on the assert which ensures every instruction has type
that is not TYPE_UNKNOWN.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
And this is fine. But hold off
On 9/6/2023 4:33 PM, Kito Cheng wrote:
csr is kind of confusing, I would suggest something like `pushpop` and
`mvpair`.
Sounds good! I'll make the update.
Edwin
On 9/6/2023 4:23 PM, Kito Cheng wrote:
LGTM
Edwin Lu 於 2023年9月7日 週四 01:51 寫道：
This patch adds types to vector instructions that were added after
or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
gcc/ChangeLog
This patch turns on the assert which ensures every instruction has type
that is not TYPE_UNKNOWN.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.cc | 2 --
1 file changed, 2 deletions(-)
diff --git
This patch creates a new "zicond" type and updates all zicond instructions
with that type.
gcc/ChangeLog:
* config/riscv/riscv.md: Add "zicond" type
* config/riscv/zicond.md: Update types
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.md | 5 +++
This patch adds types to riscv instructions that were added or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
gcc/ChangeLog:
* config/riscv/riscv.md: Update types
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.md | 3 +++
1 file
This patch adds types to the untyped zc instructions. Creates a new
type "csr" for these instructions for now.
gcc/ChangeLog:
* config/riscv/riscv.md: Add "csr" type
* config/riscv/zc.md: Update types
Signed-off-by: Edwin Lu
---
gcc/config/riscv/riscv.md
-by: Edwin Lu
---
gcc/config/riscv/autovec-opt.md | 42 ++---
gcc/config/riscv/autovec.md | 28 +++---
2 files changed, 47 insertions(+), 23 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 1ca5ce97193
/newlib multilib
Additional extensions tested:
gcv
gc_zba_zbb_zbc_zbs
Edwin Lu (5):
RISC-V: Update Types for Vector Instructions
RISC-V: Add Types for Un-Typed zc Instructions
RISC-V: Add Types to Un-Typed Zicond Instructions
RISC-V: Add Types to Un-Typed Zicond Instructions
RISC-V: Remove
On 9/1/2023 11:02 AM, Jeff Law wrote:
On 8/31/23 11:32, Edwin Lu wrote:
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the riscv instructions to ensure that no insn is left
without a type attribute. Added
On 9/1/2023 6:15 AM, Jeff Law wrote:
On 8/31/23 17:01, Edwin Lu wrote:
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5...@gmail.com/
This patch updates the pic instructions to ensure that no insn is left
without a type attribute.
Tested
:
* config/riscv/pic.md: Update types
Signed-off-by: Edwin Lu
---
gcc/config/riscv/pic.md | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/pic.md b/gcc/config/riscv/pic.md
index da636e31619..cfaa670caf0 100644
--- a/gcc/config
:
* config/riscv/thead.md: Update types
Signed-off-by: Edwin Lu
---
gcc/config/riscv/thead.md | 7 +++
1 file changed, 7 insertions(+)
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 29f98dec3a8..6e63cb946e4 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config
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