The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013
Successfully tested and bootstrapped on x86-64.
commit 44430ef3d8ba75692efff5f6969d5610134566d3
Author: Vladimir N. Makarov
Date: Mon May 13 10:12:11 2024 -0400
[PR115013][LRA]: Modify register starvation
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114942
The patch was successfully bootstrapped and tested on x86-64, ppc64le,
aarch64.
commit 9585317f0715699197b1313bbf939c6ea3c1ace6
Author: Vladimir N. Makarov
Date: Fri May 10 09:15:50 2024 -0400
On 5/8/24 23:25, Li, Pan2 wrote:
Hi Vladimir,
Looks this patch results in some ICE in the rvv.exp of RISC-V backend,
feel free to ping me if more information is needed for reproducing.
= Summary of gcc testsuite =
| # of unexpected case / # of unique unexpected case
|gcc
The following patch is a fix for PR114810 from LRA side.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810
The patch was successfully bootstrapped and tested on x86_64, aarch64,
ppc64le.
commit dc859c1fcb6f3ad95022fb078c040907ef361e4c
Author: Vladimir N. Makarov
Date: Wed May 8 10:39:04
On 5/7/24 23:01, Lehua Ding wrote:
Hi Vladimir,
I'll send V3 patchs based on these comments. Note that these four
patches only support subreg liveness tracking and apply to IRA and LRA
pass. Therefore, no performance changes are expected before we support
subreg coalesce. There will be new
On 2/3/24 05:50, Lehua Ding wrote:
This patch apply the DF_LIVE_SUBREG to LRA pass. More changes were made
to the LRA than the IRA since the LRA will modify the DF data directly.
The main big changes are centered on the lra-lives.cc file.
gcc/ChangeLog:
* lra-coalesce.cc
On 2/3/24 05:50, Lehua Ding wrote:
This patch simple replace df_get_live_in to df_get_subreg_live_in
and replace df_get_live_out to df_get_subreg_live_out.
gcc/ChangeLog:
* ira-build.cc (create_bb_allocnos): Switch to DF_LIVE_SUBREG df data.
(create_loop_allocnos): Ditto.
I am resending this message as the previous one had one wrong response
email address "gcc-pat...@gcc.gnu.org"
Forwarded Message
Subject: Re: [PATCH V2 0/4] Add DF_LIVE_SUBREG data and apply to IRA
and LRA
Date: Wed, 1 May 2024 08:35:27 -0400
From: Vladim
On 4/29/24 08:59, Wilco Dijkstra wrote:
According to documentation, '^' should only have an effect during reload.
However ira-costs.cc treats it in the same way as '?' during early costing.
As a result using '^' can accidentally disable valid alternatives and cause
significant regressions (see
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114415
The patch was successfully tested and bootstrapped on x86_64, ppc64le,
aarch64.
commit fe305ca39930afc301cdd1f1143d540d1bfa2a48
Author: Vladimir N. Makarov
Date: Thu Apr 4 16:04:04 2024 -0400
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99829
The patch was successfully bootstrapped and tested on x86-64, ppc64le,
and aarch64.
commit 9c91f8a88b2db50c8faf70786d3cef27b39ac9fc
Author: Vladimir N. Makarov
Date: Tue Mar 19 16:57:11 2024 -0400
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113790
The patch was successfully bootstrapped and tested on x86-64,ppc64le,
and aarch64.
commit cebbaa2a84586a7345837f74a53b7a0263bf29ee
Author: Vladimir N. Makarov
Date: Fri Mar 8 14:48:33 2024 -0500
On 2/5/24 11:10, Jeff Law wrote:
On 2/5/24 00:01, Lehua Ding wrote:
For SPEC INT 2017, when using upstream GCC (whitout these patches),
I get a
coredump when training the peak case, so no data yet. The cause of
the core
dump still needs to be investigated.
Typo, SPEC INT 2017 -> SPEC FP
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113526
The patch was successfully bootstrapped and tested on x86-64, ppc64le,
and aarch64.
commit 5c617df410602d0e51d61c84d1ae7e9b3f51efa4
Author: Vladimir N. Makarov
Date: Thu Jan 25 14:41:17 2024 -0500
On 1/15/24 07:56, Maxim Kuvyrkov wrote:
Hi Vladimir,
Hi Jeff,
Richard and Alexander have reviewed this patch and [I assume] have no
further comments. OK to merge?
I trust Richard and Alexander therefore I did not do additional review
of the patches and have no any comment. Richard's or
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113354
The patch was tested on building MIPS target.
The patch was successfully tested and bootstrapped on x86-64, ppc64le,
aarch64.
commit 5f662bce28618ea5417f68a17d5c2d34b052ecb2
Author: Vladimir N. Makarov
Date:
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112918
The patch was successfully bootstrapped and tested on x86_64, aarch64,
ppc64le
commit 902a5931a1fbb04c65b48ca8b0f3827f6ff3b43e
Author: Vladimir N. Makarov
Date: Thu Jan 11 08:46:26 2024 -0500
[PR112918][LRA]:
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112918
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64.
The patch affects a sensitive part of LRA. So I will monitor that the
commit does not create serious failures on other targets. If
On 12/13/23 16:00, Alex Coplan wrote:
Hi,
In PR112906 we ICE because we try to use force_reg to reload an
auto-increment address, but force_reg can't do this.
With the aim of fixing the PR by supporting reloading arbitrary
addresses in pre-RA splitters, this patch generalizes
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112875
The patch was successfully tested and bootstrapped on x86-64 and ppc64le.
commit 48cb51827c9eb991b92014a3f59d31eb237ce03f
Author: Vladimir N. Makarov
Date: Fri Dec 8 15:37:42 2023 -0500
[PR112875][LRA]: Fix
On 12/7/23 03:39, Jakub Jelinek wrote:
On Thu, Dec 07, 2023 at 09:36:22AM +0100, Jakub Jelinek wrote:
So, one way to fix the LRA issue would be just to use
lra_insn_recog_data_len = index * 3U / 2;
if (lra_insn_recog_data_len <= index)
lra_insn_recog_data_len = index + 1;
basically
On 12/3/23 05:13, Richard Sandiford wrote:
[Gah. In my head I'd sent this a few weeks ago, but it turns out
that I hadn't even got to the stage of writing the changlog...]
LRA keeps track of the biggest mode for both hard registers and
pseudos. The updates assume that the modes are
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112445
The patch was successfully bootstrapped and tested on x86-64, aarch64,
ppc64le.
commit 1390bf52c17a71834a1766c0222e4f8a74efb162
Author: Vladimir N. Makarov
Date: Fri Dec 1 11:46:37 2023 -0500
[PR112445][LRA]:
On 11/22/23 06:14, Maxim Kuvyrkov wrote:
We currently have 3 implementations of print_hard_reg_set()
(all with the same name!) in ira-color.cc, ira-conflicts.cc, and
sel-sched-dump.cc. This patch generalizes implementation in
ira-color.cc, and uses it in all other places. The declaration
is
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112610
The patch was successfully tested and bootstrapped on x86-64.
commit 95f61de95bbcc2e4fb7020e27698140abea23788
Author: Vladimir N. Makarov
Date: Wed Nov 22 09:01:02 2023 -0500
[IRA]: Fix using undefined dump
On 11/16/23 21:06, Lehua Ding wrote:
Hi Vladimir,
Thank you so much for your review. Based on your comments, I feel like
there are a lot of issues, especially the long compile time issue. So
I'm going to reorganize and refactor the patches so that as many of
them as possible can be
On 11/12/23 07:08, Lehua Ding wrote:
This patch relax the subreg track capability to all subreg registers.
The patch is ok for me when general issues I mentioned in my first email
and the issue given below are fixed.
gcc/ChangeLog:
* ira-build.cc (get_reg_unit_size): New.
On 11/12/23 07:08, Lehua Ding wrote:
This patch changes the previous way of creating a copy between allocnos to
objects.
gcc/ChangeLog:
* ira-build.cc (find_allocno_copy): Removed.
(find_object): New.
(ira_create_copy): Adjust.
(add_allocno_copy_to_list):
On 11/12/23 07:08, Lehua Ding wrote:
gcc/ChangeLog:
* hard-reg-set.h (struct HARD_REG_SET): New shift operator.
* ira-build.cc (ira_create_object): Adjust.
(find_object): New.
(find_object_anyway): New.
(ira_create_allocno): Adjust.
(get_range):
On 11/12/23 07:08, Lehua Ding wrote:
This patch switch the use of live_reg data to live_subreg data.
gcc/ChangeLog:
* ira-build.cc (create_bb_allocnos): Switch.
Switch to what? Although from the patch itself someone can figure it
out, you should write it in the changelog entry.
On 11/14/23 12:18, Vladimir Makarov wrote:
On 11/14/23 03:38, Lehua Ding wrote:
This is perfectly fine, the code inside the live_subreg problem has a
branch that goes through similar logic to live_reg if it finds no
subreg inside the program. Then when the optimization level is less
On 11/14/23 03:38, Lehua Ding wrote:
This is perfectly fine, the code inside the live_subreg problem has a
branch that goes through similar logic to live_reg if it finds no
subreg inside the program. Then when the optimization level is less
than 2, it doesn't track the subreg. By the way,
On 11/14/23 04:03, Richard Biener wrote:
I suggest you farm bugzilla for the compile-time-hog / memory-hog testcases.
I do have a set of "large" testcases. Scanning results points at
PRs 36262, 37448, 39326, 69609 all having RA in the 20% area at
-O0 -g.
It's also a good idea to take say
On 11/12/23 09:52, Richard Sandiford wrote:
SME has various instructions that require aligned register tuples.
However, the associated tuple modes are already widely used and do
not need to be aligned in other contexts. It therefore isn't
appropriate to force alignment in
On 11/12/23 07:08, Lehua Ding wrote:
This patch adds a live_subreg problem to extend the original live_reg to
track the liveness of subreg. We will only try to trace speudo registers
who's mode size is a multiple of nature size and eventually a small portion
of the inside will appear to use
On 11/12/23 07:08, Lehua Ding wrote:
V3 Changes:
1. fix three ICE.
2. rebase
Hi,
These patchs try to support subreg coalesce feature in
register allocation passes (ira and lra).
I've started review of v3 patches and here is my initial general
criticism of your patches:
* Absence
On 11/12/23 07:01, Lehua Ding wrote:
Thanks for the specint performance data. I'll do my best to get the
compile time and memory issues fixed. I'm very curious to know if the
way used to solve the subreg coalesce problem makes sense to you?
If it works, it is ok for me. There is always a
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112337
The patch was successfully bootstrapped an tested on x86-64, ppc64le,
and aarch64.
commit b3d1d30eeed67c78e223c146a464d2fdd1dde894
Author: Vladimir N. Makarov
Date: Fri Nov 10 11:14:46 2023 -0500
[IRA]: Check
On 11/7/23 22:47, Lehua Ding wrote:
Lehua Ding (7):
ira: Refactor the handling of register conflicts to make it more
general
ira: Add live_subreg problem and apply to ira pass
ira: Support subreg live range track
ira: Support subreg copy
ira: Add all nregs >= 2 pseudos to
This is one more patch for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110215
The patch was successfully tested and bootstrapped on x86-64, aarch64,
ppc64le.
commit df14f1c0582cd6742a37abf3a97f4c4bf0caf864
Author: Vladimir N. Makarov
Date: Thu Nov 9 08:51:15 2023 -0500
[IRA]: Fixing
On 10/31/23 18:51, Edwin Lu wrote:
genattr.cc currently generates insn-attr.h with the following structure:
#if CPU_UNITS_QUERY
extern int get_cpu_unit_code (const char *);
extern int cpu_unit_reservation_p (state_t, int);
#endif
extern bool insn_has_dfa_reservation_p (rtx_insn *);
however
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111971
Successfully bootstrapped and tested on x86-64, aarch64, pp64le.
commit df111406b4ea1fe2890e94d51655e571cf260d29
Author: Vladimir N. Makarov
Date: Tue Oct 31 10:54:43 2023 -0400
[RA]: Fixing LRA cycling for
The following patch fixes i686 bootstrap failure because of my recent
patch:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112107
commit 7361b49d7fa3624cb3f1f825a22607d9d31986e5
Author: Vladimir N. Makarov
Date: Fri Oct 27 14:50:40 2023 -0400
[RA]: Fixing i686 bootstrap failure because
The following patch fixes one aarch64 GCC test failure resulted from my
previous patch dealing with reg equivalences.
The patch was successfully bootstrapped and tested on x86-64, aarch64,
ppc64le.
commit 9b03e1d20c00dca215b787a5e959db473325b660
Author: Vladimir N. Makarov
Date: Fri Oct
On 10/27/23 09:56, Christophe Lyon wrote:
Hi Vladimir,
On Thu, 26 Oct 2023 at 16:00, Vladimir Makarov wrote:
This is the second attempt to improve RA cost calculation for pseudos
with equivalences. The patch explanation is in the log message.
The patch was successfully bootstrapped
This is the second attempt to improve RA cost calculation for pseudos
with equivalences. The patch explanation is in the log message.
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64le. The patch was also benchmarked on x86-64 spec2017.
specfp2017
On 10/18/23 09:37, Richard Sandiford wrote:
Vlad, is it OK if I backport the patch below to fix
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111528 ? Jakub has
given a conditional OK on irc.
Ok. It should be safe. I don't expect any issues because of this.
On 10/3/23 10:07, Surya Kumari Jangala wrote:
ira: Scale save/restore costs of callee save registers with block frequency
In assign_hard_reg(), when computing the costs of the hard registers, the
cost of saving/restoring a callee-save hard register in prolog/epilog is
taken into
I've got a lot of complaints about my recent patch to improve equiv cost
calculation. So I am reverting the patch.
commit 8552dcd8e4448c02fe230662093756b75dd94399
Author: Vladimir N. Makarov
Date: Thu Sep 28 11:53:51 2023 -0400
Revert "[RA]: Improve cost calculation of pseudos with
I've pushed the following patch. The explanation is in commit message.
The patch was successfully bootstrapped on x86-64.
commit 0c8ecbcd3cf7d7187d2017ad02b663a57123b417
Author: Vladimir N. Makarov
Date: Thu Sep 28 09:41:18 2023 -0400
[RA]: Add flag for checking IRA in progress
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111497
The patch was successfully tested and bootstrapped on x86-64 and aarch64.
commit 3c23defed384cf17518ad6c817d94463a445d21b
Author: Vladimir N. Makarov
Date: Mon Sep 25 16:19:50 2023 -0400
[PR111497][LRA]: Copy
On 9/22/23 06:56, Hongyu Wang wrote:
Like base_reg_class, INDEX_REG_CLASS also does not support backend insn.
Add index_reg_class with insn argument for lra/reload usage.
gcc/ChangeLog:
* addresses.h (index_reg_class): New wrapper function like
base_reg_class.
*
On 9/22/23 06:56, Hongyu Wang wrote:
From: Kong Lingling
Current reload infrastructure does not support selective base_reg_class
for backend insn. Add new macros with insn parameters to base_reg_class
for lra/reload usage.
gcc/ChangeLog:
* addresses.h (base_reg_class): Add insn
On 9/15/23 10:48, Vladimir Makarov wrote:
On 9/14/23 06:45, Surya Kumari Jangala wrote:
ira: Consider save/restore costs of callee-save registers [PR110071]
In improve_allocation() routine, IRA checks for each allocno if spilling
any conflicting allocnos can improve the allocation
On 9/14/23 06:45, Surya Kumari Jangala wrote:
ira: Consider save/restore costs of callee-save registers [PR110071]
In improve_allocation() routine, IRA checks for each allocno if spilling
any conflicting allocnos can improve the allocation of this allocno.
This routine computes the cost
I've committed the following patch. The reason for this patch is
explained in its commit message.
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64le.
commit 3c834d85f2ec42c60995c2b678196a06cb744959
Author: Vladimir N. Makarov
Date: Thu Sep 14 10:26:48 2023
On 9/10/23 00:49, Hongyu Wang wrote:
Vladimir Makarov via Gcc-patches 于2023年9月9日周六 01:04写道：
On 8/31/23 04:20, Hongyu Wang wrote:
@@ -2542,6 +2542,8 @@ the code of the immediately enclosing expression
(@code{MEM} for the top level
of an address, @code{ADDRESS} for something that occurs
On 8/31/23 04:20, Hongyu Wang wrote:
@@ -2542,6 +2542,8 @@ the code of the immediately enclosing expression
(@code{MEM} for the top level
of an address, @code{ADDRESS} for something that occurs in an
@code{address_operand}). @var{index_code} is the code of the corresponding
index
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111225
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64le.
commit f7bca44d97ad01b39f9d6e7809df7bf517eeb2fb
Author: Vladimir N. Makarov
Date: Thu Sep 7 09:59:10 2023 -0400
[LRA]:
On 9/7/23 02:23, Uros Bizjak wrote:
On Wed, Sep 6, 2023 at 9:43 PM Vladimir Makarov wrote:
On 9/1/23 05:07, Hongyu Wang wrote:
I think the approach proposed by Intel developers is better. In some way
we already use such approach when we pass memory mode to get the base
reg class
On 9/1/23 05:07, Hongyu Wang wrote:
Uros Bizjak via Gcc-patches 于2023年8月31日周四 18:16写道：
On Thu, Aug 31, 2023 at 10:20 AM Hongyu Wang wrote:
From: Kong Lingling
Current reload infrastructure does not support selective base_reg_class
for backend insn. Add insn argument to base_reg_class for
On 8/17/23 07:19, senthilkumar.selva...@microchip.com wrote:
On Wed, 2023-08-16 at 12:13 -0400, Vladimir Makarov wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the
content is safe
The attached patch fixes recently found wrong insn removal in LRA port
for AVR
The following patch fixes a problem with allocating the same stack slots
to conflicting pseudos. The problem exists only for AVR LRA port.
The patch was successfully bootstrapped and tested on x86-64 and aarch64.
commit c024867d1aa9d465e0236fc9d45d8e1d4bb6bd30
Author: Vladimir N. Makarov
The attached patch fixes recently found wrong insn removal in LRA port
for AVR.
The patch was successfully tested and bootstrapped on x86-64 and aarch64.
commit 748a77558ff37761faa234e19327ad1decaace33
Author: Vladimir N. Makarov
Date: Wed Aug 16 09:13:54 2023 -0400
[LRA]: Spill
The patch fixes a failure of building aarch64 port with my yesterday patch.
The patch was successfully bootstrapped on x86-64 and aarch64.
commit c4760c0161f92b92361feba11836e3d066bb330c
Author: Vladimir N. Makarov
Date: Mon Aug 14 16:06:27 2023 -0400
[LRA]: Process output stack pointer
On 8/14/23 14:37, Prathamesh Kulkarni wrote:
On Mon, 14 Aug 2023 at 06:39, Vladimir Makarov via Gcc-patches
wrote:
The following patch fixes useless asserts in my latest patch
implementing output stack pointer reloads.
Hi Vladimir,
It seems that this patch caused the following ICE
The following patch fixes useless asserts in my latest patch
implementing output stack pointer reloads.
commit 18b417fe1a46d37738243267c1f559cd0acc4886
Author: Vladimir N. Makarov
Date: Sun Aug 13 20:54:58 2023 -0400
[LRA]: Fix asserts for output stack pointer reloads
The patch
Sorry, I had some problems with email. Therefore there are email
duplication and they were sent to g...@gcc.gnu.org instead of
gcc-patches@gcc.gnu.org
On 8/9/23 16:54, Vladimir Makarov wrote:
On 8/9/23 07:15, senthilkumar.selva...@microchip.com wrote:
Hi,
After turning on FP ->
On 8/7/23 09:18, Richard Biener wrote:
On Wed, 2 Aug 2023, Richard Biener wrote:
On Mon, 31 Jul 2023, Jeff Law wrote:
On 7/31/23 04:54, Richard Biener via Gcc-patches wrote:
On Tue, 25 Jul 2023, Richard Biener wrote:
The following applies a micro-optimization to find_hard_regno_for_1,
The following patch fixes a problem found by LRA port for avr target.
The problem description is in the commit message.
The patch was successfully bootstrapped and tested on x86-64 and aarch64.
commit abf953042ace471720c1dc284b5f38e546fc0595
Author: Vladimir N. Makarov
Date: Fri Aug 4
On 8/1/23 01:20, Surya Kumari Jangala wrote:
Ping
Sorry for delay with the answer. I was on vacation.
On 21/07/23 3:43 pm, Surya Kumari Jangala via Gcc-patches wrote:
The improve_allocation() routine does not update the
allocated_hardreg_p[] array after an allocno is assigned a register.
On 7/25/23 09:40, Richard Biener wrote:
The following removes the code checking whether a noop copy
is between something involved in the return sequence composed
of a SET and USE. Instead of checking for this special-case
the following makes us only ever remove noop copies between
pseudos -
The following patch fixes sparc solaris bootstrap. The explanation of
the patch is in the commit message.
The patch was successfully bootstrap on x86-64, aarch64, and sparc64
solaris.
commit d17be8f7f36abe257a7d026dad61e5f8d14bdafc
Author: Vladimir N. Makarov
Date: Fri Jul 21 20:28:50
On 7/20/23 16:45, Rainer Orth wrote:
Hi Vladimir,
The following patch is necessary for porting avr to LRA.
The patch was successfully bootstrapped and tested on x86-64, aarch64, and
ppc64le.
There is still avr poring problem with reloading of subreg of frame
pointer. I'll address it later
The following patch improves code for avr LRA port. More explanation
for the patch can be found in the commit message.
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64le.
commit 4b8878fbf7b74ea5c3405c9f558df0517036f131
Author: Vladimir N. Makarov
Date: Thu
The following patch is necessary for porting avr to LRA.
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64le.
There is still avr poring problem with reloading of subreg of frame
pointer. I'll address it later on this week.
commit
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109520
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64le.
commit b175b4887f928118af997f6d4d75097a64dcec5d
Author: Vladimir N. Makarov
Date: Thu Jul 13 10:42:17 2023 -0400
On 7/12/23 07:05, senthilkumar.selva...@microchip.com wrote:
Hi,
I've been spending some (spare) time trying to get LRA working
for the avr target.
Thank you for addressing this problem.
The code you changing is very sensitive and was a source of multiple PRs
in the past. But I
On 7/12/23 12:22, Richard Sandiford wrote:
Vladimir Makarov writes:
On 7/12/23 06:07, Richard Sandiford wrote:
Vladimir Makarov via Gcc-patches writes:
diff --git a/gcc/lra-assigns.cc b/gcc/lra-assigns.cc
index 73fbef29912..2f95121df06 100644
--- a/gcc/lra-assigns.cc
+++ b/gcc/lra
On 7/12/23 06:07, Richard Sandiford wrote:
Vladimir Makarov via Gcc-patches writes:
diff --git a/gcc/lra-assigns.cc b/gcc/lra-assigns.cc
index 73fbef29912..2f95121df06 100644
--- a/gcc/lra-assigns.cc
+++ b/gcc/lra-assigns.cc
@@ -1443,10 +1443,11 @@ assign_by_spills (void
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110372
The patch was successfully bootstrapped and tested on x86-64.
commit 1f7e5a7b91862b999aab88ee0319052aaf00f0f1
Author: Vladimir N. Makarov
Date: Fri Jul 7 09:53:38 2023 -0400
LRA: Refine reload pseudo class
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110215
The patch was successfully tested and bootstrapped on x86-64, aarch64,
and ppc64le.
It is difficult to make a stable test for the PR. So there is not test
in the patch.
commit
On 6/7/23 12:20, Jeff Law wrote:
On 6/7/23 09:35, Vladimir Makarov via Gcc-patches wrote:
The following patch fixes
-ENOPATCH
Sorry, here is the patch.
commit 08ca31fb27841cb7f3bff7086be6f139136be1a7
Author: Vladimir N. Makarov
Date: Wed Jun 7 09:51:54 2023 -0400
RA: Constrain
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109541
The patch was successfully bootstrapped and tested on x86-64, aarcha64,
and ppc64le.
The following patch fixes an LRA bug triggered by switching H8300 target
from reload to LRA. The description of the problem is in the commit
message.
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64le.
commit 30038a207c10a2783fa2695b62c7c8458ef05e73
Author:
On 5/17/23 02:57, liuhongt wrote:
r14-172-g0368d169492017 replaces GENERAL_REGS with NO_REGS in cost
calculation when the preferred register class are not known yet.
It regressed powerpc PR109610 and PR109858, it looks too aggressive to use
NO_REGS when mode can be allocated with GENERAL_REGS.
On 5/5/23 12:59, Richard Sandiford wrote:
This patch follows on from g:9f635bd13fe9e85872e441b6f3618947f989909a
("the previous patch"). To start by quoting that:
If an insn requires two operands to be tied, and the input operand dies
in the insn, IRA acts as though there were a copy from the
On 4/19/23 20:46, liuhongt via Gcc-patches wrote:
1547 /* If this insn loads a parameter from its stack slot, then it
1548 represents a savings, rather than a cost, if the parameter is
1549 stored in memory. Record this fact.
1550
1551 Similarly if we're loading other constants
The following patch fixes test failure of 20030222-1.c on moxie port.
But the problem can occur on other targets. The patch actually
implements the old reload approach for the test case.
The patch was successfully tested and bootstrapped on x86-64, aarch64,
and ppc64le.
commit
On 4/4/23 21:29, Jeff Law wrote:
On 4/3/23 23:13, liuhongt via Gcc-patches wrote:
There's a potential performance issue when backend returns some
unreasonable value for the mode which can be never be allocate with
reg class.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for
This is one more patch for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109052
The patch adds trying commutative operands exchange for recently
implemented combining secondary memory reload and original insn:
The patch was successfully bootstrapped and tested on x86_64.
commit
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109137
The patch was successfully bootstrapped and tested on x86-64.
commit 81d762cbec9685c2f2571da21d48f42c42eff33b
Author: Vladimir N. Makarov
Date: Wed Mar 22 12:33:11 2023 -0400
LRA: Do not repeat inheritance
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109052
The patch was successfully bootstrapped and tested on x86-64, i686,
aarch64, and ppc64le.
commit 57688950b9328cbb4a9c21eb3199f9132b5119d3
Author: Vladimir N. Makarov
Date: Fri Mar 17 08:58:58 2023 -0400
LRA:
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108999
The patch was successfully bootstrapped and tested on i686, x86-64,
aarch64, and ppc64 be/le.
commit 3c75631fc09a22f2513fab80ef502c2a8b0f9121
Author: Vladimir N. Makarov
Date: Thu Mar 9 08:41:09 2023 -0500
The following patch is for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90706
The patch was successfully bootstrapped and tested on i686, x86-64,
aarch64, ppc64le.
commit 23661e39df76e07fb4ce1ea015379c7601d947ef
Author: Vladimir N. Makarov
Date: Thu Mar 2 16:29:05 2023 -0500
IRA: Use
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108774
The patch was successfully bootstrapped and tested on i686, x86_64, and
aarch64.
commit a33e3dcbd15e73603796e30b5eeec11a0c8bacec
Author: Vladimir N. Makarov
Date: Mon Feb 13 16:05:04 2023 -0500
RA: Clear
The following patch should solve
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108754
The patch simply switches off a new optimization for targets using the
old reload pass.
The patch was successfully bootstrapped on x86-64.
commit 7757567358a84c3774cb972350bd7ea299daaa8d
Author: Vladimir
The following patch is for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108500
The patch improves compilation speed. Compilation time of the biggest
test in the PR decreases from 1235s to 709s.
The patch was successfully bootstrapped on x86-64.
commit
This is another try to solve
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103541
The patch was successfully bootstrapped (--enable-languages=all) and
tested on x86, x86-64, aarch64
commit 1ad898d18904ac68432ba9b8ffa2b083d007cc2d
Author: Vladimir N. Makarov
Date: Thu Feb 9 15:18:48 2023
On 2/7/23 22:48, Andrew Pinski wrote:
On Tue, Feb 7, 2023 at 6:08 AM Vladimir Makarov via Gcc-patches
wrote:
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103541
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64le.
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