would fail without Patch 2/3 please don't add them.
Ramana
Best regards,
Thomas
-Original Message-
From: Richard Earnshaw
Sent: Wednesday, January 14, 2015 2:53 PM
To: Thomas Preud'homme; Tony Wang; gcc-patches@gcc.gnu.org
Cc: Ramana Radhakrishnan
Subject: Re: [PATCH 3/3, ARM, libgcc
On 13/01/15 21:01, Andrew Stubbs wrote:
On 12/01/15 13:50, Ramana Radhakrishnan wrote:
In principle ok, but I'd like a comment in there explaining why we've
done this. Can you also post under what configurations these have been
tested ?
Is this better?
I tested it by running the vect.exp
On Mon, Jan 12, 2015 at 2:29 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Now with patch attached
Kyrill
On 12/01/15 14:27, Kyrill Tkachov wrote:
Hi all,
In this PR we ICE when compiling with -mtune=xscale. The ICE is a
segfault in xscale_sched_adjust_cost.
The root cause is that
On Wed, Jan 14, 2015 at 10:20 AM, Thomas Preud'homme
thomas.preudho...@arm.com wrote:
When compiling for size, live high registers are not saved in function prolog
in ARM backend in Thumb mode. The problem comes from
arm_conditional_register_usage setting call_used_regs for all high register
On 14/01/15 10:14, Hale Wang wrote:
Hi,
This patch is tuned particularly for benchmark performance on cortex-m7.
Tested with GCC regression test, no regressions. Is it ok for trunk?
BR,
Hale Wang
gcc/ChangeLog
2014-12-24 Hale Wang hale.w...@arm.com
* config/arm/arm.c: Tune the
On 12/01/15 20:15, Philipp Tomsich wrote:
---
gcc/ChangeLog-2014| 10 ++
gcc/config/arm/arm-cores.def | 1 +
gcc/config/arm/arm-tables.opt | 3 +++
gcc/config/arm/arm-tune.md| 3 ++-
gcc/config/arm/arm.c | 22 ++
On Sun, Jan 11, 2015 at 9:55 PM, Andreas Tobler andreast-l...@fgznet.ch wrote:
Hi,
I have here a possible way to make the enum_9.f90 and the enum_10.f90 work
under arm*-*-freebsd*. The solution for enum_9.f90 is straight forward. But
the one for enum_10.f90 requires a reordering of the
On 12/01/15 20:15, Philipp Tomsich wrote:
---
gcc/config/aarch64/aarch64.md | 2 +-
gcc/config/arm/types.md | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 1f6b1b6..98f4f30 100644
---
On Thu, Jan 8, 2015 at 8:51 PM, Andreas Tobler andreast-l...@fgznet.ch wrote:
On 08.01.15 17:27, Richard Earnshaw wrote:
On 29/12/14 18:44, Andreas Tobler wrote:
All,
here is the third attempt to support ARM with FreeBSD.
In the meantime we found another issue in the unwinder where I had
On 19/11/14 02:43, Joey Ye wrote:
Current thumb2 -Os generates suboptimal code for following tail call case:
int f4(int b, int a, int c, int d);
int g(int a, int b, int c, int d)
{ return f4(b, a, c, d); }
arm-none-eabi-gcc -Os -mthumb -mcpu=cortex-m3 test.c
push
{r4, lr}
mov r4, r1
mov r1,
Sorry about the slow response- have been on holiday and still catching
up on email.
On 12/01/15 13:16, Andrew Stubbs wrote:
Ping.
On 23/12/14 16:46, Andrew Stubbs wrote:
On 03/12/14 15:03, Andrew Stubbs wrote:
The tools have always allowed us to drop down the arch to
march=armv5te along
On Thu, Dec 4, 2014 at 9:19 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
On 02/12/14 22:58, Ramana Radhakrishnan wrote:
On Tue, Nov 11, 2014 at 11:55 AM, Kyrill Tkachov kyrylo.tkac...@arm.com
wrote:
Hi all,
This is the arm implementation of the macro fusion hook.
It tries to fuse
On Thu, Dec 11, 2014 at 9:34 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
While looking in this area on other business I noticed we could be using the
names R0_REGNUM
and R1_REGNUM when creating those REG rtxs since it's a bit more descriptive
that just 0 and 1.
Tested
On Tue, Sep 23, 2014 at 4:07 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
Some intrinsics had the wrong name (inconsistent with the NEON intrinsics
spec). This patch fixes that and adds the vrndx_f32 and vrndxq_f32
intrinsics that were missing.
These map down to vrintx.f32 NEON
On Mon, Dec 8, 2014 at 11:24 AM, Bernd Edlinger
bernd.edlin...@hotmail.de wrote:
Hi Kyrill,
Hi all,
As the subject says, this just fixes a typo in the fprofile-generate
option name and rewords the text in the next sentence a bit.
Ok to commit?
Thanks,
Kyrill
I think this kind of
On 20/11/14 11:54, Tom de Vries wrote:
Richard,
This patch fixes PR63718, which currently breaks Thumb1 bootstrap.
The problem is that in Thumb1 mode, we emit the epilogue in RTL, but the last
insn - epilogue_insns - does not accurately model the corresponding insns
emitted in the asm file.
On 29/11/14 06:50, Chen Shanyao wrote:
I've backported this fix to 4.8 4.9 branch.
These patches have been tested for armeb-none-eabi-gcc/g++ with qemu,
and both the test results were ok.
The Changelog should mention all authors of the original patches i.e.
include my name.
Otherwise
On Tue, Dec 2, 2014 at 2:01 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
On 23/09/14 09:27, James Greenhalgh wrote:
On Mon, Sep 15, 2014 at 11:56:03AM +0100, Andrew Stubbs wrote:
On 15/09/14 10:46, Richard Earnshaw wrote:
Hmm, I wonder if arm_override_options should reject neon + (arch
On Fri, Nov 21, 2014 at 6:44 PM, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
The following patch-series adds optimized support for the APM X-Gene 1
by providing a cost-model and pipeline-model. The pipeline-model has a
few long reservation-chains, but looking at the stats for
On Fri, Nov 21, 2014 at 6:44 PM, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
To keep this change separately buildable from the pipeline model,
this patch directs the APM XGene-1 to use the generic scheduling
model.
---
gcc/ChangeLog| 8 +++
On Fri, Nov 21, 2014 at 6:44 PM, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
---
gcc/ChangeLog | 6 +
gcc/config/aarch64/aarch64.md | 3 +-
gcc/config/arm/xgene1.md | 532
++
3 files changed, 540
CCing release maintainers as well as they need to approve this
backport if Vlad is happy with it.
Vlad - is this ok to go back as it fixes a bug for ARM in the 4.9 tree
that came up in building bits of debian.
Ramana
On Mon, Dec 1, 2014 at 5:24 PM, Renlin Li renlin...@arm.com wrote:
On
On Tue, Nov 11, 2014 at 11:55 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This is the arm implementation of the macro fusion hook.
It tries to fuse movw+movt operations together. It also tries to take lo_sum
RTXs into account since those generate movt instructions as well.
intend to backport the same to the 4.9 branch as the issue exists there
too and this is just in the configury and build of the baremetal toolchain.
regards
Ramana
2014-11-28 Ramana Radhakrishnan ramana.radhakrish...@arm.com
* config/arm/t-aprofile (MULTILIB_MATCHES): New entry
On Thu, Nov 13, 2014 at 5:25 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch adds support for the Cortex-A17 processor to the arm backend.
Cortex-A17 is an ARMv7ve core with the same architectural features as the
Cortex-A7, A12 and A15 cores.
The -m{tune, cpu}=cortex-a17
On Thu, Nov 13, 2014 at 5:25 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
The Cortex-A12 very close to the Cortex-A17 and this patch updates the
tuning struct
parameters to match the Cortex-A17 ones.
This has improved performance in a number of benchmarks that I tried.
The
5:33 PM
To: Thomas Preud'homme
Cc: Tony Wang; gcc-patches@gcc.gnu.org; d...@debian.org; aph-
g...@littlepinkcloud.com; Richard Earnshaw; Ramana Radhakrishnan;
libstd...@gcc.gnu.org
Subject: Re: [Patch, ARM, ping1] Fix PR target/56846
On 26/11/14 17:23 -, Thomas Preud'homme wrote:
Ping?
I'm
On Thu, Nov 13, 2014 at 4:03 PM, Thomas Preud'homme
thomas.preudho...@arm.com wrote:
[Taking over Tony's patch]
Ping?
Best regards,
Thomas
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
ow...@gcc.gnu.org] On Behalf Of Tony Wang
Sent: Thursday,
, 2014 3:31 PM
To: gcc-patches@gcc.gnu.org; Ramana Radhakrishnan; Richard Earnshaw
Subject: [PATCH][ARM] Fix PR59593/PR63742: arm *movhi_insn_arch4
pattern for big-endian
Currently, constant pool entries for QImode, HImode and SImode values
are filled as 32-bit quantities. This works fine
On Tue, Nov 18, 2014 at 10:40 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
Following up from adding Cortex-A17 support this patch adds a big.LITTLE
option cortex-a17.cortex-a7.
Similar to the existing cortex-a15.cortex-a7 support we schedule for
Cortex-A7 and make the other
On Wed, Oct 29, 2014 at 10:20 AM, Jiong Wang jiong.w...@arm.com wrote:
On 26/08/14 13:36, Richard Earnshaw wrote:
On 29/07/14 15:49, Jiong Wang wrote:
test done
===
no regression on the full toolchain test on arm-none-eabi.
ok to install?
Hmm, I think this is wrong for DF mode. The
On Wed, Nov 19, 2014 at 2:54 PM, Christian Bruel christian.br...@st.com wrote:
On 11/19/2014 03:18 PM, Ramana Radhakrishnan wrote:
On Wed, Nov 19, 2014 at 1:24 PM, Christian Bruel christian.br...@st.com
wrote:
I think I missed the stage3, Anyway would it be OK for stage1 when it
reopens
On 27/11/14 11:09, Kyrill Tkachov wrote:
On 27/11/14 08:52, Ramana Radhakrishnan wrote:
On Thu, Nov 13, 2014 at 5:25 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch adds support for the Cortex-A17 processor to the arm backend.
Cortex-A17 is an ARMv7ve core with the same
?
regards
Ramana
2014-11-20 Ramana Radhakrishnan ramana.radhakrish...@arm.com
PR target/59593
* config/arm/arm.md (*movhi_insn): Use right formatting
for immediate.
Index: gcc/ChangeLog
===
--- gcc
On Wed, Nov 19, 2014 at 9:42 PM, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
Here's an updated patch with Kyrill's and Andrew's comments integrated.
I left the file in the config/arm-directory, as XGene-family is capable of
executing ARMv7 and we will wire this into the 32bit
On 14/11/14 15:12, Maxim Kuvyrkov wrote:
On Nov 14, 2014, at 8:38 AM, Jeff Law l...@redhat.com wrote:
On 10/20/14 22:06, Maxim Kuvyrkov wrote:
Hi,
Ramana, this change requires benchmarking, which I can't easily do
at
the moment. I would appreciate any benchmarking results that you can
On 19/11/14 09:29, Yangfei (Felix) wrote:
Sorry for missing the point. It seems to me that 't2' here will conflict with
condition of the pattern *movhi_insn_arch4:
TARGET_ARM
arm_arch4
(register_operand (operands[0], HImode)
|| register_operand (operands[1],
On Wed, Nov 19, 2014 at 1:24 PM, Christian Bruel christian.br...@st.com wrote:
I think I missed the stage3, Anyway would it be OK for stage1 when it
reopens ?
Since you submitted this well during stage1 and given that these
patches address comments from earlier in the review process we should
A testcase is added for all targets as I think it's a middle-end
issue. And sorry for not being able to simplify it.
arm-none-eabi has been test on the model, no new issues. bootstrapping
and regression tested on x86, no new issues.
Is it Okay to commit?
Yes. Thanks very much for working on
On 06/11/14 08:35, Yangfei (Felix) wrote:
The idea is simple: Use movw for certain const source operand instead of
ldrh. And exclude the const values which cannot be handled by
mov/mvn/movw.
I am doing regression test for this patch. Assuming no issue pops up,
OK for trunk?
On Wed, Nov 12, 2014 at 4:38 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This is a much-delayed respin of the patch in response to Richards feedback
at:
http://gcc.gnu.org/ml/gcc-patches/2014-05/msg00068.html
We now let recursion do its magic and just add the cost of the
On Wed, Nov 12, 2014 at 5:08 PM, James Greenhalgh
james.greenha...@arm.com wrote:
Hi,
I was taking a look at fixing the issues in the ARM back-end exposed
by Marc Glisse's patch in [1], and hoped to fix them by adapting the
patch recently commited by Tejas ([2]).
As I looked, I realised
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
As part of some wider cleanup I'd like to do to ARM's Neon Builtin
infrastructure, my first step will be to remove the Magic Words used
to decide which variant of an instruction should be emitted.
The Magic Words interface allows a single
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
If we want to move all the code relating to builtin initialisation and
expansion to a common file, we must share the processor flags with that
common file.
This patch pulls those definitions out to config/arm/arm-protos.h
Bootstrapped and
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
The config/arm/arm.c file has always seemed a worrying size to me.
This patch pulls out the builtin related code to its own file. I think
this will be a good idea as we move forward. It seems a more sensible
separation of concerns. There are no
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
These macros can always be defined as a base case of VAR1 and a recursive
case of VARn-1. At the moment, the body of VAR1 is duplicated to each
macro.
This patch makes that change.
Regression tested on arm-none-linux-gnueabihf with no issues.
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
Now we have everything we need to start keeping track of the correct
qualifiers for each Neon builtin class in the arm back-end.
Some of the ARM Neon itypes are redundant when mapped to the qualifiers
framework. For now, don't change these, we
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
The poly types end up going through the default mangler, but only
sometimes.
We don't want to change the mangling for poly types with the next patch in
this series, so add a test which should pass before and after.
I've checked that the new
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
This patch wires up builtin initialisation similar to the AArch64 backend,
making use of the qualifiers arrays to decide on types for each builtin
we hope to initialise.
We could take an old snapshot of the qualifiers code from AArch64, but as
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
This final patch clears up the remaining data structures which we no
longer have any use for...
* _QUALIFIERS macros which do not name a distinct pattern of
arguments/return types.
* The neon_builtin_type_mode enum is not needed, we can
On Mon, Nov 17, 2014 at 5:06 AM, Hale Wang hale.w...@arm.com wrote:
Hi,
Refer to the previous small multiply patch (r217175).
The conditions in the small multiply test cases are not restrictive enough.
If forcing the march=armv4t/armv5t, these cases will fail.
These cases can be used only
On Mon, Nov 10, 2014 at 3:02 PM, Christophe Lyon
christophe.l...@linaro.org wrote:
On 30 October 2014 23:02, Christophe Lyon christophe.l...@linaro.org wrote:
On 29 October 2014 16:28, Ramana Radhakrishnan
ramana@googlemail.com wrote:
On Wed, Oct 29, 2014 at 3:26 PM, Christophe Lyon
On Thu, Nov 13, 2014 at 9:42 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
Following the trend in i386 and alpha, this patch uses std::swap to perform
swapping of values in the arm backend instead of declaring temporaries.
Tested and bootstrapped on arm-none-linux-gnueabihf.
Ok
On 18/11/14 11:02, Yangfei (Felix) wrote:
On 06/11/14 08:35, Yangfei (Felix) wrote:
The idea is simple: Use movw for certain const source operand
instead of
ldrh. And exclude the const values which cannot be handled by
mov/mvn/movw.
I am doing regression test for this patch.
On Tue, Nov 18, 2014 at 11:51 AM, Yangfei (Felix) felix.y...@huawei.com wrote:
Ping again? Any comment please?
Pinging daily is only going to irritate people. Please desist from doing so.
Ramana
Ping? I hope this patch can catch up with stage 1 of GCC-5.0. Thanks.
Hi Felix,
Sorry for missing the point. It seems to me that 't2' here will conflict with
condition of the pattern *movhi_insn_arch4:
TARGET_ARM
arm_arch4
(register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode))
#define TARGET_ARM (!
On 18/11/14 12:51, Yangfei (Felix) wrote:
On Tue, Nov 18, 2014 at 11:51 AM, Yangfei (Felix) felix.y...@huawei.com
wrote:
Ping again? Any comment please?
Pinging daily is only going to irritate people. Please desist from doing so.
Ramana
Oh, thanks for reminding me. And sorry if this
On Mon, Nov 17, 2014 at 5:13 PM, Marcus Shawcroft
marcus.shawcr...@gmail.com wrote:
On 14 November 2014 14:35, Wilco Dijkstra wdijk...@arm.com wrote:
2014-11-14 Wilco Dijkstra wdijk...@arm.com
* gcc/config/aarch64/aarch64.c (generic_regmove_cost):
Increase FP move cost.
On Tue, Nov 11, 2014 at 11:59 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch models the latency of moves between FP and GP registers on the
A15 and A57 a bit more accurately by splitting the reservations for FP-GP
and GP-FP moves and adding an appropriate bypass.
On Wed, Nov 12, 2014 at 9:51 AM, Terry Guo terry@arm.com wrote:
Hi there,
Attached patch intends to add pipeline description for ARM MCU Cortex-M7.
Is it ok to trunk?
This is OK. Can you please make sure there's an entry in changes for 5.0 ?
Ramana
BR,
Terry
2014-11-12 Terry Guo
On Mon, Nov 17, 2014 at 2:48 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
Some configurations of Cortex-A53 and Cortex-A57 don't ship with crypto,
so enabling it by default for -mcpu=cortex-a53 and cortex-a57 is
inappropriate.
Tested aarch64-none-elf. Reminder that at the moment
On Fri, Nov 14, 2014 at 11:11 AM, Marcus Shawcroft
marcus.shawcr...@gmail.com wrote:
On 14 November 2014 10:50, James Greenhalgh james.greenha...@arm.com wrote:
On Fri, Nov 14, 2014 at 10:42:27AM +, Andrew Pinski wrote:
On Fri, Nov 14, 2014 at 2:35 AM, James Greenhalgh
On 14/11/14 10:02, Terry Guo wrote:
Hi there,
Attached patch intends to fix a pattern that is found still non-UAL when do
gcc thumb-1 bootstrap. A test case is reduced and attached. Tested with gcc
regression test on pre-v6 thumb1 and v6 thumb1. No regression. Multilib can
be built for both
On 12/11/14 13:06, Christophe Lyon wrote:
On 12 November 2014 04:50, Yangfei (Felix) felix.y...@huawei.com wrote:
On Wed, Oct 22, 2014 at 10:49 PM, Michael Collison michael.colli...@linaro.org
wrote:
Patch that removes extraneous comment attached.
The CLZ_DEFINED_VALUE_AT_ZERO macro is
On 07/11/14 13:36, Richard Henderson wrote:
On 11/07/2014 01:02 PM, Ramana Radhakrishnan wrote:
+ *cost = COSTS_N_INSNS (aarch64_internal_mov_immediate
+(gen_rtx_REG (mode, 0), x, false));
}
Can't you pass NULL for the register when generate
and resubmit if folks think this is a good idea.
regards
Ramana
2014-11-12 Ramana Radhakrishnan ramana.radhakrish...@arm.com
* lib/wrapper.exp ${tool}_wrap_filename (): Define
* lib/g++.exp (g++_init): Use appropriate filename
for wrapper file.
* lib/gcc.exp (gcc_init
.
This is also in line with what we do in the AArch64 backend.
Will apply after a test run tonight on armhf.
regards
Ramana
* config/arm/sync.md (memory_barrier): Use dmb ish.
commit fca60730dee3281db4b688d9029ef08688507843
Author: Ramana Radhakrishnan ramana.radhakrish...@arm.com
Date: Fri Sep
the
recognizer kicks in.
Bootstrapped and regression tested on armhf.
Applied to trunk.
Ramana
2014-11-12 Ramana Radhakrishnan ramana.radhakrish...@arm.com
* config/arm/arm.md (arith_shift_insn): Fix typo in operand
number.
Index: gcc/config/arm/arm.h
On 11/11/14 08:40, Terry Guo wrote:
Hi there,
Attached patch intends to fix below trunk failure caused by recent thumb-1
UAL patch:
/tmp/cc9EfnXy.s: Assembler messages:
/tmp/cc9EfnXy.s:69: Error: MOV Rd, Rs with two low registers is not
permitted on this architecture -- `mov r6,r7'
Now for
34392753bd7f1481eff6ff86e055981618a3d06e
Author: Ramana Radhakrishnan ramana.radhakrish...@arm.com
Date: Thu Nov 6 16:08:27 2014 +
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 736ad90..20cbb2d 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
On 07/11/14 13:36, Richard Henderson wrote:
On 11/07/2014 01:02 PM, Ramana Radhakrishnan wrote:
+ *cost = COSTS_N_INSNS (aarch64_internal_mov_immediate
+(gen_rtx_REG (mode, 0), x, false));
}
Can't you pass NULL for the register when generate
On Tue, Oct 21, 2014 at 11:01 AM, Hale Wang hale.w...@arm.com wrote:
Hi,
Some configurations of the Cortex-M0 and Cortex-M1 come with a high latency
multiplier. This patch adds support for such configurations.
Small multiplier means using add/sub/shift instructions to replace the mul
On 05/11/14 07:09, Yangfei (Felix) wrote:
Hi,
This patch fixes PR63742 by improving arm *movhi_insn_arch4 pattern to
make it works under big-endian.
The idea is simple: Use movw for certain const source operand instead of
ldrh. And exclude the const values which cannot be handled
On Sun, Oct 26, 2014 at 4:50 PM, Christophe Lyon
christophe.l...@linaro.org wrote:
On 24 October 2014 10:07, Marcus Shawcroft marcus.shawcr...@gmail.com wrote:
On 21 October 2014 14:02, Christophe Lyon christophe.l...@linaro.org wrote:
This patch series is an updated version of the series I
On Tue, Oct 21, 2014 at 10:48 AM, Hale Wang hale.w...@arm.com wrote:
Hi,
This patch is used to tune the gcc for Cortex-M7.
The performance of Dhrystone can be improved by 1%.
The performance of Coremark can be improved by 2.3%.
Patch also attached for convenience.
Is it ok for trunk?
On Tue, Oct 21, 2014 at 10:18 AM, Terry Guo terry@arm.com wrote:
Hi There,
This is the first patch to enable GCC generate UAL assembly code for Thumb1
target. This new option enables user to specify which syntax is used in
their inline assembly code. If the inline assembly code uses UAL
On Tue, Oct 21, 2014 at 12:19 PM, Terry Guo terry@arm.com wrote:
Hi there,
Attached patch intends to enable GCC generate UAL format code for Thumb1
target. Tested with regression test and no regressions. Is it OK to trunk?
This is OK - Please don't commit it until we have sorted out
a obvious fix? Thank you so much!
applied this as obvious.
Ramana
2014-11-04 Ramana Radhakrishnan ramana.radhakrish...@arm.com
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Fix typo in definition
of __ARM_FEATURE_IDIV.
Kind regards,
Renlin
Index: gcc/config/arm/arm.h
On Fri, Oct 24, 2014 at 1:01 PM, Alan Lawrence alan.lawre...@arm.com wrote:
Similarly to last patch.
Tested, in combination with previous patch:
bootstrap on arm-none-linux-gnueabihf
cross-tested check-gcc on arm-none-eabi.
gcc/ChangeLog:
config/arm/neon.md (reduc_smin_mode *2):
On Fri, Oct 24, 2014 at 12:57 PM, Alan Lawrence alan.lawre...@arm.com wrote:
This migrates ARM from reduc_splus_optab and reduc_uplus optab to a single
reduc_plus_optab.
Tested, in combination with next patch:
bootstrap on arm-none-linux-gnueabihf
cross-tested check-gcc on arm-none-eabi.
On Wed, Oct 29, 2014 at 1:22 PM, Christophe Lyon
christophe.l...@linaro.org wrote:
Hi,
Following discussions after Thomas's patches improving bswap support
https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01279.html
I noticed that:
* the associated tests weren't executed on aarch64_be
* ARM
On Wed, Oct 22, 2014 at 10:49 PM, Michael Collison
michael.colli...@linaro.org wrote:
Patch that removes extraneous comment attached.
The CLZ_DEFINED_VALUE_AT_ZERO macro is hard coded to return 32. For the
vector intrinsic vclz this is incorrect and should return the value
vclz_{s,u}8 ...
On Wed, Oct 29, 2014 at 3:26 PM, Christophe Lyon
christophe.l...@linaro.org wrote:
Hi,
In PR61153, the vbic and vorn tests fail because when compiled at -O0
the expected Neon instructions are not generated, making
scan-assembler fail.
This patch:
- replaces -O0 by -O2
- moves the
On Wed, Oct 29, 2014 at 4:31 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This fixes an arm build failure due to removing the 'enum' keyword from
machine_mode.
Since libgcc2 is compiled with C rather than C++ we need it there for the
definition of CUMULATIVE_ARGS.
Another place
that reverting
Kyrill's patch breaks the build) . Will have to deal with AArch64 in
the morning unless someone beats me to it.
Ramana
2014-10-29 Ramana Radhakrishnan ramana.radhakrish...@arm.com
* config/arm/arm.h (MACHMODE): Treat machine_mode as a
scalar typedef
On Tue, Oct 28, 2014 at 11:46 AM, Matthew Fortune
matthew.fort...@imgtec.com wrote:
Do you have an objection to allowing an option to disable these
instructions (despite the reason for wanting to do so)?
Yes this seems like a bad workaround for broken code.
Well, we work around
On Fri, Oct 24, 2014 at 12:47 PM, Jiong Wang jiong.w...@arm.com wrote:
we should not add explicit declaration there.
arm_neon.h contains those prototype already. they will be available if the
compiler configuration is with related builtin predefine, for example
__ARM_FEATURE_CRYPTO.
so,
On Wed, Oct 22, 2014 at 11:02 AM, Jiong Wang jiong.w...@arm.com wrote:
On 21/10/14 15:30, Ramana Radhakrishnan wrote:
On Mon, Oct 13, 2014 at 3:15 PM, Renlin Li renlin...@arm.com wrote:
Hi all,
This is a simple patch to add missing __ARM_FEATURE_IDIV__ predefined
marco(ACLE 2.0
On 21/10/14 14:48, Jiong Wang wrote:
this patch update arm testcases for recently gnu11 change.
ok for trunk?
This is OK bar the minor nit in the ChangeLog below - as a follow up it
would be nice to see if we can use the ACLE feature macros instead of
hard-coding some of the functions
On Mon, Oct 13, 2014 at 3:15 PM, Renlin Li renlin...@arm.com wrote:
Hi all,
This is a simple patch to add missing __ARM_FEATURE_IDIV__ predefined
marco(ACLE 2.0) into TARGET_CPU_CPP_BUILTINS.
Is it Okay to commit?
gcc/ChangeLog:
2014-10-13 Renlin Li renlin...@arm.com
*
On Mon, Oct 20, 2014 at 10:17 PM, Richard Sandiford
rdsandif...@googlemail.com wrote:
Maxim Kuvyrkov maxim.kuvyr...@linaro.org writes:
[Adding ARM maintainers to CC]
On Oct 21, 2014, at 9:44 AM, Sebastian Pop seb...@gmail.com wrote:
Hi Maxim,
Maxim Kuvyrkov wrote:
Thanks, benchmarking
On 16/10/14 21:43, Andrew Pinski wrote:
On Thu, Oct 16, 2014 at 1:38 PM, Sebastian Pop seb...@gmail.com wrote:
Richard Biener wrote:
I have posted 5 patches as part of a larger series to merge
(parts) from the match-and-simplify branch. While I think
there was overall consensus that the
On Wed, Oct 15, 2014 at 5:29 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
On 15/10/14 14:00, Richard Biener wrote:
Any comments and reviews welcome (I don't think that
my maintainership covers enough to simply check this in
without approval).
Hi Richard,
The match-and-simplify
If the port has a splitter to rip apart a douple-word load into single-word
loads, then we'd obviously only want to do that in cases where the
double-word load actually generates 1 assembly instruction.
Or indeed if it is really a performance win. And I think that should
purely be a per
What do you prefer me to do for these tests? I can think of:
- do not include them at all until fp16 is fully supported on both
AArch32 and AArch64
- include only those with float16x4_t
- include both float16x4_t and float16x8_t tests, leaving float16x8_t commented
I would include them both
Hi Christian,
Thanks for looking at this. I will need to read the code in detail but
this is a first top level reivew.
On 09/29/14 12:03, Christian Bruel wrote:
Hi Ramana, Richard,
This patch implements the attribute target (and pragma) to allow
function based interworking.
as in the
arrives with the
different parts.
regards
Ramana
Best Regards
Christian
On 10/08/2014 03:05 PM, Ramana Radhakrishnan wrote:
Hi Christian,
Thanks for looking at this. I will need to read the code in detail but
this is a first top level reivew.
On 09/29/14 12:03, Christian Bruel
Hi,
I've been digging into why on AArch64 we generate pretty bad code
for the following testcase.
void g2(float, float, float, float, float, float, float, float);
void f2a(void)
{
float x0 = 1.0, x1 = 2.0, x2 = 3.0, x3 = 4.0, x4 = 5.0, x5 = 6.0, x6
= 7.0, x7 = 8.0;
float x8 = 0.5,
On Wed, Oct 1, 2014 at 10:03 AM, Christian Bruel christian.br...@st.com wrote:
Hi Ramana,
Your patch https://gcc.gnu.org/ml/gcc-patches/2012-02/msg01492.html
seems to have not been applied for 4.10. Are there any stoppers or is it
an omission ?
Short answer, no, not an omission. It could
On Wed, Sep 24, 2014 at 6:17 AM, Terry Guo terry@arm.com wrote:
Hi there,
The attached patch intends to provide option support to newly announced core
Cortex-M7 and related FPU:
http://www.arm.com/about/newsroom/arm-supercharges-mcu-market-with-high-perf
ormance-cortex-m7-processor.php
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