subject:"add taishanv110 pipeline scheduling"

Re: add taishanv110 pipeline scheduling

2018-12-14 Thread Ramana Radhakrishnan

Hi Wuyuan,

On 06/12/2018 01:31, wuyuan (E) wrote:
> Hi ARM maintainers:
>  The taishanv110 core uses generic pipeline scheduling, which 
> restricted the performance of taishanv110 core. By adding the pipeline 
> scheduling of taishanv110 core in GCC,The performance of taishanv110 has been 
> improved.
>  The patch  as follows, please join.

Who is looking to fix the architectural version of the tsv110 like the 
LLVM description here https://reviews.llvm.org/D53908 ?

The GCC implementation considers this to be an armv8.4-A part while it 
really appears to be an armv8.2-A part with some optional extensions 
based on the link above ?

We are in the run up to the GCC 9 release so it would be good to get 
this fixed up before that.

regards
Ramana

> 
> 
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> old mode 100644
> new mode 100755
> index c4ec556..d6cf1d3
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,9 @@
> +2018-12-05  wuyuan  
> +
> +   * config/aarch64/aarch64-cores.def: New CPU.
> +   * config/aarch64/aarch64.md : Add "tsv110.md"
> +   * gcc/config/aarch64/tsv110.md : pipeline description
> +
> 2018-11-26  David Malcolm  
> 
>* dump-context.h (dump_context::dump_loc): Convert 1st param from
> diff --git a/gcc/config/aarch64/aarch64-cores.def 
> b/gcc/config/aarch64/aarch64-cores.def
> index 74be5db..8e84844 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -99,7 +99,7 @@ AARCH64_CORE("ares",  ares, cortexa57, 8_2A,  
> AARCH64_FL_FOR_ARCH8_2 | AARCH64_F
> /* ARMv8.4-A Architecture Processors.  */
> 
> /* HiSilicon ('H') cores. */
> -AARCH64_CORE("tsv110", tsv110,cortexa57,8_4A, 
> AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES 
> | AARCH64_FL_SHA2, tsv110,   0x48, 0xd01, -1)
> +AARCH64_CORE("tsv110", tsv110,tsv110,8_4A, 
> AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES 
> | AARCH64_FL_SHA2, tsv110,   0x48, 0xd01, -1)
> 
> /* Qualcomm ('Q') cores. */
> AARCH64_CORE("saphira", saphira,saphira,8_4A,  
> AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira,   
> 0x51, 0xC01, -1)
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 82af4d4..5278d6b 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -348,7 +348,7 @@
> (include "thunderx.md")
> (include "../arm/xgene1.md")
> (include "thunderx2t99.md")
> -
> +(include "tsv110.md")
> ;; ---
> ;; Jumps and other miscellaneous insns
> ;; ---
> diff --git a/gcc/config/aarch64/tsv110.md b/gcc/config/aarch64/tsv110.md
> new file mode 100644
> index 000..e912447
> --- /dev/null
> +++ b/gcc/config/aarch64/tsv110.md
> @@ -0,0 +1,708 @@
> +;; tsv110 pipeline description
> +;; Copyright (C) 2014-2016 Free Software Foundation, Inc.
> +;;
> +;; This file is part of GCC.
> +;;
> +;; GCC is free software; you can redistribute it and/or modify it
> +;; under the terms of the GNU General Public License as published by
> +;; the Free Software Foundation; either version 3, or (at your option)
> +;; any later version.
> +;;
> +;; GCC is distributed in the hope that it will be useful, but
> +;; WITHOUT ANY WARRANTY; without even the implied warranty of
> +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> +;; General Public License for more details.
> +;;
> +;; You should have received a copy of the GNU General Public License
> +;; along with GCC; see the file COPYING3.  If not see
> +;; .
> +
> +(define_automaton "tsv110")
> +
> +(define_attr "tsv110_neon_type"
> +  "neon_arith_acc, neon_arith_acc_q,
> +   neon_arith_basic, neon_arith_complex,
> +   neon_reduc_add_acc, neon_multiply, neon_multiply_q,
> +   neon_multiply_long, neon_mla, neon_mla_q, neon_mla_long,
> +   neon_sat_mla_long, neon_shift_acc, neon_shift_imm_basic,
> +   neon_shift_imm_complex,
> +   neon_shift_reg_basic, neon_shift_reg_basic_q, neon_shift_reg_complex,
> +   neon_shift_reg_complex_q, neon_fp_negabs, neon_fp_arith,
> +   neon_fp_arith_q, neon_fp_reductions_q, neon_fp_cvt_int,
> +   neon_fp_cvt_int_q, neon_fp_cvt16, neon_fp_minmax, neon_fp_mul,
> +   neon_fp_mul_q, neon_fp_mla, neon_fp_mla_q, neon_fp_recpe_rsqrte,
> +   neon_fp_recpe_rsqrte_q, neon_fp_recps_rsqrts, neon_fp_recps_rsqrts_q,
> +   neon_bitops, neon_bitops_q, neon_from_gp,
> +   neon_from_gp_q, neon_move, neon_tbl3_tbl4, neon_zip_q, neon_to_gp,
> +   neon_load_a, neon_load_b, neon_load_c, neon_load_d, neon_load_e,
> +   neon_load_f, neon_store_a, neon_store_b, neon_store_complex,
> +   unknown"
> +  (cond [
> + (eq_attr "type" "neon_arith_acc, neon_reduc_add_acc,\
> +  neon_reduc_add_acc_q")
> +   (const_string "neon_arith_acc")
> +

答复: add taishanv110 pipeline scheduling

2018-12-11 Thread wuyuan (E)

HI Terry,Kyrill
I'm sorry to reply to your email after a week, it's a busy week.
Glad to receive your advice, Follow kyrill's advice ,adjust the reservation 
to 12 cycles, the result shows that it will not affect the scheduling 
performance.
I have modified the patch according to the suggestion(See modification  in 
the attachment),Please review. Anyway If you have more suggestions, I will 
continue to modify.



Thinks   

-邮件原件-
发件人: Kyrill Tkachov [mailto:kyrylo.tkac...@foss.arm.com] 
发送时间: 2018年12月6日 20:37
收件人: wuyuan (E) ; gcc-patches@gcc.gnu.org
抄送: Zhanghaijian (A) ; Zhangyichao (AB) 
; Yangfei (Felix) ; James 
Greenhalgh ; Richard Earnshaw 
; Ramana Radhakrishnan 
; Marcus Shawcroft 
主题: Re: add taishanv110 pipeline scheduling

Hi Wu,

I notice you CC'ed the arm maintainers. This is an aarch64 patch as the arm 
(aarch32) and aarch64 ports are separate in GCC.
I've added the aarch64 maintainers on CC for you.

On 06/12/18 01:31, wuyuan (E) wrote:
>
> Hi ARM maintainers:
>
> The taishanv110 core uses generic pipeline scheduling, which 
> restricted the performance of taishanv110 core. By adding the pipeline 
> scheduling of taishanv110 core in GCC,The performance of taishanv110 has been 
> improved.
>
> The patch  as follows, please join.
>
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
>
> old mode 100644
>
> new mode 100755
>
> index c4ec556..d6cf1d3
>
> --- a/gcc/ChangeLog
>
> +++ b/gcc/ChangeLog
>
> @@ -1,3 +1,9 @@
>
> +2018-12-05  wuyuan 
>
> +
>
> +   * config/aarch64/aarch64-cores.def: New CPU.
>
> +   * config/aarch64/aarch64.md : Add "tsv110.md"
>
> +   * gcc/config/aarch64/tsv110.md : pipeline description
>
> +
>

No "gcc/" in the path. Also, I'd use "New file."

> 2018-11-26  David Malcolm 
>
>   * dump-context.h (dump_context::dump_loc): Convert 1st param 
> from
>
> diff --git a/gcc/config/aarch64/aarch64-cores.def 
> b/gcc/config/aarch64/aarch64-cores.def
>
> index 74be5db..8e84844 100644
>
> --- a/gcc/config/aarch64/aarch64-cores.def
>
> +++ b/gcc/config/aarch64/aarch64-cores.def
>
> @@ -99,7 +99,7 @@ AARCH64_CORE("ares", ares, cortexa57, 8_2A,  
> AARCH64_FL_FOR_ARCH8_2 | AARCH64_F
>
> /* ARMv8.4-A Architecture Processors.  */
>
> /* HiSilicon ('H') cores. */
>
> -AARCH64_CORE("tsv110", tsv110, cortexa57,8_4A, 
> AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES 
> | AARCH64_FL_SHA2, tsv110,   0x48, 0xd01, -1)
>
> +AARCH64_CORE("tsv110", tsv110, tsv110,8_4A, AARCH64_FL_FOR_ARCH8_4 | 
> AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, 
> tsv110,   0x48, 0xd01, -1)
>
> /* Qualcomm ('Q') cores. */
>
> AARCH64_CORE("saphira", saphira, saphira,8_4A,  
> AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira,   
> 0x51, 0xC01, -1)
>
> diff --git a/gcc/config/aarch64/aarch64.md 
> b/gcc/config/aarch64/aarch64.md
>
> index 82af4d4..5278d6b 100644
>
> --- a/gcc/config/aarch64/aarch64.md
>
> +++ b/gcc/config/aarch64/aarch64.md
>
> @@ -348,7 +348,7 @@
>
> (include "thunderx.md")
>
> (include "../arm/xgene1.md")
>
> (include "thunderx2t99.md")
>
> -
>
> +(include "tsv110.md")
>
> ;; ---
>
> ;; Jumps and other miscellaneous insns
>
> ;; ---
>
> diff --git a/gcc/config/aarch64/tsv110.md 
> b/gcc/config/aarch64/tsv110.md
>
> new file mode 100644
>
> index 000..e912447
>
> --- /dev/null
>
> +++ b/gcc/config/aarch64/tsv110.md
>
> @@ -0,0 +1,708 @@
>
> +;; tsv110 pipeline description
>
> +;; Copyright (C) 2014-2016 Free Software Foundation, Inc.
>
> +;;
>
> +;; This file is part of GCC.
>
> +;;
>
> +;; GCC is free software; you can redistribute it and/or modify it
>
> +;; under the terms of the GNU General Public License as published by
>
> +;; the Free Software Foundation; either version 3, or (at your 
> +option)
>
> +;; any later version.
>
> +;;
>
> +;; GCC is distributed in the hope that it will be useful, but
>
> +;; WITHOUT ANY WARRANTY; without even the implied warranty of
>
> +;; MERCHANTABILITY or FITNESS FOR

Re: add taishanv110 pipeline scheduling

2018-12-06 Thread Kyrill Tkachov


Hi Wu,

I notice you CC'ed the arm maintainers. This is an aarch64 patch as the arm 
(aarch32) and aarch64 ports are separate in GCC.
I've added the aarch64 maintainers on CC for you.

On 06/12/18 01:31, wuyuan (E) wrote:


Hi ARM maintainers:

The taishanv110 core uses generic pipeline scheduling, which restricted 
the performance of taishanv110 core. By adding the pipeline scheduling of 
taishanv110 core in GCC,The performance of taishanv110 has been improved.

The patch  as follows, please join.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog

old mode 100644

new mode 100755

index c4ec556..d6cf1d3

--- a/gcc/ChangeLog

+++ b/gcc/ChangeLog

@@ -1,3 +1,9 @@

+2018-12-05  wuyuan 

+

+   * config/aarch64/aarch64-cores.def: New CPU.

+   * config/aarch64/aarch64.md : Add "tsv110.md"

+   * gcc/config/aarch64/tsv110.md : pipeline description

+



No "gcc/" in the path. Also, I'd use "New file."


2018-11-26  David Malcolm 

  * dump-context.h (dump_context::dump_loc): Convert 1st param from

diff --git a/gcc/config/aarch64/aarch64-cores.def 
b/gcc/config/aarch64/aarch64-cores.def

index 74be5db..8e84844 100644

--- a/gcc/config/aarch64/aarch64-cores.def

+++ b/gcc/config/aarch64/aarch64-cores.def

@@ -99,7 +99,7 @@ AARCH64_CORE("ares", ares, cortexa57, 8_2A,  
AARCH64_FL_FOR_ARCH8_2 | AARCH64_F

/* ARMv8.4-A Architecture Processors.  */

/* HiSilicon ('H') cores. */

-AARCH64_CORE("tsv110", tsv110, cortexa57,8_4A, AARCH64_FL_FOR_ARCH8_4 
| AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110,   0x48, 
0xd01, -1)

+AARCH64_CORE("tsv110", tsv110, tsv110,8_4A, AARCH64_FL_FOR_ARCH8_4 | 
AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110,   0x48, 
0xd01, -1)

/* Qualcomm ('Q') cores. */

AARCH64_CORE("saphira", saphira, saphira,8_4A,  AARCH64_FL_FOR_ARCH8_4 
| AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira,   0x51, 0xC01, -1)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md

index 82af4d4..5278d6b 100644

--- a/gcc/config/aarch64/aarch64.md

+++ b/gcc/config/aarch64/aarch64.md

@@ -348,7 +348,7 @@

(include "thunderx.md")

(include "../arm/xgene1.md")

(include "thunderx2t99.md")

-

+(include "tsv110.md")

;; ---

;; Jumps and other miscellaneous insns

;; ---

diff --git a/gcc/config/aarch64/tsv110.md b/gcc/config/aarch64/tsv110.md

new file mode 100644

index 000..e912447

--- /dev/null

+++ b/gcc/config/aarch64/tsv110.md

@@ -0,0 +1,708 @@

+;; tsv110 pipeline description

+;; Copyright (C) 2014-2016 Free Software Foundation, Inc.

+;;

+;; This file is part of GCC.

+;;

+;; GCC is free software; you can redistribute it and/or modify it

+;; under the terms of the GNU General Public License as published by

+;; the Free Software Foundation; either version 3, or (at your option)

+;; any later version.

+;;

+;; GCC is distributed in the hope that it will be useful, but

+;; WITHOUT ANY WARRANTY; without even the implied warranty of

+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

+;; General Public License for more details.

+;;

+;; You should have received a copy of the GNU General Public License

+;; along with GCC; see the file COPYING3.  If not see

+;; .

+

+(define_automaton "tsv110")

+

+(define_attr "tsv110_neon_type"

+  "neon_arith_acc, neon_arith_acc_q,

+   neon_arith_basic, neon_arith_complex,

+   neon_reduc_add_acc, neon_multiply, neon_multiply_q,

+   neon_multiply_long, neon_mla, neon_mla_q, neon_mla_long,

+   neon_sat_mla_long, neon_shift_acc, neon_shift_imm_basic,

+   neon_shift_imm_complex,

+   neon_shift_reg_basic, neon_shift_reg_basic_q, neon_shift_reg_complex,

+   neon_shift_reg_complex_q, neon_fp_negabs, neon_fp_arith,

+   neon_fp_arith_q, neon_fp_reductions_q, neon_fp_cvt_int,

+   neon_fp_cvt_int_q, neon_fp_cvt16, neon_fp_minmax, neon_fp_mul,

+   neon_fp_mul_q, neon_fp_mla, neon_fp_mla_q, neon_fp_recpe_rsqrte,

+   neon_fp_recpe_rsqrte_q, neon_fp_recps_rsqrts, neon_fp_recps_rsqrts_q,

+   neon_bitops, neon_bitops_q, neon_from_gp,

+   neon_from_gp_q, neon_move, neon_tbl3_tbl4, neon_zip_q, neon_to_gp,

+   neon_load_a, neon_load_b, neon_load_c, neon_load_d, neon_load_e,

+   neon_load_f, neon_store_a, neon_store_b, neon_store_complex,

+   unknown"

+  (cond [

+ (eq_attr "type" "neon_arith_acc, neon_reduc_add_acc,\

+ neon_reduc_add_acc_q")

+   (const_string "neon_arith_acc")

+ (eq_attr "type" "neon_arith_acc_q")

+   (const_string "neon_arith_acc_q")

+ (eq_attr "type" "neon_abs,neon_abs_q,neon_add, neon_add_q, 
neon_add_long,\

+ neon_add_widen, neon_neg, neon_neg_q,\

+ neon_reduc_add, neon_reduc_add_q,\

+ neon_reduc_add_long, neon_sub, neon_sub_q,\

+ neon_sub_long, neon_sub_widen, neon_logic,\

+

Re: add taishanv110 pipeline scheduling

2018-12-05 Thread Terry Guo

On Thu, Dec 6, 2018 at 9:31 AM wuyuan (E)  wrote:
>
> Hi ARM maintainers:
> The taishanv110 core uses generic pipeline scheduling, which 
> restricted the performance of taishanv110 core. By adding the pipeline 
> scheduling of taishanv110 core in GCC,The performance of taishanv110 has been 
> improved.
> The patch  as follows, please join.
>
>
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> old mode 100644
> new mode 100755
> index c4ec556..d6cf1d3
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,9 @@
> +2018-12-05  wuyuan  
> +

Better be "Wu Yuan"

> +   * config/aarch64/aarch64-cores.def: New CPU.
> +   * config/aarch64/aarch64.md : Add "tsv110.md"
> +   * gcc/config/aarch64/tsv110.md : pipeline description
> +
Can remove the "gcc/" part.

> 2018-11-26  David Malcolm  
>
>   * dump-context.h (dump_context::dump_loc): Convert 1st param from
> diff --git a/gcc/config/aarch64/aarch64-cores.def 
> b/gcc/config/aarch64/aarch64-cores.def
> index 74be5db..8e84844 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -99,7 +99,7 @@ AARCH64_CORE("ares",  ares, cortexa57, 8_2A,  
> AARCH64_FL_FOR_ARCH8_2 | AARCH64_F
> /* ARMv8.4-A Architecture Processors.  */
>
> /* HiSilicon ('H') cores. */
> -AARCH64_CORE("tsv110", tsv110,cortexa57,8_4A, 
> AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES 
> | AARCH64_FL_SHA2, tsv110,   0x48, 0xd01, -1)
> +AARCH64_CORE("tsv110", tsv110,tsv110,8_4A, 
> AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES 
> | AARCH64_FL_SHA2, tsv110,   0x48, 0xd01, -1)
>
> /* Qualcomm ('Q') cores. */
> AARCH64_CORE("saphira", saphira,saphira,8_4A,  
> AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira,   
> 0x51, 0xC01, -1)
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 82af4d4..5278d6b 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -348,7 +348,7 @@
> (include "thunderx.md")
> (include "../arm/xgene1.md")
> (include "thunderx2t99.md")
> -
> +(include "tsv110.md")
> ;; ---
> ;; Jumps and other miscellaneous insns
> ;; ---
> diff --git a/gcc/config/aarch64/tsv110.md b/gcc/config/aarch64/tsv110.md
> new file mode 100644
> index 000..e912447
> --- /dev/null
> +++ b/gcc/config/aarch64/tsv110.md
> @@ -0,0 +1,708 @@
> +;; tsv110 pipeline description
> +;; Copyright (C) 2014-2016 Free Software Foundation, Inc.
> +;;

Given this is a new file, I think the copyright year should be updated.

BR,
Terry

> +;; This file is part of GCC.
> +;;
> +;; GCC is free software; you can redistribute it and/or modify it
> +;; under the terms of the GNU General Public License as published by
> +;; the Free Software Foundation; either version 3, or (at your option)
> +;; any later version.
> +;;
> +;; GCC is distributed in the hope that it will be useful, but
> +;; WITHOUT ANY WARRANTY; without even the implied warranty of
> +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> +;; General Public License for more details.
> +;;
> +;; You should have received a copy of the GNU General Public License
> +;; along with GCC; see the file COPYING3.  If not see
> +;; .
> +
> +(define_automaton "tsv110")
> +
> +(define_attr "tsv110_neon_type"
> +  "neon_arith_acc, neon_arith_acc_q,
> +   neon_arith_basic, neon_arith_complex,
> +   neon_reduc_add_acc, neon_multiply, neon_multiply_q,
> +   neon_multiply_long, neon_mla, neon_mla_q, neon_mla_long,
> +   neon_sat_mla_long, neon_shift_acc, neon_shift_imm_basic,
> +   neon_shift_imm_complex,
> +   neon_shift_reg_basic, neon_shift_reg_basic_q, neon_shift_reg_complex,
> +   neon_shift_reg_complex_q, neon_fp_negabs, neon_fp_arith,
> +   neon_fp_arith_q, neon_fp_reductions_q, neon_fp_cvt_int,
> +   neon_fp_cvt_int_q, neon_fp_cvt16, neon_fp_minmax, neon_fp_mul,
> +   neon_fp_mul_q, neon_fp_mla, neon_fp_mla_q, neon_fp_recpe_rsqrte,
> +   neon_fp_recpe_rsqrte_q, neon_fp_recps_rsqrts, neon_fp_recps_rsqrts_q,
> +   neon_bitops, neon_bitops_q, neon_from_gp,
> +   neon_from_gp_q, neon_move, neon_tbl3_tbl4, neon_zip_q, neon_to_gp,
> +   neon_load_a, neon_load_b, neon_load_c, neon_load_d, neon_load_e,
> +   neon_load_f, neon_store_a, neon_store_b, neon_store_complex,
> +   unknown"
> +  (cond [
> + (eq_attr "type" "neon_arith_acc, neon_reduc_add_acc,\
> +  neon_reduc_add_acc_q")
> +   (const_string "neon_arith_acc")
> + (eq_attr "type" "neon_arith_acc_q")
> +   (const_string "neon_arith_acc_q")
> + (eq_attr "type" "neon_abs,neon_abs_q,neon_add, neon_add_q, 
> neon_add_long,\
> +  neon_add_widen, neon_neg, neon_neg_q,\
> +

add taishanv110 pipeline scheduling

2018-12-05 Thread wuyuan (E)

Hi ARM maintainers:
The taishanv110 core uses generic pipeline scheduling, which restricted 
the performance of taishanv110 core. By adding the pipeline scheduling of 
taishanv110 core in GCC,The performance of taishanv110 has been improved.
The patch  as follows, please join.


diff --git a/gcc/ChangeLog b/gcc/ChangeLog
old mode 100644
new mode 100755
index c4ec556..d6cf1d3
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-12-05  wuyuan  
+
+   * config/aarch64/aarch64-cores.def: New CPU.
+   * config/aarch64/aarch64.md : Add "tsv110.md"
+   * gcc/config/aarch64/tsv110.md : pipeline description
+
2018-11-26  David Malcolm  

  * dump-context.h (dump_context::dump_loc): Convert 1st param from
diff --git a/gcc/config/aarch64/aarch64-cores.def 
b/gcc/config/aarch64/aarch64-cores.def
index 74be5db..8e84844 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -99,7 +99,7 @@ AARCH64_CORE("ares",  ares, cortexa57, 8_2A,  
AARCH64_FL_FOR_ARCH8_2 | AARCH64_F
/* ARMv8.4-A Architecture Processors.  */

/* HiSilicon ('H') cores. */
-AARCH64_CORE("tsv110", tsv110,cortexa57,8_4A, 
AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | 
AARCH64_FL_SHA2, tsv110,   0x48, 0xd01, -1)
+AARCH64_CORE("tsv110", tsv110,tsv110,8_4A, AARCH64_FL_FOR_ARCH8_4 
| AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, 
tsv110,   0x48, 0xd01, -1)

/* Qualcomm ('Q') cores. */
AARCH64_CORE("saphira", saphira,saphira,8_4A,  
AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira,   0x51, 
0xC01, -1)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 82af4d4..5278d6b 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -348,7 +348,7 @@
(include "thunderx.md")
(include "../arm/xgene1.md")
(include "thunderx2t99.md")
-
+(include "tsv110.md")
;; ---
;; Jumps and other miscellaneous insns
;; ---
diff --git a/gcc/config/aarch64/tsv110.md b/gcc/config/aarch64/tsv110.md
new file mode 100644
index 000..e912447
--- /dev/null
+++ b/gcc/config/aarch64/tsv110.md
@@ -0,0 +1,708 @@
+;; tsv110 pipeline description
+;; Copyright (C) 2014-2016 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but
+;; WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+;; General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+(define_automaton "tsv110")
+
+(define_attr "tsv110_neon_type"
+  "neon_arith_acc, neon_arith_acc_q,
+   neon_arith_basic, neon_arith_complex,
+   neon_reduc_add_acc, neon_multiply, neon_multiply_q,
+   neon_multiply_long, neon_mla, neon_mla_q, neon_mla_long,
+   neon_sat_mla_long, neon_shift_acc, neon_shift_imm_basic,
+   neon_shift_imm_complex,
+   neon_shift_reg_basic, neon_shift_reg_basic_q, neon_shift_reg_complex,
+   neon_shift_reg_complex_q, neon_fp_negabs, neon_fp_arith,
+   neon_fp_arith_q, neon_fp_reductions_q, neon_fp_cvt_int,
+   neon_fp_cvt_int_q, neon_fp_cvt16, neon_fp_minmax, neon_fp_mul,
+   neon_fp_mul_q, neon_fp_mla, neon_fp_mla_q, neon_fp_recpe_rsqrte,
+   neon_fp_recpe_rsqrte_q, neon_fp_recps_rsqrts, neon_fp_recps_rsqrts_q,
+   neon_bitops, neon_bitops_q, neon_from_gp,
+   neon_from_gp_q, neon_move, neon_tbl3_tbl4, neon_zip_q, neon_to_gp,
+   neon_load_a, neon_load_b, neon_load_c, neon_load_d, neon_load_e,
+   neon_load_f, neon_store_a, neon_store_b, neon_store_complex,
+   unknown"
+  (cond [
+ (eq_attr "type" "neon_arith_acc, neon_reduc_add_acc,\
+  neon_reduc_add_acc_q")
+   (const_string "neon_arith_acc")
+ (eq_attr "type" "neon_arith_acc_q")
+   (const_string "neon_arith_acc_q")
+ (eq_attr "type" "neon_abs,neon_abs_q,neon_add, neon_add_q, 
neon_add_long,\
+  neon_add_widen, neon_neg, neon_neg_q,\
+  neon_reduc_add, neon_reduc_add_q,\
+  neon_reduc_add_long, neon_sub, neon_sub_q,\
+  neon_sub_long, neon_sub_widen, neon_logic,\
+  neon_logic_q, neon_tst, neon_tst_q,\
+  neon_compare, neon_compare_q,\
+  neon_compare_zero, neon_compare_zero_q,\
+

Re: add taishanv110 pipeline scheduling

答复: add taishanv110 pipeline scheduling

Re: add taishanv110 pipeline scheduling

Re: add taishanv110 pipeline scheduling

add taishanv110 pipeline scheduling

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