Could you make the patch relative to what I just checked in?
OK, try this one.
Nothing attached.
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Ok, that one's committed too. Thanks!
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http://archives.seul.org/geda/user/Jan-2009/msg00056.html
May be some pages in that example have similarity to
your screen shot example?
Yes, very similar.
its not difficult to have the gnet-xxx.scm to flatten
it for flat-netlist.
IMHO the ability to expand those lists into individual
For PCB, I think we need additional attributes (if footprint symbols
were to support bus pins), since we need a mapping onto pin-number for
each element in the bus). This would be similar to the net=foo:1, but
with the foo scoped to search for named signals inside the symbol's
pins, rather
Why not just use gdImageFill() ?
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Me likey. However, with alpha checked, pads come out green instead of
grey... http://www.delorie.com/pcb/green-pads.png
Also, future addition - scan for the edges of the transparency, and do
the top/bottom shadow thing on them so the board edges look 3-D.
Hmmm... we could try taking out the patterning we do for the pads to
see, that's the only thing I know of that may use lots of palette
entries.
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Anybody else!?!?
I'm willing, but I've already got the LF work to do. My pet projects
for GSoC'09:
* bus nets in gaf - the ability to use pin numbers like
[1-4,6,8,10-15] and net names like D[0-15] and have them
demultiplex into individual signals when you run the netlister.
* The
I know you are very busy and its very difficult to discuss all the
details. Do you think an example, or a screen shot may help?
In my case, what I want is pretty simple to show. I want these to be
equivalent: http://www.delorie.com/pcb/djbus.png
The netlister backends should always see the
484 frames in 6.5 seconds = 74.291 FPS
339 frames in 5.3 seconds = 63.483 FPS
452 frames in 6.2 seconds = 73.287 FPS
Just for comparison, Bert, my reasonable but not super-fast notebook
gives answers more like:
2918 frames in 5.0 seconds = 582.974 FPS
3911 frames in 5.0 seconds =
Damn me. I knew this thread would degrade into my glxgears
FPS is bigger than yours. :)
Actually, my son's glxgears are even bigger, but his card is only a
few months old.
Long story short, if you want good OpenGL performance you need
accelerated GL drivers and DRI enabled.
I
One interesting experiment I did was to pull out _all_ the drawing
code, and measure PCB's frame rate.
Can the batch HID do this for us? Or did you short-circuit the
gtk/lesstif hid?
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Can I put a copy of this in the sources?
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Ok, I've got this so far then. Still have to bloat the pads to force
them to overlap, else pads intersecting the edges of polygons don't
get picked. We *still* miss pads that are within minspace of the edge
of a polygon but neither intersect nor plow into the polygon.
Index: find.c
What DRC usually does is bloat the copper by pcb-bloat and
intersect those. If they touch, they're too close. It doesn't
actually calculate distance anywhere. However, the polygon.c routines
do *not* bloat, which is causing the problems. We need to know if
lines/pads/etc are *near* the
Re: sourceforge bug # 1890743
The underlying code checks the polygon clearance of each pad that's in
a polygon. If it's too little, it complains.
However, it's using code that sees if the pad is inside the *clipped*
polygon. Since pads clear polygons, this is never the case, and we
never end
Some experimentation has led me to this patch, does it make sense?
It's a little agressive (4* instead of 2*) but 2* didn't seem to work,
I don't know if the global Bloat was overriding it.
Index: find.c
===
RCS file:
First, please don't say dicer when you don't mean dicer. The
polygon dicer is the code that cuts a polygon with holes (such as
any typical plane) up into sub-parts which have no holes. These are
used to render to certain devices.
The dicer turns a polygon-with-holes into N
Please keep in mind, that schematic editing, and PCB designing could
be far away from each other. I mean... someone designes a schematic,
sends a forward anno file, then you with your computer should be
able to interpret that file.
Right, but that's not the 90% use case. That's in the 10%,
Would it be sensible to abstract the execution of an update command to
generate new action scripts / netlist etc..?
No matter where you put the command, something needs to be associated
with the board/project, and it needs to be vetted before use. So I
don't think such an abstraction would be
I'm thinking that relative at least needs to be supported so you can
move a project directory around.
Right, the idea is that each schematic name is a filename, either
absolute or relative to the board, rather than storing the schematic's
base name in one list and a set of search paths in a
What I find myself doing is growing the board area enough to have some
free space, sprinkling the new parts out in this area, and then
manually moving them onto the board.
I do this too. One of the options we talked about is to have a
separate space for non-placed parts, either a list or a
In my view, just as gEDA/gaf can netlist to any backend,
so should PCB read an arbitrary action list generated from any tool.
It *can*, which is why the bulk of the information comes across as an
action script. However, I'm also trying to optimize the *common*
case, which is, pcb used with
But how does PCB know which gnetlist to run? Just the first
one on the $PATH?
Yes. That's the right one for the 90% case.
But there must also be a menu option file - read forward
annotation file which just reads the raw forward anno file.
:ExecuteFile(anno.sc) ;-)
In the best case, a
Just to clarify, my vision is that the old gsch2pcb program (and its
friends) will be modified to emit an action script instead of a
.pcb.new file.
Sure.
Updating gsch2pcb is intended to be outside the SOW.
I'd need to write the netlister anyway, for testing.
On the subject of the action
Sounds like you've just invented a very awkward netlist and parts-list
format, with each line having an explicit verb ;)
Yup. That's what an action script is.
We already have an action to load a netlist file, but that means we
need not one but two files being spit out by gnetlist. Three if
That is, the fwd anno file would represent a delta between the
existing .pcb file and what's changed in the .sch files.
I'm looking at it a step further away - the fwd anno file includes all
the info about the pcb *that comes from the schematic*. PCB will
integrate this desired list with the
[subject changed from Re: gEDA-dev: [LF] forward annotation ideas]
Just to follow up on my last comment, I wonder if there is anything to
be gained by adding a full interpreter?
The action syntax suggests that adding a TCL or scheme interpreter
would be fairly trivial - except that actions
AddElement(X, Y, rotatation, refdes, footprint, etc. etc. etc)
then PCB would look to see if a component existed at (X, Y) with the
same rotation, refdes, footprint, etc. and if it did, then PCB would
just leave it alone. Otherwise, it would update the parameters which
are different.
In
Although Scheme has generated some complaints from heavy-duty
EDA guys (who prefer TCL), I think if we can get away from guile and
it's problems, then the objection to Scheme is greatly reduced.
I suspect the interpreter would just be a hid or plugin anyway.
The tricky part is setting up the
propagate them through the PCB design. Is this something for which
there's a well-defined workflow that I just haven't stumbled over
yet, or is this an area of weakness?
This is an area of weakness.
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How is it that the scope of the Linux Fund grant was as narrow as
define syntax to forward annotate PCB, but not code anything that
creates a forward annotation action list?
IMHO, the LF scope is streamline schematic-pcb updates
For the 10% power users there will be other options. LF only
This sounds like the .pcb file is going to hold lots of project
definition data either temporarily, or as a central repository. I
suppose that's fine for getting going, but it would be truly fine if
the API for dealing with the project work flow allows future project
managers to be
Stuart Brorson s...@cloud9.net writes:
Dec 28th
I now have plans for the 28th.
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Question: in cvs, should the vfs files subdirectory be a subdir of
the src/ directory, or be a peer to it?
H, why is the src/ directory in there at all?
in cvs
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Do I win a prize for my answer? :-)
The prize is, I keep typing ;-)
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I checked in the PCB Getting Started Guide. I can only assume there
will be tweaks to make it work without pre-installed tools, or in a
cross environment, over time... but it's in. Edit away :-)
You'll need to use -d to pick up the new directory, the first time.
This is what I'm thinking for the forward annotation (gsch2pcb) design:
The PCB has a list of schematics that it gets info from. Do we need
path support, or is full-paths (or relative to the pcb) ok?
Wildcards? Anyway, the list of schematics is stored in the .pcb file
somehow. The GUI needs a
Dec 27th
Dec 28th
Jan 3rd
Jan 4th
I'm open those days.
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It should be trivial enough to just rsync my area to some other
x86-based apache server elsewhere, regularly. No need to make drastic
changes. Then I'd set the IP for gedasymbols.org to be both machines
and it wouldn't matter which one you got.
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Does it draw behind, or in front of, the schematic?
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The GEDADATA setting in Cygwin is the same as the Windows GEDADATA
setting. If I set that back to the correct Cygwin path then it is all
fine. There might be a way to stop Cygwin from doing this, but it
appears to import the Windows system variables (probably when it is
launched).
Cygwin,
Also... not sure how useful they'd be, but you can use pictures from
the Getting Started guide too.
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Personally. I'd be hesitant to see my email address in a public
screen-shot, but its not bot-readable, and is defunct as far as I
could tell when I tried to contact him.
I'd at least paint out the domain part.
Fine. Or public domain, I'm not fussed.
Don't put anything in the public domain
I've got a board where adding teardrops causes a polygon clipping
error, and a big chunk of my ground plane goes away.
Board: http://www.delorie.com/electronics/powermeter/powermeter.pcb
Just run :Teardrops() on it, and the left ground plane vanishes.
Debian stable.
What hardware? ia32? x86-64? ARM?
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I wonder if the polygon clipper is being ignorant of arcs that aren't
multiples of 90 degrees?
Of course, teardrops look just fine when it *does* work, angles or
otherwise, so it's not *that* ignorant.
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Ick.
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I also ran into this today, bom'ing the powermeter board:
http://archives.seul.org/geda/user/Feb-2008/msg00277.html
Should we make that workaround permanent?
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What OS is that? I tried TAB on my pcb and it worked fine.
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PCB
2.4.0 is what we check for.
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I've seen this elsewhere, how feasible would it be to add such a thing
to gschem/gnetlist?
Somewhere on the schematic, include a table. This table has three
colums: refdes, pin, netname.
The table would have to be a real object, not just decorated text. It
would have to retain the
I'm particularly slow today, but to what end would somebody need/use
this mechanism? Adding power nets to a schematic/component?
Remapping of power pins? Both?
Yes. Mostly, the connecting-power-pins-for-slotted-gates problem.
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Why not support both? Have the table read from a separate file.
Me, I'd rather have that page's power nets specified on THAT page, so
I don't forget about them when updating symbols.
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Why put in in the schematic?
So it gets printed with the rest of the schematic?
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I am not sure that would add the same feature.
No, but I thought you might be interested anyway.
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A simpler solution is to remember if we auto-converted the footprint
to a board, and save the right thing when asked.
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Similar to MinMaskGap()
Comments on name, syntax, action?
Index: action.c
===
RCS file: /cvsroot/pcb/pcb/src/action.c,v
retrieving revision 1.130
diff -p -U3 -r1.130 action.c
--- action.c5 Jul 2008 19:19:38 - 1.130
one thing we noticed with gerbv is that using cairo rendering under
windows is *way* faster than using gdk rendering. pcb is using gdk
for its rendering. I'm not sure about gschem. So I wonder if
migrating to cairo would help in this area. The question is if it
hurts X11 performance
Is there any basis for this other than the FSF's claims?
As Ales has asked this thread to end, I'll end my participation with a
simple statement: The GPL has not been well tested in court, so the
actual results depend on what a judge decides. Until there's more
relevent case history, we're all
, Michael Leonov, DJ Delorie, Dan
McMahill...
This is why projects like GNU always require a copyright assignment or
disclaimer. It keeps the number of owners at one, simplifying
copyright issues. This is how the FSF can easily change projects from
GPL2 to GPL3.
The or later clause allows
That's why I would love to see something definitive from the FSF
I don't think I'd trust something from the FSF; they appear to be
somewhat out of touch with copyright reality. For example, I've seen
it reported that they appears to believe their license can bind code
not covered by it -
Which, I believe, is simply _wrong_.
It's a license, it's neither right or wrong. You choose to accept it,
or you don't. It doesn't *force* you to do anything.
As I said, in view of this - an apparent belief that the GPL can bind
code that bears no relation in copyright law anything GPLed
Does anyone know if there is any compatibility issue with
distributing or managing a mix of GPLv2 and GPLv3 code?
In general, if it's a mere aggregate the licenses don't affect each
other. In other words, if two programs can be used independently,
they can be licensed independently. License
In practice, this is usually handled by not attempting to optimise
routines that include a call to setjmp(), but putting in phantom
control-flow edges is a (usually very pessimistic) alternative.
There are some optimizations that can't be made when you use setjmp,
but they're minor. Assume
If you're willing to assume you're using gcc,
We're not.
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Running make in pcb/doc/gs gave that it is missing eps2png
Where can I get that program ?
I don't recall where I downloaded it from, but here it is:
#!/usr/bin/perl
my $RCS_Id = '$Id: eps2png.pl,v 2.2 2001-06-25 18:35:25+02 jv Exp $ ';
# Author : Johan Vromans
# Created On :
I think I'm ready to commit the getting started guide to CVS. Here's
the sources (plus a few utilities):
http://www.delorie.com/pcb/gs-source.tar.gz
Could some of you test this on your platforms to make sure it
basically works? It will probably need some interaction with
maintainer-mode and
Also, I've been prodding some stuff with polygons. I noticed rendering
benchmarks spent a lot of time in the no holes polygon dicer.
Yup.
I've changed things such that polygons can take the CLEARLINE
flag, (j on the keyboard bindings), to change if a polygon clears
other polygons or not.
Still... 100 in internal PCB units is what - 1mil?
Currently, yes.
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This would be much simpler if pads just used the polygon code.
Or if it were better object-oriented, and you could just let
everything do their own tasks? ;-)
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I was suggesting that supporting rotated pads would be easier if they
were a sub-type of polygon (or used Polygons internally - just like pin
thermals do).
You're saying this is wrong?
Rotated *square* pads, fine. Rotated *round* pads are better
classified as lines.
In general, it looks good, but all that vector math probably needs a
closer look to make sure all the signs are right. Or we need a draw
bounding box option for pcb ;-)
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Yep - thats how I tested it. I have the code to do that as a separate
patch in case I needed to do any more testing again later.
I would be amenable to checking that patch in also, with an #if 0
around it, for the next time we need to debug that.
Ales Hvezda [EMAIL PROTECTED] writes:
Great, thanks for posting this information. Why did you
create the various new attributes? I wasn't planning on creating
any new attributes and the existing slotting mechanism would stay
the same
I like the idea of the light symbols having
Now, if we could name busses that way, and assign them multiple
pins...
Elaborate please?
I want to name a pin something like A[0-15]
The pin number would be something like 14-18,20,22,25-33
It would attach to a bus directly (inhereting the net name from the
pin name) or with a bus
Does verilog use gschem's bus thing, or just the net thing, for
connectivity?
I suppose we can get by without bus-level connectivity checking in
gnetlist, though.
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Consider a resistor. The vast majority of resistors in my designs
are 0805.
More interesting in my case are capacitors. I default to 0603 size,
and use larger sizes if needed. So, I specify capacitors by uF and V,
and I want the software to automatically select 0603 footprint devices
if it
Well, I am not people and can only speak for myself. I am all in
favor of footprint mapping inside gschem.
I'm all in favor of keeping the mappings inside the schematic too, as
hidden attributes (migrated to pcb footprint attributes), but I see no
need to restrict *editing* them to gschem.
I'm sure there is some kind of export it could be persueded to do. What
does the previews for gedasymbols.org footprints?
pcb -x png $footprint
I hacked up some mods to PCB (not committed) which attempt to make the
library-chooser work without any other GUI windows being open - so you
can
What do people think of the whole idea of running an external program
(like Cvpcb) to assign footprint information?
What, like gattrib? ;-)
I've stated this before, but to recap...
The schematic symbols should be as light as possible, with some
database mapping symbols to physical devices,
DJ, are you talking laminating photo-etch-resist film to the copper
laminate,
The photosensitive film is laminated to the bare copper, producing a
negative sensitive board.
The printed mask is just laid on top of that, then a sheet of glass to
hold it against the board. Normally you'd use a
Ah so... all components are optimized in same direction with
subtractive etching, negative resist, a negative phototool
minimizing ink printed and maximizing copper left on the board,
which minimizes chemicals used and waste generated.
Pretty much. An ink-less page results in 100% UV cure,
Where are you guys getting this dry film photoresist?
http://www.pcbhobbyist.com/
He bought a big roll of it and has been selling it piecemeal.
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What model are you using?
I'm using an Epson R280, but only because it came free with my digital
camera. It does 2880x5760 but I use 2880x2880 for the films. Also,
I've tried quarter sheets but the printer can't get as good a grip on
them as it can a half sheet, and ends up mis-registering
This looks excellent: http://www.delorie.com/pcb/inkjet/mask-csp.jpg
Ah, that's a 0.5mm CSP footprint with 5 mil line/space rules, although
most of the lines (the non-diagonal ones) are 6 mil. I just got the
rest of the parts for that board, so I can try populating.
How is the sensitivity to low light? Can you align and get ready
for photomask exposure with a 60 watt incandescent light in the
room?
My basement uses 100w compact fluorescent bulbs, and there are a
couple of windows. I take care with the roll of unused film, keeping
it in a blackout bag
I originally bought this stuff because I thought that it would save
time and money to build prototypes myself but after building the
first board, which was successful, I decided that my time would be
better spent on designing circuits.
Yeah, it's not something everyone finds rewarding. I
[moved to geda-dev and subject changed]
It's not supposed to be possible to create them,
Easy to do if you draw two non-co-linear lines and move the endpoints
to become co-linear.
Given that, I was able to produce a corrupt polygon with two lines and
a rectangle (see pcb below). This doesn't
I may try to be physically present at the next one, if I can scrape
together the funds!
I'll try to accomodate your schedule next year, if you're in the area :-)
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10am to 5pm EST
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I've seen something similar myself, if you have two symbols with the
same refdes AND the same pin numbers, you get TWO nets for the common
pins, not a combined net. Here's a schematic with such a case:
http://www.delorie.com/electronics/m16c-26-adapter/
I have one connector symbol for the MCU,
Reminder that the Freedog cookout and sprint is this Sunday, the 29th,
from our usual 10am to 5pm, at my house (email if you need
directions). Family are welcome, but the weather isn't looking
promising yet. If it rains it will be a cook-in instead ;-)
DJ
One of these days I need to fly over and come to one of these events, DJ!
Next time you fly over during the summer, we'll plan one for you :-)
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btw, is there a board available that exercises most of the features
of gEDA's pcb? Maybe something from DJ Delorie?
I certainly have plenty of boards to show, but I never thought about
feature-completeness. The furnace board, for example, has SMT (both
sides) and through-hole, multi layers
It looks like 28 June is bad for me as well. 29-June should be OK.
It looks like the 29th then. I'll mark my calendar.
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Beautiful house...I like the trees (I am a tree lover from California).
Thanks!
Where is your house? ...if you are in California I might be able to make it.
New Hampshire.
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I wonder if ARC_LOOP was intended to be used for both elements and
layers? We could #define to be the other.
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Which layer is the component layer?
The group that includes the 'c' layer.
Don't confuse drawing layers with copper layers. In the 1,2,c case
you have two drawing layers (1 and 2) plus a tag (c) that says that
group represents the component-side copper layer. *Groups* map to
physical layers,
gschem. I have no idea how to clear this cache, but closing / re-opening
hash -r gschem
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