2009/5/12 Joerg joerg...@analogconsultants.com
For guitar pickup modelling, you might like to do a bit of Googling on
spice model guitar pickup or similar.
Yes, that is a very interesting page. This is precisely the kind of
thing I'm interested in. I had no idea the capacitance of the
Quick tip on your schematic: it's a good idea to offset 4 wire
junctions (C1, R1, R2 Q1b) so that they appear as two pairs of 3
wire junctions. That way even if the junction dot disappears in a .png
or .pdf or whatever, it is obvious that the 4 wires are all joined and
it's not just 2 wires
Hello everybody,
I am trying to create a footprint with a correct name using the IPC-7351
Naming Convention for Standard SMT Land Patterns.
But I am having some issues, i am using the below document to learn about
the naming convention:
On Wed, 2009-05-13 at 14:45 +0200, Jelle de Jong wrote:
Could somebody help me out by making an example for the 54-pin TSOP II
footprint?
I can not open your linked PDF documents, I get security warnings like
this:
secure.powercraft.nl uses an invalid security certificate.
The
Jelle de Jong wrote:
Hello everybody,
I am trying to create a footprint with a correct name using the IPC-7351
Naming Convention for Standard SMT Land Patterns.
But I am having some issues, i am using the below document to learn about
the naming convention:
Someone asked how one can build PCB boards like this:
http://www.mikrocontroller.net/topic/137821#new
(Click on the picture too enlarge)
This layout may have advantages if PCB is made mechanical, i.e. by
milling machines.
So I asked myself is current PCB can do it -- I guess not, but I may be
Interesting idea.
Looks like it's a single (maybe double) sided through hole PCB.
Probably only a low frequency board.
I can see this may have some advantages for high current and therefore
maybe switch mode PSU's but it may only have limited use for the
following reasons:
i) All tracks have
Stefan Salewski wrote:
http://www.mikrocontroller.net/attachment/50837/Beispiel.jpg
This layout may have advantages if PCB is made mechanical, i.e. by
milling machines.
That kind of layout has etchant cost minimization as advantage also.
John
Andy Fierman wrote:
Could open a whole new topological discussion on auto routers though :)
I don't know how you could automate the boundary descriptions, but once
you had that then it looks like a basic flood-fill...
b.g.
--
Bill Gatliff
b...@billgatliff.com
Bill Gatliff wrote:
Andy Fierman wrote:
Could open a whole new topological discussion on auto routers though :)
I don't know how you could automate the boundary descriptions, but once
you had that then it looks like a basic flood-fill...
Typically this isn't done fully automated. One
Hi gEDAns,
I'm one of the developers of Fritzing. I know I'm coming to this
thread rather late but I have a few comments and clarifications...
First, I think some of the initial debate and criticism was based on
looking at our old (archive.fritzing.org) web site that had a bunch of
early
On Wed, May 13, 2009 at 10:16 AM, Stefan Salewski
[1]m...@ssalewski.de wrote:
Someone asked how one can build PCB boards like this:
[2]http://www.mikrocontroller.net/topic/137821#new
(Click on the picture too enlarge)
This layout may have advantages if PCB is made
Joerg írta:
Bill Gatliff wrote:
Andy Fierman wrote:
Could open a whole new topological discussion on auto routers though :)
I don't know how you could automate the boundary descriptions, but once
you had that then it looks like a basic flood-fill...
Typically this isn't done fully
Kai-Martin Knaak írta:
On Mon, 11 May 2009 17:52:04 -0400, DJ Delorie wrote:
Note that you can change PCB's internal default by changing MASKFRAME
in the top-level globalconst.h.
Setting must be done at compile time, is it ?
That default, yes.
Would it be difficult to add this to the
Kovács Levente wrote:
Joerg írta:
Bill Gatliff wrote:
Andy Fierman wrote:
Could open a whole new topological discussion on auto routers though :)
I don't know how you could automate the boundary descriptions, but once
you had that then it looks like a basic flood-fill...
Typically
On Wednesday 13 May 2009, Brendan Howell wrote:
for expediency we hacked up a quick output to Eagle.
I saw that, opened mouth too soon.
While the demo was cool, it quickly turned into an unpleasant
experience for coders as we reached the limitations of the
GUI framework (not to mention the
On Tue, May 12, 2009 at 6:43 PM, Joerg joerg...@analogconsultants.com wrote:
Michael B Allen wrote:
Anyway it looks like their AC generator is using 2mV. So the 20mV
value I used to get a good output SIN looks closer to reality which
means my model is probably ok.
I wish I had a real
On Tue, 2009-05-12 at 23:31 +, Kai-Martin Knaak wrote:
I'd love to point my coworkers to a place where they can get everything
they need to install gschem/pcb in a windows context. If web space is an
issue, I may dedicate bandwidth either on my private website or at the
university of
On Wed, May 13, 2009 at 04:16:26PM +0200, Stefan Salewski wrote:
Someone asked how one can build PCB boards like this:
http://www.mikrocontroller.net/topic/137821#new
(Click on the picture too enlarge)
This layout may have advantages if PCB is made mechanical, i.e. by
milling machines.
I could offer up space on my personal web site as well. Only 2Mbps ougoing BW,
but there's no monthly limit so if only one or two people are hitting it at a
time, it would probably suffice.
Dave
-Original Message-
From: geda-user-boun...@moria.seul.org
On Wed, 13 May 2009 17:41:54 +0200, Kovács Levente wrote:
You can change the mask size after you convert the
footprint, of course.
With the GUI? How?
1) activate tht display of the mask
2) let the mouse float above the pin
3) type [k] several times to increase mask clearance
3a) type
On Tue, May 12, 2009 at 6:31 PM, Kai-Martin Knaak k...@familieknaak.de wrote:
On Mon, 11 May 2009 19:14:26 -0400, DJ Delorie wrote:
PS: I use gEDA on cygwin. I have a cygwin mirror at work, and I made a
cygwin package for gEDA, as well as making a modified cygwin installer
so that coworkers
On Wednesday 13 May 2009, Peter Baxendale wrote:
I routinely package up cygwin with built gEDA cygwin
executables once a year for our Windows users here. Because
it's once a year it gets a bit out of date, but I'd be happy
to make it available to anyone interested. It has a readme to
tell you
On Wed, 13 May 2009 17:32:37 +0100, Peter Baxendale wrote:
I routinely package up cygwin with built gEDA cygwin executables once a
year for our Windows users here. Because it's once a year it gets a bit
out of date, but I'd be happy to make it available to anyone interested.
It has a readme
On May 13, 2009, at 10:27 AM, al davis wrote:
A while back I made a proposal for a file interchange system
that is neutral in the sense that it is not tied to any
particular target. It's based on the structural subset of
Verilog.
But that's essentially a netlist format. It's already easy
On Wednesday 13 May 2009, John Doty wrote:
The graphics problem is 1000x harder, but gets almost no
mention in your proposal.
The intent is not to translate the symbols themselves, any more
than moving between text markup formats translates fonts.
My proposal does consider placement, which
Hi,
Maybe off-topic a bit...
I just recieved an Avnet Spartan-3A Evaluation Kit. It has the above
mentioned interface for downloading configuration. I only found Win
based software for it.
Has anyone any experience with it under Linux?
Thanks,
/sza2
Tamas Szabo wrote:
I just recieved an Avnet Spartan-3A Evaluation Kit. It has the above
mentioned interface for downloading configuration. I only found Win
based software for it.
Has anyone any experience with it under Linux?
I did some work with PSoC a few years ago and wasn't able to
On Wed, 2009-05-13 at 12:03 -0700, Eric Brombaugh wrote:
Since their development
IDE is Win-only I didn't see much point in pursuing it further.
Maybe my understanding of your comment is wrong, but to make it clear:
Xilinx FPGA development tools called WebPack are available free of costs
for
Stefan Salewski wrote:
On Wed, 2009-05-13 at 12:03 -0700, Eric Brombaugh wrote:
Since their development
IDE is Win-only I didn't see much point in pursuing it further.
Maybe my understanding of your comment is wrong, but to make it clear:
Xilinx FPGA development tools called WebPack are
Subject:
Re: gEDA-user: geda cygwin package
From:
David C. Kerber [1]dker...@warrenrogersassociates.com
Date:
Wed, 13 May 2009 13:08:07 -0400
To:
gEDA user mailing list [2]geda-user@moria.seul.org
DJ Delorie wrote:
I have not already used their WebPack for Linux, but I am sure it
works.
I use WebPack for Linux, it works just fine. Although, I don't use
any of their programming cables.
___
geda-user mailing list
Eric Brombaugh wrote:
I also use Xilinx ISE (both full-blown and Webpack) under Linux with no
difficulties.
I've used that too, and it's a great source of irritation and amazement
to me that they manage to produce a 1.4GB install file to program a
device the size of a postage stamp! :(
or
al davis wrote:
My proposal does consider placement, which should be enough.
It is essentially a netlist format. That's the idea.
How about having a netlist format that holds footprint center, plus pad/pin
centers
that are defined as center of main part of a pad and center of hole circles,
I believe the electronics industry has already centered on the PADs
ASCII file format which has the netlist, components, foor print's,
layers, lines, vias etc.
I have bumped into pcb and assembly shop requests for this a few times
where they use the information for programming their pick and
John Doty wrote:
On May 13, 2009, at 3:01 PM, John Griessen wrote:
al davis wrote:
pad/pin centers
that are defined as center of main part of a pad and center of hole
circles, and also
pad numbers?
Remember that Al's vision includes schematic translation.
I have not read his starting
Chris Smith wrote:
Eric Brombaugh wrote:
I also use Xilinx ISE (both full-blown and Webpack) under Linux with no
difficulties.
I've used that too, and it's a great source of irritation and amazement
to me that they manage to produce a 1.4GB install file to program a
device the size of a
On May 13, 2009, at 3:01 PM, John Griessen wrote:
al davis wrote:
My proposal does consider placement, which should be enough.
It is essentially a netlist format. That's the idea.
How about having a netlist format that holds footprint center, plus
pad/pin centers
that are defined as
Hi Jelle,
On Wed, 2009-05-13 at 14:45 +0200, Jelle de Jong wrote:
Hello everybody,
I am trying to create a footprint with a correct name using the IPC-7351
Naming Convention for Standard SMT Land Patterns.
But I am having some issues, i am using the below document to learn about
the
On Wed, 2009-05-13 at 15:41 -0400, DJ Delorie wrote:
I have not already used their WebPack for Linux, but I am sure it
works.
I use WebPack for Linux, it works just fine. Although, I don't use
any of their programming cables.
Don't touch their drivers with a barge pole.. use these:
I use WebPack for Linux, it works just fine. Although, I don't use
any of their programming cables.
Don't touch their drivers with a barge pole.. use these:
I said *cables* so of course none of the standard drivers would work
for me anyway. I write my own.
On Wed, 13 May 2009 14:12:52 -0700, Steve Meier wrote:
I believe the electronics industry has already centered on the PADs
ASCII file format which has the netlist, components, foor print's,
layers, lines, vias etc.
Is this standard open in any way?
That is, can it be read without signing a
Kai-Martin Knaak wrote:
On Wed, 13 May 2009 14:12:52 -0700, Steve Meier wrote:
I believe the electronics industry has already centered on the PADs
ASCII file format which has the netlist, components, foor print's,
layers, lines, vias etc.
Is this standard open in any way?
That is, can
Brendan Howell wrote:
Hi gEDAns,
We looked at easily a dozen different GUI frameworks before
chosing Qt.
We don't really see Fritzing as competing with the other open
source/free EDA tools. Our target audience is largely hobbyists,
students, designers and artists: essentially,
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