On Sun, Jan 10, 2010 at 6:04 PM, Ben Jackson b...@ben.com wrote:
On Sat, Jan 09, 2010 at 05:41:05PM -0800, Ben Jackson wrote:
I meant automatic solutions which would enforce the normal DRC rules on
the slivers, eliminating any smaller than the minimum trace width.
(replying to myself)
On Tue, 23 Feb 2010 11:16:45 +1300, Anthony Blake wrote:
I don't get a lot of time atm.. please jump in =)
Ok, then. Can you compile a list of tasks that need to be accomplished
before the topo router is ready for general use? The smaler the
individual tasks, the more likely they can be
Hello all,
I did an oval shape hole once by using three overlapping round drill
holes, worked fine. maybe you can do the same with 6 small round holes:
ooo
ooo
ooo
Cheers, Robert
-Original Message-
From: Dave N6NZ n...@arrl.net
Reply-to: gEDA user mailing list geda-user@moria.seul.org
On Mon, 22 Feb 2010 21:53:46 -0800, Dave N6NZ wrote:
Really? Is there a use for gEDA-Eagle?
There is at my place. I represent an island of geda in an eagle using
environment. Eagle is pretty popular in German academia. If I want to
share my work with them, a conversion path to eagle would
Hello Jimen,
Are you still at this address? I have a new version of vbpp to offer. Can
you please grant me access to
http://svn.seul.org/viewcvs/viewvc.cgi/eda/vbpp/?root=SEUL
You can find my version of vbpp here:
http://www.verilog.net/vbpp-1.2.0.tar.gz
Thanks,
Martin
On Tue, 9 Feb 2010,
al davis wrote:
I proposed a translator system, using an intermediate language,
to translate both ways between schematic, layout, and
simulation. It needs to happen.
I've got a phone call to Reid Wenders of Triad scheduled this PM.
Anyone have any ideas you'd like mentioned to him?
Hi,
I noticed a small issue with the line spacing in the postscript output
of gschem. It appears to be that the text line spacing is not
consistent with the font scaling when output to postscript. Here is a
screenshot to show the difference between the gschem scaling and the
output postscript
On Tue, 2010-02-23 at 22:07 +0200, Duncan Drennan wrote:
Hi,
I noticed a small issue with the line spacing in the postscript output
of gschem. It appears to be that the text line spacing is not
consistent with the font scaling when output to postscript. Here is a
screenshot to show the
On Tue, 2010-02-23 at 22:01 +, Peter Clifton wrote:
Hmm... this will all be fixed when I get my backside into gear and
finish up the cairo printing support... until then, I'm not sure..
It might be something we can fix in the existing printing code, but it
could also just be a failing of
I have daydreamed about the possibility of linking gEDA with qucs and
simavr/gdb for example. To be able to create a circuit layout and
perform harmonic ballance simulation combined with microcontroller
code simulation... Oh, and while I daydream, an integrated tool for
doing FEM analysis the pcb
The attached patch should make things a little closer between on-screen
and print-out.
Apparently this isn't the whole story though, on my box at least, Pango
seems to be using a little inter-line spacing. The calculations with
this patch assume that a 12 point font has 12/72 inches between each
On Wed, 2010-02-24 at 09:46 +1100, Geoff Swan wrote:
I have daydreamed about the possibility of linking gEDA with qucs and
simavr/gdb for example. To be able to create a circuit layout and
perform harmonic ballance simulation combined with microcontroller
code simulation... Oh, and while I
On Tue, 2010-02-23 at 23:02 +, Peter Clifton wrote:
The attached patch should make things a little closer between on-screen
and print-out.
Apparently this isn't the whole story though, on my box at least, Pango
seems to be using a little inter-line spacing. The calculations with
this
Kai-Martin Knaak wrote:
On Tue, 23 Feb 2010 11:16:45 +1300, Anthony Blake wrote:
I don't get a lot of time atm.. please jump in =)
Ok, then. Can you compile a list of tasks that need to be accomplished
before the topo router is ready for general use? The smaler the
individual tasks, the
On Tuesday 23 February 2010, John Griessen wrote:
Anyone have any ideas you'd like mentioned to him? Questions
I should ask? I'm just planning on telling him the status of
verilog-ams backend of gnetlist and that it can run some
simulations from a netlist -- the way it needs to be for
On Mon, 2010-02-22 at 20:02 -0800, Jared Casper wrote:
On Mon, Feb 22, 2010 at 3:42 PM, Peter Clifton pc...@cam.ac.uk wrote:
I'm tempted to pay someone a bounty to kill those with fire ;)
(or certainly fix the message window's focus-stealing, attention
grabbing - behaviour. The same is
On Sun, 2010-02-21 at 11:26 +, Peter Clifton wrote:
Looks like a mistake.. PCB has defgnetlist hard-coded rather than
gnetlist.
Try with this environment variable set as a work-around for now:
PCB_GNETLIST=gnetlist
This is no longer necessary.. I fixed the hard-coded default to be
Peter Clifton wrote:
On Wed, 2010-02-24 at 09:46 +1100, Geoff Swan wrote:
I have daydreamed about the possibility of linking gEDA with qucs and
simavr/gdb for example.
My phone conversation today with Mr Wender of Triad was about verilog-ams and
the
possibilities it offers mostly. One way
[snip]
So let me ask again, how do I upload it here:
http://svn.seul.org/viewcvs/viewvc.cgi/eda/vbpp/?root=SEUL
You really to get permission from the author of the vbpp to
get write access to his repository. I did see some of the e-mails that
you sent, but until you get a response,
On Tuesday 23 February 2010, John Griessen wrote:
Al, are you saying that Icarus verilog would run along side
of gnucap once that interface is ready?
Icarus has two key parts .. A compiler, and a virtual machine.
In its normal use, the compiler generates code for the virtual
machine, then
[snip]
You really to get permission from the author of the vbpp to
^
\- need
get write access to his repository. I did see some of the e-mails that
[snip]
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On 02/23/2010 06:46 PM, Anthony Blake wrote:
Ok, then. Can you compile a list of tasks that need to be
accomplished before the topo router is ready for general use? The
smaler the individual tasks, the more likely they can be tackled by
low time hackers like me...
For sure. It would require
After a very long time, I am just about ready to send out 3 different
boards for fab. I would appreciate any advice to improve my chances of
success. So far here's what has been done:
1. Run DRC on all PCBs with no issues..
2. Checked schematics.
3. Checked schematic matches layout.
4. In
Print out your surface copper layers and put the parts on the printout
to make sure they match.
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DJ Delorie wrote:
Print out your surface copper layers and put the parts on the printout
to make sure they match.
that's a really good idea, thanks! It'll delay things some, but yeah,
sounds like the conservative way to go. I'll have to order up a bunch
of parts to make it happen but that's
Check the gerbers and drill files using gerbv.
I use a script that zips and renames all the files for the fab house.
I take the zip file that is created, unzip it and check those files
with gerbv.
For a system of boards that plug into each I might panelize them
so that they all
John Luciani wrote:
Check the gerbers and drill files using gerbv.
I use a script that zips and renames all the files for the fab house.
I take the zip file that is created, unzip it and check those files
with gerbv.
For a system of boards that plug into each I might panelize them
On Tue, Feb 23, 2010 at 8:01 PM, gene glick carzr...@optonline.net wrote:
After a very long time, I am just about ready to send out 3 different boards
for fab. I would appreciate any advice to improve my chances of success.
So far here's what has been done:
1. Run DRC on all PCBs with no
[cc'ing geda-user since it looks like my subscription is all sorted out]
On Feb 19, 2010, at 9:54 AM, Peter TB Brett wrote:
Charles Lepple wrote:
Peter,
sorry to email you directly, but I am having some issues
subscribing to geda-user. (I'll email Ales later today.)
I am trying to
On Tue, 23 Feb 2010 22:18:02 -0500
gene glick carzr...@optonline.net wrote:
DJ Delorie wrote:
Print out your surface copper layers and put the parts on the printout
to make sure they match.
that's a really good idea, thanks! It'll delay things some, but yeah,
sounds like the
On Tue, Feb 23, 2010 at 3:53 PM, Peter Clifton pc...@cam.ac.uk wrote:
I can't help but feel that some log messages are important enough to
bother the user about - and others are not.. we'll have to see what
people actually using it think, I'm not doing any PCB design work at the
moment myself.
This one adds a 12% leading to the text spacing for print, causing it to
pretty well match my on-screen leading. YMMV depending on what fonts
your system chooses.
Thanks Peter, I'll try it out and give you some feedback.
Regards,
Duncan
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