Okay, courtyard. Thanks for the nomenclature help :-)
I'm just thinking of a couple of parts for a design that I'm working on
where I need to make sure that I don't put any more parts in between
areas of the footprint, but traces are ok because they're part of the
board and won't
PCB has nothing special for keep-outs of any sort.
I just use the silkscreen to show where the part goes, including the
courtyard.
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Peter Clifton wrote:
Perhaps someone might like to take a stab at fixing this bug:
https://sourceforge.net/tracker/index.php?func=detailaid=3064413group_id=73743atid=538811
I've triaged the cause of the crash, but don't really have the energy to
start digging into the DRC engine's rules.
I
Hi all,
-Original Message-
From: geda-user-boun...@moria.seul.org
[mailto:geda-user-boun...@moria.seul.org] On Behalf Of Bob Paddock
Sent: Sunday, September 12, 2010 1:40 AM
To: gEDA user mailing list
Subject: Re: gEDA-user: next PCB release - 1.99za vs 4.0
In Protel there
On Sun, Sep 12, 2010 at 12:24 AM, DJ Delorie [1...@delorie.com wrote:
The top/bottom magic are needed to map footprints on
import
Don't over look buried components. Becoming more common.
I think it would be better to just have layers, that you assign a
function to, rather
On Sun, Sep 12, 2010 at 12:55 AM, DJ Delorie [1...@delorie.com wrote:
I suspect that in the main GUI you'd get a simplified set of
options,
like add layers or remove layers to switch from, say, 2-layer
PCBs
to 4-layer PCBs, etc.
In Protel there is such a dialog.
On Sun, Sep 12, 2010 at 1:40 AM, Jonathon Schrader
jlsch...@jlschrad.net wrote:
That is, a footprint (such as the battery mount mentioned previously) with a
requirement not to place any parts between the tabs, but traces are fine?
It would be good to be able to say place no component
Hi all,
-Original Message-
From: geda-user-boun...@moria.seul.org
[mailto:geda-user-boun...@moria.seul.org] On Behalf Of Bob Paddock
Sent: Sunday, September 12, 2010 1:52 PM
To: gEDA user mailing list
Subject: Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010
Maybe you could add an attribute to an element defining the height.
Something like: Attribute (element_height=, 5 mm)
That would be required to do 3D also. There would also need to be a
clearance space above the actual part thickness as well.
Think about boards that are flexing/vibrating.
On Sun, 12 Sep 2010 14:49:02 +0900
timecop time...@gmail.com wrote:
Most places handle this with the assembly layer.
Of course, this wouldn't be part of DRC, but you'd have to be blind
put stuff overlapping assembly layers and not see it right away.
Imagine having to make a change to the
On Sun, Sep 12, 2010 at 12:55:54AM -0400, DJ Delorie wrote:
I suspect that in the main GUI you'd get a simplified set of options,
like add layers or remove layers to switch from, say, 2-layer PCBs
to 4-layer PCBs, etc. Outer special layers like silk and mask just
exist, but you can
I think it would be better to just have layers, that you assign a
function to, rather than have layers have magic properties.
As flexible as I'd like to be, I think it's implied when designing
circuit boards that there's going to be outside layers on them.
From a practical viewpoint,
When you say just exist, you mean they are there by default on new
boards, not that they're magic layers, right?
There by default on new boards - yes
not magic - well, I still think intended purpose is something that
PCB needs to know about, to do its job well. We can allow for
exceptions by
Vanessa Ezekowitz wrote:
Maybe you're tired, maybe the board just has a metric assload of
parts, maybe you're pressed for time. Who knows?
+1
This is what DRC is meant for. A reliable check for stupid errors. I
often feel like doh, how could I be so blind when DRC shows
violations.
On Sun, Sep 12, 2010 at 12:53:57PM -0400, DJ Delorie wrote:
Well, a both-sides silkscreen layer makes little sense. If a user
wanted that, he could duplicate the top silkscreen to get the bottom
one. I don't think that would be common enough to require special
code.
Outlines for
Well, a both-sides silkscreen layer makes little sense.
Actually it does make sense. Think about a transformer with through-hole pins.
You want the top silk to show the courtyard, for clearances. You want
the bottom silk to show the pin numbers/labels.
--
http://blog.softwaresafety.net/
On Sun, Sep 12, 2010 at 12:38 PM, DJ Delorie d...@delorie.com wrote:
I think it would be better to just have layers, that you assign a
function to, rather than have layers have magic properties.
As flexible as I'd like to be, I think it's implied when designing
circuit boards that there's
Alright, we'll allow a top and bottom layer group.
With flex cable, top and bottom aren't limited to one layer each.
I think that if we want components on multiple layers (or all
layers), that should be a property of the component, not a layer
group/physical layer thing.
What's
Flex Circuit in a Mobius configuration.
They still have outsides, just not two of them.
I'm going to go out on a limb and state that I refuse to support
non-flat layers :-)
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On Sep 12, 2010, at 10:35 AM, Bob Paddock wrote:
Well, a both-sides silkscreen layer makes little sense.
Actually it does make sense. Think about a transformer with through-hole
pins.
You want the top silk to show the courtyard, for clearances. You want
the bottom silk to show the pin
On Sun, Sep 12, 2010 at 01:56:43PM -0400, DJ Delorie wrote:
Alright, we'll allow a top and bottom layer group.
With flex cable, top and bottom aren't limited to one layer each.
Aren't they? All layers except the top-most and bottom-most are
considered inner layers. This whole
On Sun, Sep 12, 2010 at 01:57:32PM -0400, DJ Delorie wrote:
I meant ONE silk layer printed on BOTH sides of the pcb. Much like
fabs often have an option for same mask both sides - one layer, used
twice.
Okay, I see what you're gettting at here with same layer, multiple
physical layers. And
With flex cable, top and bottom aren't limited to one layer each.
Aren't they?
No. Different areas of the cable may have extra layers or pcbs
attached, changing the number of layers in that area. So one drawing
layer might be top on the left side of the cable, but inner on the
right side.
Now, how is the relationship between drawing layers and physical layers
going to be shown to the user?
I think dual-color traces would be nice. (That is, have the main color
correspond to the physical layer, with a stripe on the left side (say)
corresponding to the drawing layer.)
What
At 04:46 PM 9/11/2010, you wrote:
On Sat, Sep 11, 2010 at 09:28:16PM +0200, kai-martin knaak wrote:
Peter Clifton wrote:
Yes, indeed.. magic silk (and other) layers should probably go
and die.
Please do. My local list of warts and rooms for improvement contains
many complaints about
At 03:42 PM 9/10/2010, you wrote:
On Sep 10, 2010, at 1:01 PM, DJ Delorie wrote:
I figure we need each layer to specify:
* type (copper, silk, mask, anti-copper, keepout, etc)
There are no types, there are only properties.
The conductors may not be copper. I've even worked with a board
At 03:45 PM 9/12/2010, you wrote:
Interesting thought - for buried vias, the top and bottom layers
correspond to inner physical layers, yet they need to be treated
differently as the annulus often needs to be bigger on layers where
the trace connects. So an internal buried via element, before
Bigger??? Why do you need an annulus on an inner layer that doesn't
connect to a trace?
Depending on the fab technique, you may need an annulus just to fill
the gap between fr4 layers so that the electroplating is reliable.
Either that, or you need to keep *other* copper far enough away that
On Sun, Sep 12, 2010 at 03:45:18PM -0400, DJ Delorie wrote:
Interesting thought - for buried vias, the top and bottom layers
correspond to inner physical layers, yet they need to be treated
differently as the annulus often needs to be bigger on layers where
the trace connects. So an
On Sun, Sep 12, 2010 at 03:40:24PM -0400, DJ Delorie wrote:
With flex cable, top and bottom aren't limited to one layer each.
Aren't they?
No. Different areas of the cable may have extra layers or pcbs
attached, changing the number of layers in that area. So one drawing
layer
On 09/12/2010 03:17 PM, Windell H. Oskay wrote:
On Sep 12, 2010, at 10:35 AM, Bob Paddock wrote:
Well, a both-sides silkscreen layer makes little sense.
Actually it does make sense. Think about a transformer with through-hole pins.
You want the top silk to show the courtyard, for
At 04:06 PM 9/12/2010, you wrote:
Bigger??? Why do you need an annulus on an inner layer that doesn't
connect to a trace?
Depending on the fab technique, you may need an annulus just to fill
the gap between fr4 layers so that the electroplating is reliable.
Either that, or you need to keep
On Sun, Sep 12, 2010 at 01:56:43PM -0400, DJ Delorie wrote:
http://download.wpsoftware.net/code/pcb/layer.h
I would add a LayerPos to each Layer, and store the Layers separately.
Okay, here is the structure: attached to the PCB is a physical layer stack.
This has a well-defined stacking
On Sun, 2010-09-12 at 06:57 +, ineiev wrote:
Peter Clifton wrote:
Perhaps someone might like to take a stab at fixing this bug:
https://sourceforge.net/tracker/index.php?func=detailaid=3064413group_id=73743atid=538811
I've triaged the cause of the crash, but don't really have the
On Sep 12, 2010, at 12:29 PM, Andrew Poelstra [1]as...@sfu.ca wrote:
On Sun, Sep 12, 2010 at 01:56:43PM -0400, DJ Delorie wrote:
Alright, we'll allow a top and bottom layer group.
With flex cable, top and bottom aren't limited to one layer
each.
Aren't they? All layers
On Sep 12, 2010, at 1:49 PM, Rick Collins wrote:
At 03:42 PM 9/10/2010, you wrote:
On Sep 10, 2010, at 1:01 PM, DJ Delorie wrote:
I figure we need each layer to specify:
* type (copper, silk, mask, anti-copper, keepout, etc)
There are no types, there are only properties.
The
does anyone have experience with this package? I want to know if they
are hard to work with. The exposed pad underneath is a problem for hand
soldering - but maybe could be left unsoldered for prototypes. Maybe
just place some solder paste under there ? If the pcb pads are long
enough, is it
get a stencil, get solder paste, apply paste over stencil, heatgun, done.
super simple. dont even bother doing it manually pin to pin, it
probably wont work.
On Mon, Sep 13, 2010 at 10:46 AM, gene glick carzr...@optonline.net wrote:
does anyone have experience with this package? I want to know
And I think the only way to do ... in a non-kludgy way
Yet another example of you automatically putting down any idea that
isn't yours. Please stop that. Please consider the possibility that
someone might come up with a better (or even equally good) idea than
yours. Constructive criticism is
does anyone have experience with this package?
Just did one today.
I want to know if they
are hard to work with.
Harder than a QFP, but not impossible for home-fab. Pen flux the
bottom of the chip before placing it on the paste - I wish I'd
remember this more reliably :-)
The exposed pad
On Sep 12, 2010, at 7:53 PM, DJ Delorie wrote:
And I think the only way to do ... in a non-kludgy way
Yet another example of you automatically putting down any idea that
isn't yours. Please stop that. Please consider the possibility that
someone might come up with a better (or even
For quick breadboarding of an accelerometer I've deadbug soldered one
successfully. Just superglued it upside down and soldered directly to
the pads with very thin wire..
On Mon, Sep 13, 2010 at 12:04 PM, DJ Delorie d...@delorie.com wrote:
does anyone have experience with this package?
Just
Thinking about drills...
If a cutout is a property of an insulating layer, the a drill through
the whole PCB is really a composite of 2N+1 drills through N insulating
layers and N+1 conductor layers.
That seems kludgy to me. Drilling is a single operation, why do we
have to represent it as
On Sun, Sep 12, 2010 at 11:09:25PM -0400, DJ Delorie wrote:
Thinking about drills...
If a cutout is a property of an insulating layer, the a drill through
the whole PCB is really a composite of 2N+1 drills through N insulating
layers and N+1 conductor layers.
That seems kludgy to me.
...but your number of sub-composites grows exponentially. In
theory, whatever the lowest-level composite is, your sub-composite
set is the power set of that!
No, because fabs can't drill that way. You can't have a copper layer
that's part of two separate sub-assemblies before those
There are a number of different QFN package styles. Some have pads
only on the bottom, others have pads that wrap around the up the side
a bit. These tend to be easier to hand solder since you have a place
to contact with the solder iron. Sounds like yours don't have that
plus they have a
Hi all,
We use Cadence Allegro at work, and how they implement keepouts may be
interesting. There are several non-copper layers that are used to control the
keep outs and keep-in. In this tool the keep in / keep out is related to how
courtyards are defined.
Each library symbol (called a
On Sun, Sep 12, 2010 at 11:49:33PM -0400, DJ Delorie wrote:
...but your number of sub-composites grows exponentially. In
theory, whatever the lowest-level composite is, your sub-composite
set is the power set of that!
No, because fabs can't drill that way. You can't have a copper layer
but we've still got a user-interface problem.
We're used to that.
So what happens for those users?
They get exactly one composite, which ends up acting just like what we
have today - one outline, one set of drills, all copper/insulator are
on the one plain-built board.
In our previous
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