On Fri, 2011-01-14 at 21:14 -0500, al davis wrote:
Reading a file is easy. The hard part about the geda format,
where use of libgeda may be advantageous, is establishing
connectivity.
A mix of libgeda, with gnetlist wading in and flattening things (perhaps
unhelpfully). I want to see all
On Sat, 2011-01-15 at 07:54 +, Peter TB Brett wrote:
- Original message -
What is the point of the command Make Inv Text Vis in gschem, other than
aggravating me.
Good question. I'm not aware of a use-case for it either. At the very
least, it should be undo-able. Please
Am 15.01.2011 um 09:47 schrieb Peter Clifton:
On Sat, 2011-01-15 at 07:54 +, Peter TB Brett wrote:
- Original message -
What is the point of the command Make Inv Text Vis in gschem,
other than
aggravating me.
Good question. I'm not aware of a use-case for it either. At the
Lets kill it with fire.
One use-case would be to quickly inspect all of these attributes. It makes a
difference wether you see attributes in a seperate sheet vs. you see them
right next to each symbol.
I don't know if it applies to the feature you are discussing or not,
but I have a use case
Peter Clifton pc...@cam.ac.uk writes:
On Fri, 2011-01-14 at 21:14 -0500, al davis wrote:
Reading a file is easy. The hard part about the geda format,
where use of libgeda may be advantageous, is establishing
connectivity.
A mix of libgeda, with gnetlist wading in and flattening things
a) They have Altium
b) They have bits in Altium already (footprints etc..) - momentum.
c) They need an auto-router which can handle really complex stuff.
Hun? Three of us at work have spent weeks trying to get Altium's
autorouter to do much at all, and do it correctly when it does, and
On Sat, 2011-01-15 at 10:43 +0100, Markus Hitter wrote:
Lets kill it with fire.
One use-case would be to quickly inspect all of these attributes. It
makes a difference wether you see attributes in a seperate sheet vs.
you see them right next to each symbol.
For that we have
On Sat, 2011-01-15 at 07:06 -0500, Bob Paddock wrote:
I don't know if it applies to the feature you are discussing or not,
but I have a use case where I need to turn off global visibility of
values for items.
In any normal schematic, destined for a PCB layout, there is normally
a designator
On Sat, 2011-01-15 at 13:10 +0100, Stephan Boettcher wrote:
What are the use-cases?
IMO, only viewing of synthesis results, or matching up / creating a
schematic which matches an extracted netlist - either from reverse
engineering, layout extraction, or from another program.
--
Peter Clifton
Peter Clifton pc...@cam.ac.uk writes:
On Sat, 2011-01-15 at 07:54 +, Peter TB Brett wrote:
- Original message -
What is the point of the command Make Inv Text Vis in gschem, other than
aggravating me.
Good question. I'm not aware of a use-case for it either. At the very
On 01/15/2011 06:59 AM, Stephan Boettcher wrote:
Yes, please!
+1
John
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
On Sat, 2011-01-15 at 09:10 -0600, John Griessen wrote:
On 01/15/2011 06:59 AM, Stephan Boettcher wrote:
Yes, please!
+1
Consider it napalmed.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel:
Hi folks,
I seem to recall that some guys here use gEDA for chip design. John
Doty comes to mind, but i think there are others too. I'd be interested
in the workflow as i will have to make up some clever test chips in the
next few years for PhD work and i'm not in the position to be able
to sell
Markus Hitter wrote:
One use-case would be to quickly inspect all of these attributes. It
makes a difference wether you see attributes in a seperate sheet vs.
you see them right next to each symbol.
I regularly do this for the footprint attribute with
Attributes -
Any suggestions?
There is also Toped: http://code.google.com/p/toped/
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Hello Florian,
I wish I could say that I could help, but instead I'd like to say I
too am interested in learning what's involved in using gEDA for chip
design.
I'm not even sure where to begin, other than to share the few things
I've thought about so far (however naive or clueless those thoughts
On 01/15/2011 10:52 AM, Florian E. Teply wrote:
Hi folks,
I seem to recall that some guys here use gEDA for chip design. John
Doty comes to mind, but i think there are others too. I'd be interested
in the workflow as i will have to make up some clever test chips in the
next few years for
On Sat, 15 Jan 2011 16:25:39 +
Peter Clifton pc...@cam.ac.uk wrote:
On Sat, 2011-01-15 at 09:10 -0600, John Griessen wrote:
On 01/15/2011 06:59 AM, Stephan Boettcher wrote:
Yes, please!
+1
Consider it napalmed.
Napalmed ain't enough - I want that option *nuked* (from orbit
Consider it napalmed.
Napalmed ain't enough - I want that option *nuked* (from orbit yet).
It's the only way to be sure.
Peter
--
Peter Brett pe...@peter-b.co.uk
Remote Sensing Research Group
Surrey Space Centre
___
Vanessa Ezekowitz vanessaezekow...@gmail.com writes:
On Sat, 15 Jan 2011 16:25:39 +
Peter Clifton pc...@cam.ac.uk wrote:
On Sat, 2011-01-15 at 09:10 -0600, John Griessen wrote:
On 01/15/2011 06:59 AM, Stephan Boettcher wrote:
Yes, please!
+1
Consider it napalmed.
Napalmed
On 01/15/2011 10:52 AM, Florian E. Teply wrote:
Hi folks,
I seem to recall that some guys here use gEDA for chip design. John
Doty comes to mind, but i think there are others too. I'd be interested
in the workflow as i will have to make up some clever test chips in the
next few years for PhD
On 01/15/2011 10:52 AM, Florian E. Teply wrote:
i'd want both simulation as well as generation
of production-ready data (GDS or OASIS files, preferably OASIS), but
have not the slightest idea on how to accomplish that or even if that's
possible with open source software, let alone from within
On 01/15/2011 02:21 PM, Joe Chisolm - Gmail wrote:
Hands-on: Get started in analog IC design and fab (Part 1 of 3)
http://www.eetimes.com/design/analog-design/4010380/Hands-on-Get-started-in-analog-IC-design-and-fab-Part-1-of-3-
It's nice to read about what he stressed as he went after his
http://www.eetimes.com/design/analog-design/4010382/Hands-on-Get-started-in-analog-IC-design-and-fab-Part-3-of-3-
an excerpt from above section:
==
Convergence and noise modeling were key issues. At each change, I had
to learn about the new tool and adapt the models
On 01/15/2011 10:52 AM, Florian E. Teply wrote:
Hi folks,
I seem to recall that some guys here use gEDA for chip design. John
Doty comes to mind, but i think there are others too. I'd be
interested
in the workflow as i will have to make up some clever test chips in
the
I looked at Toped quiet a bit and did not think it was as good as magic
yet. I like the idea behind it, and it is much more modern feeling
that Magic, but it is still pretty immature.
Oliver
__
From: Bob Paddock
On 01/15/2011 07:39 PM, Oliver King-Smith wrote:
I extracted back out of
Magic and reran the extract circuit in LTSpice as my LVS checker. You
can also run a simple LVS in Magic, but I did not find that entirely
reliable.
I'd like to hear more about this. Are you meaning
I extracted back out of
Magic and reran the extract circuit in LTSpice as my LVS checker.
You
can also run a simple LVS in Magic, but I did not find that
entirely
reliable.
I'd like to hear more about this. Are you meaning functional
simulation to decide
on
Oliver King-Smith wrote:
There is no need to use the C++ code if you are a whiz at
scheme, but I really don't like LISP.
You are not alone :-)
Would you contribute the scheme glue script to the project? Maybe
it can even be added to the main distro of gnetlist. What do ye
developers
On Saturday 15 January 2011, Kai-Martin Knaak wrote:
I looked at lang_verilog_in.cc
Unfortunately, my c++ is not fluent enough to read the code
right away. This is aggravated by the lack of comments on
what the various code blocks do. Since I also don't know
verilog by heart, the whole file
On Saturday 15 January 2011, Kai-Martin Knaak wrote:
I don't see how this could possibly work. Both, gschem and
altium contain a graphical representation of the circuit.
Unless I massively missed something, verilog is completely
procedural. Graphics information would be lost during the
On Sat, 15 Jan 2011 17:44:33 -0600
John Griessen j...@ecosensory.com wrote:
On 01/15/2011 10:52 AM, Florian E. Teply wrote:
i'd want both simulation as well as generation
of production-ready data (GDS or OASIS files, preferably OASIS), but
have not the slightest idea on how to accomplish
There isn't much to the glue script, but now that I think about it I
might be able to make it more useful and general purpose. I don't
think it would be appropriate in its current form for distribution to
the general public. It was written specifically for my needs in a
quick and
33 matches
Mail list logo
