I could use some help with this write up!
I'll write something up and ask for reviews soon.
John
Original Message
Subject: Re: [OH Updates] Degrees of open-ness in EDA (and CAD in general)
Date: Sat, 3 Sep 2011 18:58:40 -0400
From: phillip torrone p...@oreilly.com
To: updates
On 09/04/2011 08:10 AM, John Griessen wrote:
I could use some help with this write up!
I'll write something up and ask for reviews soon.
John
Original Message
Subject: Re: [OH Updates] Degrees of open-ness in EDA (and CAD in general)
Date: Sat, 3 Sep 2011 18:58:40 -0400
On Thu, Sep 01, 2011 at 01:39:02AM +0100, Peter Clifton wrote:
On Thu, 2011-09-01 at 00:15 +0400, Vladimir Zhbanov wrote:
The symbols are nice, but there are special state standards in Russia
about what should they look like.
If you can get hold of a copy of the standard for us to look at,
Hello,
I have a strange usability behavior with gschem 1.6.2.20110115 (the version
that comes with ubuntu-11.04). I have attached a small schematic to
illustrate the problem.
In the attached schmatic, when I try to draw a net from U6-pin27 to the
gate of Q6, a little circle appears on the
Peter Clifton wrote:
Have you ever tried the mode Preferences-Alternate window layout
to allow smaller vertical size?
yes :-)
That mode moves the tool buttons underneath the menu-bar in a row,
perhaps that is closer to what you were looking for.
It is linear, but it is coupled with
Josef Wolf wrote:
In the attached schmatic, when I try to draw a net from U6-pin27 to
the gate of Q6, a little circle appears on the nearest pin,
indicating where the connection would be autocompleted to. But even
if the circle appears at the gate of Q6, at the moment I click to
make the
gEDA and KiCAD get a mention ;)
http://www.eevblog.com/2011/08/12/eevblog-195-open-source-hardware-explained/
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the
For the last two (three?) years I used and tested Peters pcb+GL
branch of PCB because it provided the joy of speed and transparency.
If Peter would screw his version, which he rarely did, I could fall
back to git-head from gpleda.org . Fall back to the last relased
version of PCB would have been
Peter Clifton wrote:
gEDA and KiCAD get a mention ;)
http://www.eevblog.com/2011/08/12/eevblog-195-open-source-hardware-explained/
About what point in time?
---)kaimartin(---
--
Kai-Martin Knaak
Email: k...@familieknaak.de
http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53
If this happens too often, I may have to quit using and testing the
cutting edge version. After all, I still have to get my projects
done. I guess, other users feel the same.
This has always been the case. If you want a stable reliable tool,
use a released version, or stick with one
On Mon, Sep 05, 2011 at 03:21:25AM +0200, Kai-Martin Knaak wrote:
Proposal to tone down the impact of patches breaking important features:
Add a branch test to git. This branch would work pretty much like
sid/unstable repo of debian. It would receive all the new stuff so
advanced
On Sun, Sep 4, 2011 at 6:21 PM, Kai-Martin Knaak k...@familieknaak.de wrote:
back to git-head from gpleda.org . Fall back to the last relased
version of PCB would have been not so nice, because of the long
release cycle.
On Sun, Sep 4, 2011 at 7:14 PM, DJ Delorie d...@delorie.com wrote:
use a
Hi all,
I'm using gschem, gnetlist and ngspice to simulate some aspects of my
research work. I am using a technique called Bond - graph modelling
(http://en.wikipedia.org/wiki/Bond_graph), which some of you may be
familiar with.
I have creating symbols for all the elements I require, which are
Maybe give a non-dev volunteer permission to make official
development snapshots, similar to how Icarus Verilog has done in the
past.
Go for it, I say. It's Free Software, they don't need permission,
they just need dedication. If they offer something useful, people
will use it.
Note that I
On Sun, Sep 4, 2011 at 9:52 PM, DJ Delorie d...@delorie.com wrote:
Maybe give a non-dev volunteer permission to make official
development snapshots, similar to how Icarus Verilog has done in the
past.
Go for it, I say. It's Free Software, they don't need permission,
they just need
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