I discovered a box of books that never got unpacked after the last
rearrangement of my home office. Among these, I found several EDIF-related
books. Since I long ago stopped giving a rat's rear end about EDIF, I offer
them to the group. I'm guessing I could stuff them into a USPS flat-rate
On Oct 11, 2010, at 1:43 PM, Stefan Salewski wrote:
-- may long default to 64 bit on 64 bit systems
A well, that depends on the programming model that the system
developers chose. 64 bit systems have been done two ways: LP64 or ILP64, that
is longs and pointers are 64, ints are
Good on you. It really gripes me when open hardware projects use something
like Eagle for the schematic/pcb flow. The current object of my derision for
doing that is the RepRap foundation. Today there are at least two reasonable
choices for open source schematic and pcb design -- why do open
On Oct 9, 2010, at 10:28 AM, Kevin Vermeer wrote:
What can we do to gEDA to make it more accessible to these
folks?
IMHO, the OP is on the right track. It will take less energy and time to
simply fork the designs and push them out to a public repo than to lobby with
the originators.
I
KiCAD -- I haven't tried it myself, so I don't know much about it's
capabilities.
-dave
On Oct 9, 2010, at 3:48 PM, Rick Collins wrote:
I assume one is gEDA... what is the other?
Rick
At 01:56 AM 10/9/2010, you wrote:
Good on you. It really gripes me when open hardware projects use
On Oct 9, 2010, at 6:44 PM, John Griessen wrote:
On 10/09/2010 08:14 PM, Dave N6NZ wrote:
KiCAD -- I haven't tried it myself, so I don't know much about it's
capabilities.
When I first looked at it a couple of years ago it was a small group,
but now it seems to have critical mass
On Oct 8, 2010, at 8:57 AM, Levente Kovacs wrote:
On Fri, 08 Oct 2010 10:31:10 -0400
Rick Collins gnuarm.2...@arius.com wrote:
Personally, I can't imagine a PCB larger than 2 meters much less 4
meters. Or is the possibility of uses other than PCB design being
considered here?
I
On Oct 8, 2010, at 8:57 AM, Levente Kovacs wrote:
On Fri, 08 Oct 2010 10:31:10 -0400
Rick Collins gnuarm.2...@arius.com wrote:
Personally, I can't imagine a PCB larger than 2 meters much less 4
meters. Or is the possibility of uses other than PCB design being
considered here?
FYI --
On Oct 8, 2010, at 12:42 PM, Andrew Miner wrote:
For flexible PCBs which are made on roll to roll machinery,
Good point, I forgot that a few months ago I saw some of these at a show. The
vendor said you could do printed circuits 8 inches wide by arbitrarily long.
Nice flex boards, too.
On Oct 8, 2010, at 10:27 AM, Dave N6NZ wrote:
I couldn't say what the standard panel sizes are in the industry, but I could
make an effort to find out.
FWIW,
A quick poll of my friends indicates that 18x24 inches seems to be a standard
panel size, but 48 x 22 inch boards used
On Oct 7, 2010, at 7:50 AM, Stefan Salewski wrote:
On Thu, 2010-10-07 at 22:29 +0800, Steven Michalske wrote:
I cannot get rid of the jagged diagonal lines on my design. There's lots
of them. The picture shows a couple of examples. I've tried different
grid sizes, line widths, but
I think a lot of people confuse the difference between a theoretical physicist
and an experimental physicist.
A theoretical uses a whiteboard and marker. He/She writes a paper.
An experimental physicist reads the paper and goes -- Oh, really?. He/She
constructs experimental apparatus using
On Oct 6, 2010, at 1:01 PM, DJ Delorie wrote:
You don't need to deliver *any* source code unless it is requested
by the user.
In the case of an embedded product, with GPLv3, the *only* way to not
include the source is to include the written offer, which opens you up
for a DDNS. You can
On Oct 6, 2010, at 3:20 PM, Geoff Swan wrote:
So just to clarify - if you distribute an embedded device that runs a
GPLv3 binary; to comply with the GPLv3 you must not only provide the
source, but also a hardware-programmer/uploader?
I suppose in most cases this isn't necessarily a huge
Yeah. I can't imagine a modern photo plotter having trouble with it.
In CNC code, doing a circle cut in arc segments is considered 'good practice'
by some, since a machine controller will only pause between lines of G-code. If
a circle is done as quadrants, then if something goes wacky you
On Aug 31, 2010, at 10:32 AM, DJ Delorie wrote:
That all depends on what the software says the difference is. I can
see those being very different things. One is an arc that is less
than half a circle and the other an arc that is more than half a
circle. But if the software
On Aug 14, 2010, at 2:16 PM, John Doty wrote:
The only real problem with Fink is that it gets itself tied in knots
occasionally. Every couple of years, I have to rm -rf /sw and reinstall the
whole thing.
The only *other* problem with Fink is that is doesn't always play well with
On Aug 12, 2010, at 7:17 AM, John Griessen wrote:
certain 3D entities are *not* documented,
they are binary blobs and you can only get the spec by paying for a license
from Autocad and signing an NDA. So no open source
dxf library will ever be able to handle all of dxf. My immediate
On Aug 13, 2010, at 12:51 PM, Felipe De la Puente Christen wrote:
On Fri, 2010-08-13 at 11:21 -0700, Dave N6NZ wrote:
I've been watching FOSS 3D CAD for a while, and until FreeCAD came along the
outlook was pretty depressing. The FreeCAD guys, however, are making
progress a bullet
On Aug 11, 2010, at 12:28 PM, John Griessen wrote;
What's a good reference about DXF?
Arghhh... I've spent a bit of time trying to read .dxf correctly. My first
shot was for reading .dxf to drive a simple laser cutter that used bastardized
HP/GL. I did an ad hoc parser in C after reading
On Jul 21, 2010, at 1:03 PM, Richard Rasker wrote:
Hello,
I'm a happy GSchem + PCB user for quite a few years now, but I'm still
puzzled about one aspect of defining symbols and footprints, and that is
special pins and pads. With special I mean the following types of
pins/pads:
-
On Jul 21, 2010, at 1:35 PM, DJ Delorie wrote:
- So-called don't care pins and pads, e.g. mounting pads for SMD
connectors.
I name them M1 through M4 for example, and if you want to connect
them to something, yeah, they need to be in the netlist. I'm not sure
if DRC ignores them if
On Jul 16, 2010, at 7:17 AM, Armin Faltl wrote:
Dave N6NZ wrote:
But my application is a little different. I want to get a DXF file that I
can run through a CAM package, in particular the paste layer, which isn't a
'real' layer, unfortunately -- it is synthesized in the output HID as I
there is one. Yet, a license that says only that you must
publish design data in publicly documented file format would allow such a
design. That is my point.
On Thu, Jul 15, 2010 at 2:06 PM, Dave N6NZ n...@arrl.net wrote:
On Jul 14, 2010, at 9:47 PM, timecop wrote:
Example: FPGA's. Verilog
On Jul 15, 2010, at 7:47 AM, asom...@gmail.com wrote:
On Wed, Jul 14, 2010 at 10:32 PM, Dave N6NZ n...@arrl.net wrote:
On Jul 14, 2010, at 7:46 PM, Windell H. Oskay wrote:
On Jul 14, 2010, at 7:36 PM, Ales Hvezda wrote:
And my usual questions:
http://lwn.net/Articles/396011
On Jul 15, 2010, at 12:40 PM, Mark Rages wrote:
Hi all,
Having reached the limits of pcb's feeble editor, I want to take some
traces on a pcb through a pcb-???-dxf-qcad-dxf-dxftopcb-pcb
cycle.
I had already written the dxftopcb tool.
(http://vivara.net/software/dxftopcb) when I
On Jul 14, 2010, at 7:46 PM, Windell H. Oskay wrote:
On Jul 14, 2010, at 7:36 PM, Ales Hvezda wrote:
And my usual questions:
http://lwn.net/Articles/396011/
I've had some part in this. Whether or not proprietary design files can be
compatible with open source hardware has been an
On Jul 14, 2010, at 9:47 PM, timecop wrote:
Example: FPGA's. Verilog source isn't going to help if the FPGA fitter tool
proprietary
OK.
Please name a vendor for FPGA hardware + toolchain that fits into this
absolutely ridiculous requirement.
I don't understand your question. Can you
On Apr 14, 2010, at 10:18 AM, Kai-Martin Knaak wrote:
3) There is consensus, that the current library is in poor shape. But
there are diverging opinions how a good default library should look like.
And I doubt there will ever be a one size fits all library. The flexibility
of the
On Apr 8, 2010, at 3:31 AM, Kai-Martin Knaak wrote:
On Wed, 07 Apr 2010 11:21:53 -0700, Dave N6NZ wrote:
No amount of googling brought up a simple syntax example like that.
I added a note in the wiki.
Great! The on-line guile documentation that I found via google was pretty hard
for me
So as I understand the current situation in gschem/gnetlist, there is no way to
get a global net in a hierarchical design other than to set:
(hierarchy-netattrib-mangle disabled)
in gnetlistrc. However, now all net attributes will become global nets. So,
if one uses off-page connector
On Apr 8, 2010, at 2:28 PM, Dave N6NZ wrote:
So as I understand the current situation in gschem/gnetlist, there is no way
to get a global net in a hierarchical design other than to set:
(hierarchy-netattrib-mangle disabled)
in gnetlistrc. However, now all net attributes will become
On Apr 7, 2010, at 5:38 AM, Peter Clifton wrote:
On Wed, 2010-04-07 at 14:23 +0800, Atommann wrote:
Hi,
2010/4/7 Dave N6NZ n...@arrl.net:
This may be an X-windows-on-Mac question, not a gEDA question, but...
When gschem or pcb open on my macbook, the window is too tall, and the
resize
On Apr 7, 2010, at 9:25 AM, Stefan Salewski wrote:
On Wed, 2010-04-07 at 13:43 +0900, timecop wrote:
I would never trust pre-made symbols for any project, it takes very
Similar for me, and I do not trust my own symbols also!
True enough. The only time I have been badly burned is when
Suppose I want to build a path like: $HOME/path/gedasymbols to pick up
component libraries, without unrolling $HOME into a hard path in a (define..)
-- how do I get guile to pick up the value of $HOME from the shell, and then
get it pasted into the rest of the stuff?
I'm aiming for:
(define
On Apr 7, 2010, at 11:05 AM, John Doty wrote:
On Apr 7, 2010, at 11:49 AM, Dave N6NZ wrote:
Suppose I want to build a path like: $HOME/path/gedasymbols to pick up
component libraries, without unrolling $HOME into a hard path in a
(define..) -- how do I get guile to pick up the value
I've created some symbols with non-zero width outlines using line elements of
width 40.
edit-translate(0) seems to get confused, and offsets the symbol so the pins
don't line up on 100 unit grid.
edit-translate with independent x,y values seems to by broken.
How can I fix this, short of
On Apr 6, 2010, at 10:52 AM, Mark Rages wrote:
On Tue, Apr 6, 2010 at 12:27 PM, Anthony Shanks yamazak...@gmail.com wrote:
Didn't bother with any kind of scripted footprint generator as I
wanted to know exactly what the file format was for footprints. Once I
discovered how easy it was I felt
On Apr 6, 2010, at 4:21 PM, Levente Kovacs wrote:
On Tue, 6 Apr 2010 09:41:37 -0700
Anthony Shanks yamazakir2-re5jqeeqqe8avxtiumw...@public.gmane.org wrote:
In my opinion it's worth spending an hour going over the footprint
file format and just making your footprints in an ASCII editor.
This may be an X-windows-on-Mac question, not a gEDA question, but...
When gschem or pcb open on my macbook, the window is too tall, and the resize
grabber is off the screen on the bottom and I can't reach it to resize the
window. Normally, not an issue since I immediately move the window over
On Apr 5, 2010, at 3:22 PM, kai-martin knaak wrote:
Dave N6NZ wrote:
I'm getting started on an open-hardware project using gEDA, and did a
couple of gEDA logo items.
1. logo'ed title block symbol. This is pretty much a clone of the
standard title-B symbol, with these tweaks
I'm getting started on an open-hardware project using gEDA, and did a couple of
gEDA logo items.
1. logo'ed title block symbol. This is pretty much a clone of the standard
title-B symbol, with these tweaks in the title block:
* sub-block for copyright
* sub-block for license (reference, not
Normally when I construct a symbol for a microcontroller or such part where the
I/O pins can have multiple functions, I like to include the alternate functions
in the pin label, like this example from an Atmel part:
pinlabel=PE2 (XTAL2/ADC0/PCINT26)
But... I've run into a part where the list
On Mar 31, 2010, at 9:06 AM, John Griessen wrote:
Peter Clifton wrote:
On Tue, 2010-03-30 at 15:41 -0700, Dave N6NZ wrote:
I want to follow the git -- but for now on the release branch (if there is
one??) not the dev head.
Use the stable-1.6 branch in that case. Individual releases
I am trying to get gschem to come up with my personal title block. Seems like
it should be easy. But...
Here is an rc file in the project directory:
(component-library /Users/dave/gitrepos/gedalib/tbsymbol2)
(define default-titleblock tbtitle-B)
If that file is named gafrc, the 'define
Hi,
I'm about to attempt building gEDA/gaf on a Mac. My plan is to use the git
repo. Two questions:
1. Is there a branch or tag or such for the latest release? I'd like to
track that and not follow the development head for now.
2. Any special Mac build tricks I should know about? I use
On Mar 30, 2010, at 3:05 PM, Steven Michalske wrote:
On Mar 30, 2010, at 2:49 PM, Dave N6NZ wrote:
Hi,
I'm about to attempt building gEDA/gaf on a Mac. My plan is to use the git
repo. Two questions:
1. Is there a branch or tag or such for the latest release? I'd like to
track
On Mar 30, 2010, at 3:53 PM, Peter Clifton wrote:
On Tue, 2010-03-30 at 15:41 -0700, Dave N6NZ wrote:
I want to follow the git -- but for now on the release branch (if there is
one??) not the dev head.
Use the stable-1.6 branch in that case. Individual releases are tagged
as well.
Very
On Mar 10, 2010, at 4:24 AM, Peter Clifton wrote:
Questions though..
What to do with a manually defined paste layer if the user fiddles with
the size of the copper pad / solder mask? (Assuming that eventually
becomes more flexible to edit).
? I don't think I understand the question. Are
Well, for one thing, dxflib is rock solid, and pstoedit was broken in many ways
the last time I tried to use it.
-dave
On Mar 9, 2010, at 2:48 PM, Windell H. Oskay wrote:
Doesn't pstoedit already do this, too?
http://www.pstoedit.net/
Are there advantages to these custom versions?
On Mar 9, 2010, at 3:33 PM, Peter Clifton wrote:
On Tue, 2010-03-09 at 18:27 -0500, Dan McMahill wrote:
pstoedit converts postscript to various formats. So I suppose you could
try pcb export to postscript and then pstoedit to produce dxf. That
said, there are always issues with file
On Mar 9, 2010, at 4:01 PM, DJ Delorie wrote:
is that true? Is it simply generated on the fly off the pad
information during gerber export?
That's true.
Just in case anyone is confused by the tight snippage: It is true that there is
no real paste layer, it is generated on the fly off
If this is your first board, I'd go with a shop that is reasonably fast and
known for quality work.
Fast because:
* this is your first board, and you are excited to have it.
* this is your first board, and now is the time to make mistakes quickly.
Quality work because:
* this is your first
On Feb 27, 2010, at 8:51 AM, John Luciani wrote:
John hasn't had time to finish :(
So John, post a to-do list and your check-in check-list. If several of us
volunteer to do a symbol or three we should be able to push it over the hump by
a reasonable deadline Symbols by the Solstice
On Feb 27, 2010, at 12:44 PM, Peter Clifton wrote:
Someone with a Mac might like to try building gEDA and PCB with a native
version of GTK?
OK, I'll play dumb. I recently built PCB from git after naively using macports
to make all the dependancies go away. How is that different from what I
On Feb 28, 2010, at 9:35 AM, Charles Lepple wrote:
On Sun, Feb 28, 2010 at 11:24 AM, Dave N6NZ n...@arrl.net wrote:
On Feb 27, 2010, at 12:44 PM, Peter Clifton wrote:
Someone with a Mac might like to try building gEDA and PCB with a native
version of GTK?
OK, I'll play dumb. I recently
On Feb 24, 2010, at 6:09 PM, Girvin R. Herr wrote:
Kai-Martin Knaak wrote:
I just got aware of the open source mechanical CAD project freecad. It hit
the debian repository a month ago. Although it is still lacking important
features, much of the basic infrastructure is already up and
On Feb 25, 2010, at 10:45 AM, DJ Delorie wrote:
Everything in pcb supports non-90 arcs, except for the ability to
create them. Someone needs to come up with a friendly way to
create/edit arcs that aren't 90 degrees, that's all.
FWIW QCad has 3 pimary arc creation modes:
1. click1 sets
On Feb 25, 2010, at 4:01 PM, Vanessa Ezekowitz wrote:
On Thu, 25 Feb 2010 14:57:20 -0800
Dave N6NZ n...@arrl.net wrote:
On Feb 25, 2010, at 10:45 AM, DJ Delorie wrote:
Everything in pcb supports non-90 arcs, except for the ability to
create them. Someone needs to come up
Hi,
Is there any automated Eagle to gEDA conversion path?
(He says hopefully, but knowing it's highly unlikely.)
-dave
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On Feb 22, 2010, at 9:08 PM, timecop wrote:
Diptrace has a pair of ulp scripts to convert eagle project to ascii
schematic and pcb.
OK, although I don't know what either Diptrace or ulp are. Sounds like a good
place to start, though.
I'm wondering how the library issue would be handled.
.
That makes a lot of sense, even when the file format *is* well documented. The
question is then, how much munging does it take to transmute diptrace ascii
exchange format into gEDA stuff.
-dave
On Tue, Feb 23, 2010 at 2:53 PM, Dave N6NZ n...@arrl.net wrote:
On Feb 22, 2010, at 9:08 PM, timecop
On Feb 21, 2010, at 2:01 PM, Mark Rages wrote:
On Sun, Feb 21, 2010 at 1:55 PM, Anthony Shanks yamazak...@gmail.com wrote:
Some parts have mounting brackets that are square, not round. Yes I
know I can make a equivalent circlular hole that would fit but it
wastes a lot of space doing that
On Feb 16, 2010, at 7:37 AM, Chris Maness wrote:
Would I just download the source myself and compile?
Thanks,
Chris
I recently built pcb from the git repo without issues on 10.6.2. There were a
number of dependencies that I had to resolve first -- IIRC they were all
On Feb 3, 2010, at 12:33 AM, timecop wrote:
At the very least, it seems that there should be a way to specify that any
pin with the same number satisfies the connection.
fairly ridiculous assumption especially with ICs, many of which
specifically say something like all GND/VCC pads must
On Feb 3, 2010, at 7:53 AM, Vanessa Ezekowitz wrote:
On Wed, 03 Feb 2010 06:47:19 -0500
Ethan Swint eswint.r...@verizon.net wrote:
On 02/03/2010 03:33 AM, timecop wrote:
At the very least, it seems that there should be a way to specify that
any pin with the same number satisfies the
On Feb 3, 2010, at 9:59 AM, Peter Clifton wrote:
The danger comes if you don't populate the switch. This then causes
break in the board connectivity.
True enough. But population options are an orthogonal conceptual axis. Not
populating the microcontroller causes a loss of functionality,
I've got a pcb where close tracks through polygons are leaving thin shards of
copper between tracks. These are 8 mil tracks on a 10 mil grid. Seems to me
these have always been cleared out in the past because they are below minimum
copper size, but then again, I usually close space my tracks
On Feb 3, 2010, at 7:51 PM, Dave N6NZ wrote:
I've got a pcb where close tracks through polygons are leaving thin shards of
copper between tracks. These are 8 mil tracks on a 10 mil grid. Seems to me
these have always been cleared out in the past because they are below minimum
copper
I find it best(*) in the long run to crank out my own symbols. For things like
the PIC, I use a modified version of DJ's djboxsym. I also have a couple of
little generator scripts for other parts.
-dave
* By best, I mean best way to get symbols that match my personal taste.
On Feb 2,
On Feb 1, 2010, at 8:42 AM, Luke wrote:
My questions are:
1) What is needed to associate a symbol to a footprint when you
drawing the schematic in gschem? Is it a filename?
set footprint attribute to the name of the file foo.fp
If so, where does
that file need to be located?
I set
On Jan 30, 2010, at 9:21 PM, Kai-Martin Knaak wrote:
On Sun, 31 Jan 2010 01:10:28 +, Phil Frost wrote:
Is there some way to instruct PCB to put a copper pad for through-hole
pins only on the bottom of the board?
No.
This is an aspect of the long standing feature request user
On Jan 30, 2010, at 4:00 PM, Ben Jackson wrote:
I need to make a key matrix. I'm considering selecting a switch which
has 4 leads (two leads per internal net):
o--+--o
'
/
|
o--+--o
This appears to be a boon for the grid-style routing I need for the
switch matrix.
On Jan 28, 2010, at 12:46 PM, DJ Delorie wrote:
I've done some hacks that
look for layers named cmask or paste and just appends those to the
gerbers, but nothing that can be committed.
For those of us less familiar with the code, what is the internal design of pcb
that forces you to do
On Jan 28, 2010, at 4:20 PM, DJ Delorie wrote:
One of the LF tasks
LF?
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On Jan 26, 2010, at 11:25 PM, Bert Timmerman wrote:
FWIW, There lives a dxf exporter for pcb in a not yet finished state at:
http://github.com/bert/pcb-dxf-hid
Thanks, I wasn't aware of that.
-dave
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On Jan 24, 2010, at 3:40 PM, d...@umich.edu wrote:
snip
Dave,
I have been following the RepRap project with interest. A 3D printer that
anyone can make is a very cool scratch to itch. I am fascinated by the
artwork of the sculpter, Bathsheba Grossman. She really shows what is
On Jan 24, 2010, at 9:15 AM, John Doty wrote:
CO2 is way out in the IR. I guess the way to use it is to vaporize the
resist. Note that black in the visible may not be black at the IR wavelength
in question, and vice-versa
Good point... I should have remembered that because I was part
On Jan 23, 2010, at 12:10 PM, Bob Paddock wrote:
snip
Management saw
this: http://www.epiloglaser.com/ at CES and is thinking of spending
money (a rare event)
on one of them. There actually is a lot of industrial related stuff
at the consumer show.
I've used modern Epilog machines, and
On Jan 23, 2010, at 3:51 PM, Windell H. Oskay wrote:
We have an Epilog. Low-power lasers of this type cannot cut (or even etch)
copper foil, nor can they cut FR4.
You can potentially use it to blast away an etch-resist layer, however; I've
seen several examples of this.
Here is one:
On Jan 20, 2010, at 11:52 PM, Ben Jackson wrote:
The polygon code is fully generic. It can do what you describe (in fact,
it does, it just probably doesn't output in the format you want).
Hmmm well, point me at the code, and I'll have a look at seeing
what it would take to sew in
On Jan 21, 2010, at 12:28 PM, Peter Clifton wrote:
snip
I believe gerbv is the right place for dxf export, since that creates
a tool that works with any gerber file from any tool. The overall
tool flow is more logical that way.
Keep it modular enough, and it could live in PCB as well..
be a good idea. If the starting point is a .ps file,
then both programs could use the same backend.
The postscript file is a kludgy intermediate step that needs to be eradicated
in the 'clean' solution.
-dave n6nz
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On Jan 20, 2010, at 1:01 PM, Ben Jackson wrote:
On Tue, Jan 19, 2010 at 11:56:25PM -0500, d...@umich.edu wrote:
I just created a thread on cnczone.com, which I want to bring to your
attention. I titled it, Schematic Capture to dxf File - using gEDA,
Inkscape, and pstoedit:
I have been
On Jan 20, 2010, at 10:14 PM, Ben Jackson wrote:
On Wed, Jan 20, 2010 at 09:20:34PM -0800, Dave N6NZ wrote:
On Jan 20, 2010, at 1:01 PM, Ben Jackson wrote:
I have been thinking about how to do improved isolation routing.
How do you differentiate between pads that must be a certain shape
Hmmm... interesting. I gave your post a quick skim, and will have to go back
to read it in detail when I have more time.
A while back I created a flow to convert the paste layer to laser cutter code
for the creation of solder paste stencils. My path was:
1. print .ps from pcb
2. pstoedit to
On Jan 8, 2010, at 8:57 AM, John Eaton wrote:
Pinlabel is for humans, and for hierarchy. Pinseq is a unique
numerical identifier for the pin, independent of the footprint if
any (not all symbols correspond to parts with footprints).
So slotting lets the PCB designer exchange one 2
On Jan 5, 2010, at 9:31 AM, DJ Delorie wrote:
Can't wait to have that one implemented as it's the one point i
tripped over with about every software i tried.
Just to be clear - by writing down my ideas, I do not mean to imply
that I (or anyone else) will actually implement them.
But
On Dec 28, 2009, at 9:21 AM, Dave McGuire wrote:
Such repairs would be pretty much impossible without the full
component- and gate-level schematics I have for these machines, of
which this is an example of one page:
http://www.neurotica.com/misc/kb11c-117.png
You misunderstand
On Dec 27, 2009, at 9:16 AM, DJ Delorie wrote:
On the pin mapping subject I miss an example of the power pins of a
rail-to-rail opamp, just to nail these troublemakers down as well (sometimes
I get Vss hitched to ground instead of the negative voltage rail).
Power pins are not special in
On Dec 27, 2009, at 2:08 PM, DJ Delorie wrote:
User now needs to somehow specify that U01 GND is connected to
analog ground, U01 V+ and V- to analog power rails. U01 GND, U02
GND, U03 GND and U04 GND are connected to digital ground. U02 VCC is
connected to 5V, U03 VCC3v3 is connected to
On Dec 27, 2009, at 6:00 PM, DJ Delorie wrote:
Actually this is starting to sound like embedding a gattrib grid
on a sheet some place.
Can gattrib map pins to nets already?
Well, not that I know of. But having a grid display of row-organized data that
captures interesting stuff
On Dec 27, 2009, at 6:12 PM, gene glick wrote:
DJ Delorie wrote:
I'm not exactly sure what's best here, but I know it doesn't belong in
the *gate*. My idea is to have a table object that shows up in the
schematic, like in a corner or something, that lists all the power
pins and what
On Dec 27, 2009, at 8:22 PM, Dave N6NZ wrote:
On Dec 27, 2009, at 6:00 PM, DJ Delorie wrote:
Actually this is starting to sound like embedding a gattrib grid
on a sheet some place.
Can gattrib map pins to nets already?
Well, not that I know of. But having a grid display
On component databases:
Not sure that I have a lot to add, except that when I read it I was looking
specifically for the proposed database hookup and found the right answer :) I
already have a SQL database for parts, so I'd like to be able to write a quick
lib.so in C that hooks up to gschem
On Dec 22, 2009, at 2:08 PM, phil wrote:
I'm trying to find a shop that will make 29 long boards. They are
simple 1/16 two layer boards and will have card edge connectors.
Is there a known vendor for this type of work
I suspect any of them can do any board that fits in a panel, and the
Link wrote:
I've designed a circuit that I'm planning to home-fab, and as such, I've
had to design my board using only a single layer. After about a week or
so of puzzling, I've managed to route it. Unfortunately, it looks like
I'll need a metric craptonne of jumper wire, and I was hoping
Bill Gatliff wrote:
Now I'm beginning to see the problems with slotting and symbols the way
we're doing them now: they unnecessarily tie the concept of a symbol to
the concept of a component, because the pin numbers that we currently
record in our symbols are also the pin numbers that the
My approach would be to use a NAND symbol, a power symbol, and slotting.
I'm curious as to why you found slotting problematic? It's no more or
less obtuse than the rest of gschem.
-dave
Bill Gatliff wrote:
Guys:
I can get TI's LittleLogic NAND gates in single (SN74LVC1G00) and dual
Peter Clifton wrote:
On Thu, 2009-11-12 at 16:36 +, Kelvin Gardiner wrote:
Hi,
I'm trying to create some new AVR symbols. Can the footprint section of
a symbol file have more than one footprint listed. If so how is each
footprint separated, a tab or comma?
snip
You could make the
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