On 09/18/2011 07:56 PM, Vanessa Ezekowitz wrote:
DJ's clarification aside, I would vote for top/bottom, with each of those
symbolically being placed in the list. That is, for an 8-layer default: Top, Layer 2,
Layer 3, ..., Layer 7, Bottom
+1
JG
On 09/18/2011 10:04 PM, Andrew Poelstra wrote:
Well, C itself doesn't seem to be used too much outside of 10 year
old code. Nowadays the language du jour seems to be Python, and C is
only used for library-type projects that want many language bindings.
IMHO everything should be Lisp.;)
:-)
JG
On 09/18/2011 08:16 PM, DJ Delorie wrote:
You're +1'ing something we already have,
Whoops.
On 09/18/2011 08:16 PM, DJ Delorie wrote:
So... go get the release and test it
OK. There's another unfinished/overdue project on my to do list...
I will attempt to swap sleep/insomnia for executing
On 09/18/2011 09:01 PM, Kai-Martin Knaak wrote:
This patch replaces component and solder in the leftmost item of the
status line of the GTK HID with top and bottom.
Thanks for work to improve the GUI Kai-Martin.
JG
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On 09/10/2011 11:33 PM, Abhijit Kshirsagar wrote:
i find that the documentation for creating
hierarchical designs (schematics encapsulated inside a gschem symbol)
is rather scattered so I'm going to start off with that first. If
anyone has already written this please let me know!
I have some
On 09/10/2011 10:35 AM, Jared Casper wrote:
A reason
for the success of the toys is that documentations seems to be not
needed.
I agree with the idea, but the thing is, the Apple software that
doesn't need documentation doesn't do a whole lot.
Yes, and the hobby CAD users want it to be
On 09/10/2011 06:20 PM, Jared Casper wrote:
gEDA is as far away from Fritzing as Word is from NotePad.
Jared
But they both have many of the same low level primitive commands and actions.
I think you could base two apps on the same code and many of the users would
never know,
since some are
On 09/08/2011 04:14 PM, Kai-Martin Knaak wrote:
My solution: A titleblock symbol that is really just that. A box, which
contains the title, date, version and author, to be printed on the bottom
of a page. Because these are global attributes, they can be edited wholesale
with the attribute
On 09/08/2011 04:32 PM, Peter Clifton wrote:
Notice there are plenty of single-key bindings there already, for
example, the group at the bottom.
Hope that helps,
Yes, thanks. Maybe I'll create a tutorial based on a keybinding layout
that works smoothly with PCB and see if it is popular.
On 09/08/2011 06:58 PM, Kai-Martin Knaak wrote:
There are a few more that could potentially be matched:
gschempcb
* start drawing a net [n] start drawing a track [F2]
* edit some text [ex] edit some text [n]
.
.
.
On 09/08/2011 07:01 PM, Kai-Martin Knaak wrote:
The number of people using it one way or the other would be voted for
with tutorials written and promoted.
... and create quite some confusion during the process. Does not look
like a good idea to me.
OK, then how about we write it up in your
and paste buffers needs to be invisible by default and otional with
a workaround that
does not require knowing they exist.
After these low level stoppers, we should find textbooks to study on GUI
design, compare those
to Orcad twenty years ago, and copy what is not patented.
John Griessen
On 09/08/2011 10:03 AM, Attila Kinali wrote:
Yes, i know that the workflow is tool dependent, but there are many
tools out there that follow a more or less similar workflow and i think
gEDA should match that as well.
If there is a good reason to deviate from that common workflow, it should
be
are still some things in the docs which could use some
elaboration for new users, beside returning users like myself -
[jg]I think DJs docs are fabulous too.
John Griessen
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On 09/08/2011 11:28 AM, asom...@gmail.com wrote:
I find the two-letter commands to be very fast to use.
They're one of the main reasons why I prefer gschem to the expensive
proprietary program I used at my last job. But maybe that's just
because I'm a vi user.;)
I think the double strokes
On 09/08/2011 01:01 PM, Karl Hammar wrote:
Don't ever assume that a non native engligh speaker will understand
thoose words or view them as anything else than some random characters
lumped together.
Another reason gschem would benefit from no-recompile-required key binding
configurability
On 09/07/2011 09:48 AM, Peter Clifton wrote:
I had wondered if part of the reasoning might be that KiCad feels a lot
more local to them. (KiCad being a French originated project - CERN
being on the French / Swiss border.)
That is one thing. Also they stated their wants as integrated printed
On 09/06/2011 05:20 PM, Kai-Martin Knaak wrote:
We had a meeting at CERN on Friday and decided we would start
contributing to the Kicad project in view of taking it to a level of
quality and features suitable for our PCB design activities.
They had said that at the start, really. No surprise.
Original Message Subject: Re: [OH Updates] Degrees of
open-ness in EDA (and CAD in general) Date: Sat, 3 Sep
2011 18:58:40 -0400 From: phillip torrone p...@oreilly.com To: updates
upda...@lists.openhardwaresummit.org
john,
can you write up what's needed for gEDA in a couple
On 09/05/2011 09:33 AM, Kai-Martin Knaak wrote:
Also, they tend to bit-rot and break
when the main source moves on.
That's why they are separate. There is not enough
coding/testing man-or-woman-power to pull all conceivable plugins along
with core changes. Seems obvious. The ones that are
On 09/05/2011 11:55 AM, DJ Delorie wrote:
See gpleda.org for information on mailing lists
changed that.
JG
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On 09/05/2011 12:29 PM, DJ Delorie wrote:
I think it would help a lot if the scheme or c code underlying
functions showed in the log window in a way that can be cut and
pasted to execute it again, or create a script that can be run with
a button.
pcb --verbose does that, but there's still
On 09/05/2011 01:21 PM, DJ Delorie wrote:
Cursor movements have their own channel, so just re-running
all the actions you see won't duplicate what actually happened. For
example:
Action: PointCursor()
Action: Mode(Notify)
Action: PointCursor()
Action: PointCursor()
Action: PointCursor()
in
feel free to send it to the list here and i'll grab it from here assuming no
one has an additions to it.
cheers,
pt
On Sep 3, 2011, at 6:54 PM, John Griessen wrote:
On 09/03/2011 03:50 PM, Pierce Nichols wrote:
Taking those over to KiCAD or geda by
hand would be a big time hit... time
On 09/04/2011 08:10 AM, John Griessen wrote:
I could use some help with this write up!
I'll write something up and ask for reviews soon.
John
Original Message
Subject: Re: [OH Updates] Degrees of open-ness in EDA (and CAD in general)
Date: Sat, 3 Sep 2011 18:58:40 -0400
From
Does the category low end bother you?
Original Message
Subject: Re: [OH Updates] How can you help solve the proprietary tool problem?
Date: Fri, 2 Sep 2011 09:12:20 +1000
From: Dave Jones d...@eevblog.com
CC: upda...@lists.openhardwaresummit.org
I'm planning a review of the
On 08/31/2011 04:57 PM, Thomas Oldbury wrote:
The 3.3V bus is used all over the board. How can I locate specifically
which part is shorted?
Divide and conquer...delete some trace segments or reroute 2 pieces where one
long one is
and see what changes...
It must be something I placed
Just read these and very clarifying.
http://perens.com/works/testimony/PerensJMRI.pdf
http://itmanagement.earthweb.com/osrc/article.php/3775446/Bruce-Perens-A-Big-Change-for-Open-Source.htm
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On 08/30/2011 04:14 PM, Russell Dill wrote:
I imagine I'm not the only one running a git mirror of
gedasymbols.org. If you rely on gedasymbols.org in any way, It'd be
wise to do the same.
Oh, it's getting handled by DJ doing a secondary DNS server setup
eventually.
Then the web server mirror
On 08/29/2011 06:23 PM, DJ Delorie wrote:
It's back, but there's supposed to be a backup server on the west coast...
There is, but there's no backup DNS server, so I'm not sure you can ping
it when the main server goes down.
John
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On 08/22/2011 11:29 AM, Kai-Martin Knaak wrote:
The commercial package he wants to keep up with seems to be altium designer.
Oh, I guess that's why I referred his request to others. I like the
radical flexibility of gEDA tools without getting evangelical about it,
and KiCAD is closer to
I'm swamped.
CERN might come up with tip money for developers.
Anyone have the time to be in a committee?
John Griessen
Original Message
Subject: [Fwd: Proposed plan]
Date: Mon, 22 Aug 2011 01:24:46 +0200
From: Javier Serrano javier.serr...@cern.ch
To: John Griessen j
On 08/13/2011 06:10 PM, Kai-Martin Knaak wrote:
Who are the people, who are in the position to do so?
What effort is needed?
Not me. I'm hoping to do some work on gnetlist scheme programming
to get verilogAMS netlists to connect well with gnucap, but have to
spend time doing housing
On 08/10/2011 06:04 PM, Andrew Poelstra wrote:
Please test this and let me know what needs to be done. Thanks!
Thanks Andrew. busy til Wednesday, then will try it out.
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On 08/08/11 06:21, Chris Smith wrote:
I'm guessing that composite will be easier to work with?
Depends on the video sender products you find. If there's one for analog,
that's problem solved. Do you have plenty of power at both ends?
Google shows that there are plenty of video sender
On 08/07/11 21:47, Rob Spanton wrote:
https://xgoat.com/wp/2011/08/08/playing-with-footprints-and-constraints/
The tool is by no means complete... it's the result of just a few hours
work right now.
Thanks for sharing that, looks like python style of
sub-function.sub-function.function()
On 08/05/11 14:35, yamazakir2 wrote:
Do you guys use your linux box for general desktop usage or only EDA?
Both. Email is via Mozilla thunderbird, which seems to handle cross platform
things well. I still don't have a player for .wmv video working though.
Using Firefox with the latest
On 08/06/11 08:54, Павел Таранов wrote:
3. Trac plugin introduced. See demo http://demo.wedana.org/night_builds/trac
4. We have own domain now: http://www.wedana.org launched. Also
http://demo.wedana.org available.
Looks good. I could not figure how to use the origin input to
get a symbol
On 08/06/11 14:24, Павел Таранов wrote:
When I entered a pos number, the symbol view is off screen. neg number had
no effect...
Position (inc): 0:0
Seems it is not obvious, but after you change value in position, press
Draw button.
The result when I do that is the symbol moves to
On 08/04/11 13:08, Markus wrote:
What desktop are you using for gEDA?
Xfce on debian unstable
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He says, We do quite
complex PCB design, and for us it's important to have high-performance
quality tools. One option is to try to get some community effort behind
Kicad (or another FOSS tool) and bring it on par with some of the
non-open tools
Also said, Does the router feature push shove?
On 07/26/2011 01:14 PM, Larry Doolittle wrote:
Maybe someone (John?) would
like to go over my material ahead of time?
Yes, I'll read and understand it and then we could talk on the phone...
John
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backends for verilog.
John Griessen
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On 06/24/2011 06:10 AM, myken wrote:
I think that has something to do with the fact we used a pulse
transformer to try the circuit.
Looks like a diode drop to me, not transformer problems.
You've got a series chain of reactances. You're gonna get oscillations
and lagging, leading voltage
On 06/16/2011 01:30 PM, myken wrote:
see Rectifier_sim.jpeg)
Everything works fine if LOAD_1 and LOAD_2 are equal.
Lose C1. Lose R1. Add L2 feeding D1.
Separate D1 D2.
Add some rc filter R between
D2, C2. Or try moving L1 between D2, C2
John
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On 06/08/2011 11:08 PM, Rob Butts wrote:
I forgot to mention the power sources are DC and the power connectors
need to have at least 6 amp rating.
http://www.mouser.com/catalog/629/1099.pdf 31 amps
and here are some ideas on ways to use these type of connectors for battery
boxes:
On 06/08/2011 11:08 PM, Rob Butts wrote:
the more water proof the better.
http://www.andersonpower.com/products/spec-pak-connectors.html
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On 06/07/2011 06:05 AM, Ethan Swint wrote:
I've got the line
(component-library-search /../../footprints)
in my gafrc file. Does that set a priority?
-Ethan
Not sure of the concept of priority, but I think yes. pcb probably uses the
first it finds
and that line will be the first searched.
On 06/06/2011 01:13 PM, Ethan Swint wrote:
OK- I've been messing around with hierarchy for the first time, but I'm a bit
lost. I've got an asymmetric phase leg inverter with
three phases,
Yes, that's a good use of the flattened hierarchy we can do for now.
My problem then comes when I try
On 06/01/2011 02:54 PM, Colin D Bennett wrote:
But how (and where) would such global rules be defined?
In the chip biz you write design rules that create connectivity based on
overlap,
or boolean intersection of areas being greater than a minimum number of units.
Those rules use features of
On 05/31/2011 04:26 PM, Thomas Oldbury wrote:
Double sided boards are great, but not so great when the product is
supposed to cost only $3/each, after an MSP430, mains power supply,
heatsink, triac etc.
You seem to have BOM'd out on that product...
On 05/31/2011 04:26 PM, Thomas Oldbury wrote:
Double sided boards are great, but not so great when the product is
supposed to cost only $3/each
What you really want is the high volume technique of using
carbon conductive ink traces and insulating layers silk screened on
and single copper
On 05/30/2011 01:50 AM, John Doty wrote:
But who's volunteering?
On 05/30/2011 01:50 AM, John Doty wrote:
So, one way or another, we're looking at a new tool, I think. Maybe we keep
the old gnetlist around and feed it modified/annotated schematics.
There will always be people who don't
On 05/30/2011 11:55 AM, DJ Delorie wrote:
One thought I had for gnetlist backends, is to recode gnetlist as a
set of libraries. The Core would only load the design files
(schematics, spreadsheets, databases, back-annotation info, etc) as
raw data; the backend would be required to call at least
On 05/28/2011 10:01 AM, Dave McGuire wrote:
This is my opinion, speaking as a professional developer of both hardware and
software: Scheme was a good choice for gEDA, and it
should be left alone. The chosen implementation of Scheme, guile, may not be
the best tool for the job right now, but
On 05/26/2011 07:40 PM, John Doty wrote:
If the consensus is that gnetlist is the place to perform the transformations
we're discussing, then we're in Scheme territory, I think.
I can't see abandoning guile/scheme. I've even written scripts
in Cadence skill language, which is pretty much
On 05/24/2011 04:02 PM, DJ Delorie wrote:
Mike Bushroembush...@gmail.com writes:
As for names, data pack
I like data pack.
But the seed idea is growing on me too.
Beats python eggs! They sound like a natural disaster in Florida...
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On 05/24/2011 07:22 AM, DJ Delorie wrote:
if it's layout-specific data, the copy in the layout is correct.
Perhaps we need to keep track of whether the data in the layout and
schematic originated in that file, or is the result of user changes
elsewhere being imported.
But any solution depends
On 05/23/2011 10:13 AM, Karl Hammar wrote:
changed component-library-search to descend
into subdirectories (see diff).
The result is as seen in attachment (dump.jpg).
Dang, that was quick Karl!
John
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On 05/23/2011 11:44 AM, Karl Hammar wrote:
comment on the functionality which the screen dump hints
you at?
Like it.
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On 05/22/2011 10:37 AM, Kai-Martin Knaak wrote:
Next try: packet
This can also contain all kinds of objects. It closely avoids the
clash with the meaning of package in data sheets.
Packet is a good one. If someone is confused they can be told library packet,
or see it is in library context.
On 05/21/2011 11:35 PM, Steven Michalske wrote:
So that wires that have the same meaning are still hooked up
but new pins are unconnected, or old pins that no longer exist are now
not connected.
The other wish list ideas sound like where we are headed, but this last is
probably beyond coder
On 05/22/2011 08:57 PM, John Doty wrote:
I've been working on this for six years, now, and it's wonderful to see it all
built and plugged together.
Congrats John.
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On 05/22/2011 11:40 PM, DJ Delorie wrote:
And if you gate-swap between packages, you then need to know which two
subcircuits get their gates swapped.
That might become an instance label like:
I1.1 for slot 1
I1.2 for slot 2
And since I don't use heirarchy, I can only assume it's even more
file name. Instead of SOIC-8.fp.meta we would use
SOIC-8.fp.I231.meta
which contains attribs symbolname=FET_dual_11234.sym
symbol-meta-data=FET_dual_11234.I002.sym.meta
footprintname=SOIC-8.fp.
John Griessen
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metadata to a footprint if you have a connection
between footprint
and metadata made by them being in a data dir container. Doesn't matter what
container.
John Griessen
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On 05/22/2011 12:33 AM, DJ Delorie wrote:
I like the idea of creating a library group containing all info related
to a manufactured part or part range.
Library group? Or just a library? (not picking on the name, just
wondering what you think the difference is, or why such a difference
might
or Physical_layer
which would require changing how outline is done -- like John Doty suggested.
As is, the terminology makes people that use gimp or photoshop or inkscape
think of image or drawing layers that can be arranged in any order.
John Griessen
On 05/13/2011 08:10 AM, Peter Clifton wrote:
Comments?
Sounds close to the approach of Fritzing, where wiring is documented
as literal wires put in a plug-board. Your concept is different only
in keeping the as built prototype as a reference -- no plug-board.
One step of getting the omitted
outline was defined by a layer
called outline
holding just a 10 mil wide trace, the center of which was the desired board
edge.)
tek_7k_flex.gcode.front.cnc contained 465 polygons, so it was different...
John Griessen
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On 04/11/2011 02:11 AM, Gabriel Paubert wrote:
consider layers with the same
Z coordinate as a layer group
OK, that could be used for stackup, and also farther along,
Z is a general axis designator, so would become Z position
in the stackup, so your group number attrib
should be some other
On 04/11/2011 08:08 AM, Andrew Seddon wrote:
I'm more interested in keeping the editing to domain specific tools
but allow viewing in general purpose packages.
Sounds good.
On 04/11/2011 08:18 AM, Andrew Seddon wrote:
I suppose my sole purpose for SVG right now is the warm fuzzy feeling
of
On 04/10/2011 03:55 PM, Andrew Seddon wrote:
I am exploring the idea of using the Scalable Vector Graphics standard
as an EDA format.
$ firefox symbol.svg
renders a familiar looking symbol on my debian linux machine.
So, are you thinking of making a translation in and out of gschem for all
On 04/10/2011 06:42 PM, DJ Delorie wrote:
would such a layout be a better default for you?
Fine by me.
JG
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On 04/10/2011 07:51 PM, Peter Clifton wrote:
Supporting complex geometry primitives which SVG would bring also means
internal processing in PCB might get more difficult.
And then the ones using external programs to create such data could do the
changes
to pcb to allow it to parse those
On 04/10/2011 08:26 PM, Bob Paddock wrote:
Sometimes the outer layers are called Primary and Secondary.
Main and Second are shorter and might convey similar meaning and be more
usable...
JG
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On 04/08/2011 03:43 PM, Karl Hammar wrote:
Like this?
# 3216 / 1206 as connecting footprint
Works perfectly fine (for the attached pcb file) till you press o:
Warning! Net unnamed_net1 is shorted to net unnamed_net3
Warning! Net unnamed_net1 is shorted to F1 pad c
Thanks Karl. That's
On 04/08/2011 11:44 AM, Russell Dill wrote:
I'm not sure if it could be done simpler, but for a special copper
trace that connects two planes, you would do DRC twice, one time
ignoring between the trace and plane A, and another between the trace
and plane B.
That is a method consistent with
On 04/07/2011 04:52 AM, Stephan Boettcher wrote:
PCB layer groups may be used here. Put the short on an extra layer, in
an extra group. At checkout time, you can assign the extra layer to the
group representing the copper layer that needs shorting. This is
probably a single char in the PCB
On 04/06/2011 05:16 PM, Russell Dill wrote:
The use case I'm talking about, you have two nets, say GND and AGND1
which are two planes that are connected at a single point. Connecting
a component on the AGND1 side is different that connecting a component
on the GND side.
Yes, Levente's way of
in +60
qty 180 $403. -?- .20/sq in +60
John Griessen
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-up materials, additive processes will
naturally demand insulator materials that go down as printed layers, just
as solder mask, copper, silk-screen do now. Once you go all the way to defining
presence of material as your basic model, you no longer need any definers
of negative space...
John
On 03/24/2011 08:12 PM, Dave McGuire wrote:
http://ecosensory.com/tek/tek_7k_flex-prototype-1-sm.gif
Whoa, you're doing some Tek 7000-series plugin hacking? Mind if I ask for more
information?
Hi Dave,
Dave Casey asked for plugin prototyping capability for some ideas he has.
I have not
On 03/07/2011 03:56 PM, Rob Butts wrote:
I got it! Normally I hit the shift key once and it holds it down for
one key stroke or mouse click but this time I had to hit the shift key
twice to get it to hold down.
Good. I was thinking maybe the key shortcuts could be remapped, but that
On 03/06/2011 02:57 PM, Rob Butts wrote:
Is there a standard for pad thickness, mask diameter and clearance for
thru-holes?
For wire to board? Not sure. Probably somewhere in some corporation
in the last 60 years...
Soldering works very forgivingly -- even with no-lead. I'd just use
On 03/05/2011 05:04 AM, Peter Clifton wrote:
It depends on the primitives used - but I expect it is not too hard
either way. SVG does of course support a lot of things which RS-274X
cannot though.
OK. YOU can make SVG that is easily translatable, but if you had a
footprint tool that used it
On 03/05/2011 02:41 PM, Markus Hitter wrote:
it might be less work to replace or complement the current track drawing
stuff with a generic SVG drawing library. Then every
layout is also a valid SVG file and can be edited with other applications
as well. The tricky part is keeping the connection
On 03/05/2011 01:24 PM, Oliver King-Smith wrote:
Is there a way to get a pin or netlist count for a multi-page schematic
in gschem?
I'd run the netlist through a python script that counts the pins
that are in the form symbolname1-pinname1. But that would give
you the pins used by the
On 03/05/2011 07:41 PM, Steven Michalske wrote:
At work we use odb++ valor files.
That sounds like the rumor I heard.
odb sounds open. I bet it just sounds open and creates vendor lock in..
Uh... yeah. Like I thought:
http://www.artwork.com/odb++/odb++_overview.htm
On 03/02/2011 12:53 AM, yamazakir2 wrote:
I bought a $30 toaster oven from walmart and yeah you guys are right
it seems to work fine.
If you buy a ramp and soak thermocouple controller off ebay, and
graft the two together, it will work as well as the
IR Reflow Station box from China. The
On 03/02/2011 06:49 AM, Stefan Tauner wrote:
my idea is some combination of the existing propsals:
- Gschem parts manager or parts database (glue)
- IPC Footprint Calculator (pcb)
and my own idea: a stand-alone pcb footprint editor.
A footprint calculator that uses IPC guidelines plus an
On 03/02/2011 03:56 PM, Bert Timmerman wrote:
And
https://github.com/bert/pcb-fpw/wiki/User-Manual-for-pcb-gfpw
This one is aimed to be more resembling with the IPC Footprint Calculator
without violating IP and such.
I hope to release version 0.0.11 this month.
Wow! That will be really
On 03/04/2011 06:24 PM, Steven Michalske wrote:
I thought basing it on svg with layers defined to be each layer in a layout.
But SVG is a shape outline format and RS-274X is centerline and width format.
A round ended pad in RS-274X is a pair of points to define a line and a number
to define
On 02/23/2011 01:04 PM, John Griessen wrote:
I have 1.6GB RAM free before starting connects--autoroute and all the RAM
but 64K is used during autoroute for 12 seconds of CPU time over
about 40 seconds.
I wasn't reporting CPU time right though, it uses minutes, and I needed to
subtract
On 02/23/2011 01:20 PM, John Griessen wrote:
I wasn't reporting CPU time right though, top TIME+ uses minutes, and I needed
to
subtract the time when I start to be meaningful. It's more like 5 or 6 minutes
of top TIME+, but only 1.5 minutes wall clock time
til it seg faults.
JG
On 02/23/2011 01:38 PM, yamazakir2 wrote:
what do you guys use to get it looking flux-free
and clean again?
If you use water wash flux and solder paste, you can use hot
water and a little detergent. Could use the dish washer machine too.
John
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On 02/23/2011 02:20 PM, yamazakir2 wrote:
Is
water soluble flux better (for cleaning)?
The salesman from Nordson EFD (electronic fluid dispensing) said so.
They sell the systems for medium volume where you use paste dispensing instead
of
or to augment solder paste masks, so you can do a
On 02/23/2011 03:49 PM, Stephan Boettcher wrote:
For example the outline of the board on the attached picture
Looks like a sea urchin! Yay non-GUI!
JG
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On 02/23/2011 01:39 PM, John Griessen wrote:
On 02/23/2011 01:20 PM, John Griessen wrote:
I wasn't reporting CPU time right though, top TIME+ uses minutes, and I needed
to
subtract the time when I start to be meaningful. It's more like 5 or 6 minutes
of top TIME+, but only 1.5 minutes wall
On 02/23/2011 09:09 PM, John Griessen wrote:
==32105== Whatever the reason, Valgrind cannot continue. Sorry.
Seems like the problem may not even be related to pcb...
But it's triggered by pcb. The swap amount grows fast at first, then when
about 3GB of RAm is used the rate slows to only
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