aren't in favour, you are excluded.
Perhaps we can draft some mailing list policy for geda-dev which
encourage conversation to remain on-topic.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0
with components. If this
costs us users, it costs the project.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone
nice, but it works. I've attached an example.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
On Thu, 2010-12-09 at 18:53 +0100, Stefan Salewski wrote:
On Thu, 2010-12-09 at 17:23 +, Peter Clifton wrote:
On Thu, 2010-12-09 at 10:34 -0500, George M. Gallant, Jr. wrote:
I am looking to make a trapezoid shaped pad for an inductor. So far, I
created
a rectangular pad and drew
On Thu, 2010-12-09 at 20:46 +0100, Bert Timmerman wrote:
shameless plug
...
your personal dev-blog), on-line editing files, etc etc -- Github rocks,
...
/shameless plug
Do you work advertising for GitHub in your spare time Bert? ;)
--
Peter Clifton
Electrical Engineering Division
(especially in favour of the move ;)).
I'd also welcome feedback from anyone who works with bug reports, test
patches, merge code etc... (Doesn't have to be with gEDA / PCB, anything
regarding Launchpad / SourceForge).
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University
to get your name on the commit log,
and I did not. VERY sorry about that, especially after all the help
you've given me with testing things.
AH HECK.. I'm going to break a rule and non-fast-forward push them again
with the appropriate credit.
Best wishes,
--
Peter Clifton
Electrical Engineering
it is required.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
any errors
if asserts are disabled.
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9
such long lines).
Best wishes,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
, there
are still plenty of areas where I'm not so familiar with the original
design, and am hesitant to touch. gnetlist, gattrib and certain bits in
the very core of PCB fit into that category.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson
) that
things will get better.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
over the
next few days. (If not, I'll make a personal point of trying to help
sort it out!)
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0
container of p within the same function. (Common in our destructors /
cleanup code).
I've got the basis for the patch which I can send. (Just not all cases
of MyStrdup have been fixed).
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ
as only around 1MB is leaked
^___ ONLY?!!!
Good work Stephen! I'll push that now.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173
it, I should also just give you the benefit of the
doubt and push the patches. (If they were to break anything, they could
always be reverted!)
Let me know what you want.. either I can push the patches unread, or
pass them to Peter B to see if he has time to review them.
--
Peter Clifton
Electrical
, but I'm not sure if I have _write_ access).
I don't even have _read_ access to the gpleda.org htdocs.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel
and symptoms, I guess some r_trees are being
leaked in the autorouter code?)
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328
-local_customisation_pours
Now onto your questions:
On Mon, 2010-12-06 at 16:25 +0100, Kai-Martin Knaak wrote:
Peter Clifton wrote:
Stack order is as follows:
For PCB without pours:
local_customisation_no_pours -- This is fastest, most shiny,
but contains some local stuff like mouse
); directly elsewhere.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
On Tue, 2010-12-07 at 00:48 +, Peter Clifton wrote:
On Tue, 2010-12-07 at 10:04 +1100, Stephen Ecob wrote:
Dropping the (a) ? (a) : 1 foolishness would be cleaner, but could
expose latent bugs in the 71 callers of the mymem allocators.
I'm happy to proceed either way. What is your
On Tue, 2010-12-07 at 11:58 +1100, Stephen Ecob wrote:
On Tue, Dec 7, 2010 at 11:48 AM, Peter Clifton pc...@cam.ac.uk wrote:
On Tue, 2010-12-07 at 10:04 +1100, Stephen Ecob wrote:
Dropping the (a) ? (a) : 1 foolishness would be cleaner, but could
expose latent bugs in the 71 callers
-report though, it is now fixed for 2D view..
everything is given z=0, so no rendering issues.
Let me know how you find the pcb+gl_experimental branch.
Btw, since I've re-jigged things, you won't have to suffer my
mouse-binding changes when playing with my experimental branch.
--
Peter Clifton
origin/master
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
a
back-trace to see which code caused the allocation before any could be
fixed.
I believe valgrind is good at detecting leaks!
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173
-automatic routing where you sketch the
topology of a net with the mouse (or some other input device).
Sounds like we're thinking along similar lines. I could easily have
unconsciously absorbed your ideas and suggestions without realising I
was re-hashing stuff which has already been said.
--
Peter
that freerouting.net lists gEDA as being supported.. is that
true?
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask
,
with flashed clearances for pads etc., drawn clearances for lines.
Currently, I feel we loose too much information, and gain too muchhel
detail by flattening curves and boolean operations on geometry to
polygons at the stage we do.
--
Peter Clifton
Electrical Engineering Division,
Engineering
?
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
___
geda
definitions
Implement file-format changes (possible totally new file format?)
Arbitrary layer types / stacks
Arbitrary pad types / stacks
Release?
Pours support
Release?
3D model support
Release?
OTHER STUFF I TALKED ABOUT
--
Peter Clifton
Electrical Engineering Division,
Engineering Department
On Fri, 2010-11-26 at 13:00 +, Peter Clifton wrote:
On Fri, 2010-11-26 at 12:13 +0100, Kai-Martin Knaak wrote:
Peter Clifton wrote:
Ok. I recloned(*) compiled and benchmarked my pidpeltier layout with full
polygons and with poly_thin_draw. Hardware is my day job desktop, nvidia
breaking whatever method
you use, but if we can cooperate, I'll try and do it in a way which
isn't so hard to fix ;)
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal
On Fri, 2010-11-26 at 12:13 +0100, Kai-Martin Knaak wrote:
Peter Clifton wrote:
Ok. I recloned(*) compiled and benchmarked my pidpeltier layout with full
polygons and with poly_thin_draw. Hardware is my day job desktop, nvidia
quadro, closed source driver.
current HEAD:
full poly: 15
On Fri, 2010-11-26 at 12:13 +0100, Kai-Martin Knaak wrote:
Peter Clifton wrote:
So.. please fetch git HEAD PCB and play with things.
current HEAD:
full poly: 15 FPS
thin draw: 25 FPS
version 20091103 as it is distributed in debian/squeeze
full poly: 31 FPS
thin draw: 25 FPS
Yes
one?
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
On Tue, 2010-11-23 at 23:37 +, Peter Clifton wrote:
Hi geda-users, Kai-Martin,
Since I know some people have expressed an interest in why PCB+GL hasn't
hit stable yet, I realised earlier that there was another step which is
necessary... (besides cleaning up the hacks I made on top
On Wed, 2010-11-24 at 11:06 +0100, Kovacs Levente wrote:
On Tue, 23 Nov 2010 15:56:39 +
Peter Clifton pc...@cam.ac.uk wrote:
This is probably not something we'd commit as is to PCB, as for some
cases, DRC warnings on the outline layer could be useful, but Bdale
was looking
On Wed, 2010-11-24 at 22:05 +0100, Kai-Martin Knaak wrote:
Peter Clifton wrote:
The polygon_speedup branch should mostly be a success, but I'm fairly
sure it does increase CPU cycles for some operations. I've not had a
chance to test it very scientifically, and I'm hesitant to push
is needed IIRC, and that is not _all_ that
old.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
.
Do it a few times.. does the trace location change, or stay the same?
There may also be ways and means to debug by passing options to the GL
driver, but I don't know any specifics for Radeon.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ
effect.
NB: You WONT get warnings if your outline touches / cuts off any parts!
Best regards,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223
of all the contours within a polygon.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
define the beginning of a slot?
Oliver
The attributes list here might be of help..
http://www.geda.seul.org/wiki/geda:master_attributes_list#numslots
Note that each pin needs a valid pinseq.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University
has been done / is being / has been worked on:
http://sourceforge.net/tracker/?func=detailaid=2684726group_id=73743atid=538813#
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173
in characters as plain polygons. So it's possible (though
rather tedious) to manually edit the generated PCB file and turn the
hole-polygons into holes in their correct polygons.
See the post I just RESENT: to the mailing list. It might be of use to
you both.
--
Peter Clifton
Electrical
to make use of. (Which would then make PCB create the file).
In this idealised version of the future, the only immediate way you
would have to override the font is to edit PCB's default font,
$PREFIX/share/pcb/default_font
--
Peter Clifton
Electrical Engineering Division,
Engineering Department
= attributes which wire up their power pins. The idea is solid
though.
Best regards,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328
more boring work. I've almost been tempted to set myself the goal
of merging the PCB+GL (non-3D) bits this week ;)
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal
out the detail. Some work would be needed if you wanted
to reliably look through a section of board in a particular place
though.. possibly some adjustment of layer transparency would be in
order.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9
by existing staff, rather than go out to contract assembly with
a long lead-time.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared
, but with different textures attached).
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
dimensions and layers. Don't confuse rigid body with solid geometry.
Maybe my view is to pessimistic, but one needs to read the spec to prove.
I've seen claims 1.5 supports BREP.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue
On Sat, 2010-11-20 at 22:48 +, Gareth Edwards wrote:
The usability of the Blender 2.5x betas is a step-change from the
existing versions. I'm not saying it's easy, but it's considerably
less insane.
Just installed it, seems pretty good compared with 2.45.
Thanks for the pointer!
--
Peter
on a VRML importer at the moment, as this will give us
access to models people have created for KiCad. (And hopefully the
converse too, when PCB+GL+3D lands and users start creating models).
/me hating flex and bison like a pro now ;)
Best wishes,
--
Peter Clifton
Electrical Engineering Division
On Fri, 2010-11-19 at 01:29 +0100, kai-martin knaak wrote:
Peter Clifton wrote:
stl (very nice)
IMHO, stl is a mesh only format. That is, everything is made of
triangles -- no squares, no circles, no real curvatures. There are
no macros, no loops, or repetitions.
That suits me just fine
On Fri, 2010-11-19 at 17:30 +, Richard Barlow wrote:
On Fri, 2010-11-19 at 17:21 +, Peter Clifton wrote:
http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d_packages_mockup3.png
http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d_packages_mockup4.png
Wow, they look
users generating models.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
On Fri, 2010-11-19 at 17:43 +, Peter Clifton wrote:
On Fri, 2010-11-19 at 06:15 -0500, Patrick Doyle wrote:
Not knowing anything of which I speak (write?), would COLLADA
(https://collada.org/mediawiki/index.php/COLLADA_-_Digital_Asset_and_FX_Exchange_Schema)
fit the bill? I just
as there is a lot more referencing which is done by name within the DOM,
rather than implied by the structure of the file.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal
: cylindrical resistors, disc-shaped ceramic capacitors,
My shiny through hole resistor screen-shots had approx 6000 panels, and
yes, it does slow things down if you have lots on screen at once!
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9
On Fri, 2010-11-19 at 14:07 -0800, Colin D Bennett wrote:
It has to be mentioned that Blender is free and open source but Google
Sketchup is not.
I took that as known, but I don't disprove of using good commercial
software to do a job. I find Blender quite challenging to work with.
--
Peter
component models, no.. let GL deal with it. It is
unlikely you'll zoom into one so close that culling panels on the CPU
will be a big win.
It _is_ very helpful for board geometry though.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson
the texture space basis vectors rather than CPU.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
On Sat, 2010-11-20 at 02:39 +0100, kai-martin knaak wrote:
Did I mention, that mesh formats are a one way road, when it
comes to construction?
(Please tell me, that I don't need to make that point over and over
again ;-)
Got it ;)
--
Peter Clifton
Electrical Engineering Division
go back and try again.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
On Sat, 2010-11-20 at 03:00 +0100, kai-martin knaak wrote:
Peter Clifton wrote:
when PCB+GL+3D lands and users start creating models).
^
I'd love to see PCB+GL enter the main repo rather than wait until
3D is mature enough, too.
I've been slowly tinkering
On Sat, 2010-11-20 at 02:05 +, Peter Clifton wrote:
Wings3D can export to most if not all the formats I'm interested in, but
now you make me feel stupid.. I couldn't figure out how to get started
with it other than opening existing models. Since you say it is newbie
friendly, I'll go back
On Mon, 2010-11-15 at 10:09 -0600, John Griessen wrote:
On 11/14/2010 08:37 PM, Peter Clifton wrote:
3. What format would people like to make models in?
STEP, so I can load it in HeeksCAD and use HeeksCNC to carve enclosures.
Step looks obscenely complicated, and I'm not really sure what
of ease in processing would be:
stl (very nice)
iges (simple format, but I have no clue what the syntax is ;))
STEP (_utterly_ evil format).
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729
is extrude a geometry defined in a
2D DXF-file (made with QCAD for instance), this would allow for arbitrary
shaped boards.
Nice.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173
On Tue, 2010-11-16 at 00:01 +0100, Armin Faltl wrote:
I'm thinking VRML (perhaps as output by Wings32) might be a good choice,
as I believe this is what KiCad uses.
Same, need to check details, e.g. if dimensions and layers are supported.
VRML (as I understand it) is surfaces only.
On Mon, 2010-11-15 at 02:37 +, Peter Clifton wrote:
An actual rendering from PCB+GL with some code I've been playing with...
http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d_packages_mockup.png
And I figured out lighting a little better, and in the process ran into
a nasty bug
?
2. Will anyone bother to make 3D models for packages?
3. What format would people like to make models in?
I'm thinking VRML (perhaps as output by Wings32) might be a good choice,
as I believe this is what KiCad uses.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department
.
Contact me off-list for shipping details to the UK ;)
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
On Tue, 2010-11-09 at 23:47 +, Peter TB Brett wrote:
On Tue, 09 Nov 2010 23:08:15 +, Peter Clifton pc...@cam.ac.uk wrote:
Try again now.. it is possible that I didn't have the correct patches
pushed at that point. I was just pushing something out just now for
someone at Intel
too much in terms of build requirements
since then.
sudo apt-get build-dep pcb
That should help get you started.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal
.
Regarding this bug.. the colour looks like the errors are coming from
one of your polygon layers. Does it go away with certain layers
disabled?
What is the minimum board which exhibits the problem? Does it relate to
certain objects on the board, or is it general?
--
Peter Clifton
Electrical
On Wed, 2010-11-10 at 23:13 +, Peter Clifton wrote:
On my AMD Mobility Radeon HD3450 (driver: radeonhd) system (debian,
stable but old!) and your local_customisation_no_pours branch (without
the recent patches) the line ends look wrong
http://www.frajasalo.de/frank/projekt/pcb
On Tue, 2010-11-09 at 22:39 +0100, Frank Bergmann wrote:
Am 09.11.2010 01:16, schrieb Peter Clifton:
Tweakable options are:
Uncommenting
// buffer-use_vbo = false;
or
removing / commenting:
buffer-use_map = false;
from hid/common/hidgl.c's hidgl_init_triangle_array
hidgl_init_triangle_array()
use_vbo = false; will give you arrays (always)
Removing use_map = false; will give you mapping with use_vbo, or arrays without.
Regards,
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44
, as we
often
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
) to discard the
previous data). The only penalty ought to be allocating card / driver
memory, and this ought to happen in a ring like fashion from identically
sized areas we've previously completed rendering from.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University
.
I'll try the suggested patches later today. Some real work needs to be
done now...
Thanks for testing..
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab
On Fri, 2010-11-05 at 09:37 -0700, Ben Jackson wrote:
On Fri, Nov 05, 2010 at 09:46:00AM +, Peter Clifton wrote:
Other than this, I don't know why glMapBuffer() doesn't just work
performantly
I would expect it to map GPU memory directly via PCI, which is going to
have much higher
On Thu, 2010-11-04 at 16:43 +0100, Kai-Martin Knaak wrote:
Peter Clifton wrote:
Using VBOs that gives 85.4FPS, so effectively no difference.
Using arrays it gives an average of 93.1FPS, literally no difference!
Thanks for trying it. I'm embarassed to say your board manages about
9fps
to vblank events, so there might be some dead-time in
the rendering.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone
stuff, but I had no idea it was
so near ready. Well done!
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask
On Wed, 2010-11-03 at 15:19 -0300, John Coppens wrote:
On Wed, 03 Nov 2010 17:29:04 +
Peter Clifton pc...@cam.ac.uk wrote:
Here is the gotcha.. the VBO code didn't really work on the NVidia
machine.. rendering got really slow. If you discover this, you can force
it back to using
On Wed, 2010-11-03 at 21:54 +0100, Kai-Martin Knaak wrote:
Peter Clifton wrote:
If VBO rendering slows you down,
Ehm, how would I know, that this is the the actual bottle neck?
(What is VBO, anyway?)
Vertex buffer object:
http://en.wikipedia.org/wiki/Vertex_Buffer_Object
Throw
On Wed, 2010-11-03 at 22:04 +0100, Kai-Martin Knaak wrote:
Peter Clifton wrote:
I've got a load of changes I've been working on recently in PCB+GL, this
time on my local_customisation_no_pours branch.
For those not familiar with git, these are the commands I ran to install
Peters
On Thu, 2010-11-04 at 00:48 +, Peter Clifton wrote:
It is interesting to note that git HEAD PCB is slower than 20091103. I
wonder what I broke ;) (There might be some performance trade-offs which
have been made to improve other activities).
I might have to dig into that, as it is quite
On Wed, 2010-11-03 at 21:54 +0100, Kai-Martin Knaak wrote:
Peter Clifton wrote:
If VBO rendering slows you down,
Ehm, how would I know, that this is the the actual bottle neck?
(What is VBO, anyway?)
And to answer your other question... you don't know unless you apply the
patch in my
.. try shrinking the PCB window to the smallest possible size.. does
that increase framerate much? If you know how for your drivers (I
don't), try disabling sync to vblank.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue
to an extra buffer copy, perhaps with a blend
operation.
You might get a slight improvement without compiz, but it is typically
minimal. I usually test with compiz off just to be sure though.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ
On Thu, 2010-11-04 at 02:13 +, Richard Barlow wrote:
On Thu, 2010-11-04 at 02:01 +, Peter Clifton wrote:
Perhaps try with the patch I just sent in reply to KMK which moves a
couple of glEnableClientState calls.
Using VBOs that gives 85.4FPS, so effectively no difference.
Using
back to writing kernel profiling driver for intel GPUs to
squeeze more framerate out of PCB+GL.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0
On Sun, 2010-10-31 at 20:49 +0100, kai-martin knaak wrote:
Peter Clifton wrote:
/me goes back to writing kernel profiling driver for intel GPUs to
squeeze more framerate out of PCB+GL.
Side note: I just purchased a used ATI Radeon HD 4670 that free3d.org
announces as the fastest card
On Sun, 2010-10-31 at 22:29 +0100, Stefan Salewski wrote:
On Sun, 2010-10-31 at 19:30 +, Peter Clifton wrote:
/me goes back to writing kernel profiling driver for intel GPUs to
squeeze more framerate out of PCB+GL.
Indeed I wonder why framerate is critical -- is this only
.
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
.
--
Peter Clifton
Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA
Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me
401 - 500 of 2064 matches
Mail list logo
