On 14/09/10 18:59, DJ Delorie wrote:
I like canvas - it's a more popular idiom than cel.
Perhaps film? It gives a sense of translucency, making the idea of
overlaying multiple films feel more natural and obvious. Also it has
a historical link to PCB production, from the days of taping tracks
On Mon, Sep 13, 2010 at 10:20:52PM -0400, Matthew Sager wrote:
[*] We need a better term for drawing layers, since layer means
something specific in PCB design. Or another name for physical
layers. Or something ;-)
How about overlay?
Canvas comes to mind. It
On Sep 14, 2010, at 7:23 AM, Andrew Poelstra wrote:
On Mon, Sep 13, 2010 at 10:20:52PM -0400, Matthew Sager wrote:
[*] We need a better term for drawing layers, since layer means
something specific in PCB design. Or another name for physical
layers. Or something ;-)
How about
I like canvas - it's a more popular idiom than cel.
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I like canvas - it's a more popular idiom than cel.
Indeed it is.
My concern about canvas is that it does not convey a relationship to our
physical layers. In some cases it would be reasonable to expect a canvas
to refer a full layer or even to a stack of layers. IMHO, it would be
beneficial
On Tue, Sep 14, 2010 at 02:57:31PM -0400, Windell H. Oskay wrote:
I like canvas - it's a more popular idiom than cel.
Indeed it is.
My concern about canvas is that it does not convey a relationship to our
physical layers. In some cases it would be reasonable to expect a canvas
to refer
On 12.09.2010 00:20, Peter Clifton wrote:
(Can someone who uses / has used keepouts on another package describe
for me how they work, or how you use them?)
(In our company we are using a 5 year old package that has support for
keepouts. It has pre-defined one keepout layer where the user can
On 09/13/2010 05:07 PM, John Doty wrote:
On Sep 13, 2010, at 2:27 PM, DJ Delorie wrote:
So let me rephrase: Why have seven geometric holes,
one for each layer, when we can have one geometric hole applied to the whole
composite?
snip
My notion is that you need a general mechanism to align
On Tue, Sep 14, 2010 at 10:34:23PM -0500, John Griessen wrote:
On 09/13/2010 05:07 PM, John Doty wrote:
On Sep 13, 2010, at 2:27 PM, DJ Delorie wrote:
So let me rephrase: Why have seven geometric holes,
one for each layer, when we can have one geometric hole applied to the
whole
DJ Delorie d...@delorie.com writes:
But I figure the top/inner/bottom class is what we need for
importing footprints. They'd be layered by class, not number, so they
can adapt to whatever number of layers the board has.
Rigid-Flex boards have pads on more than two layers. There are pads on
DJ Delorie d...@delorie.com writes:
And I think the only way to do ... in a non-kludgy way
Yet another example of you automatically putting down any idea that
isn't yours. Please stop that. Please consider the possibility that
someone might come up with a better (or even equally good) idea
On Fri, 10 Sep 2010 18:11:05 -0400
DJ Delorie d...@delorie.com wrote:
And I think we need anti-layers to handle some soldermask and paste
issues anyway.
I think the soldermask layer can be an anti-layer.
--
Kovacs Levente leventel...@gmail.com
Voice: +36705071002
On Sep 12, 2010, at 9:09 PM, DJ Delorie wrote:
If a cutout is a property of an insulating layer, the a drill through
the whole PCB is really a composite of 2N+1 drills through N insulating
layers and N+1 conductor layers.
I'll call that the geometric viewpoint.
That seems kludgy to me.
On 09/12/2010 08:39 PM, John Doty wrote:
On Sep 12, 2010, at 1:49 PM, Rick Collins wrote:
Sounds suspicious. Are you sure you aren't talking about an assembly with
boards and a case? Bolts aren't normally
considered vias. ;^)
No, I'm talking about a narrow board with two rigid parts at
On 09/12/2010 10:09 PM, DJ Delorie wrote:
I'm thinking we structure the layers into composites. Each
composite contains some conductor/insulator layers, including other
composites, and an overall shape (outline, drills, slots).
Thus, a drilling operation is stored as a single drill object in
On 09/12/2010 10:36 PM, Andrew Poelstra wrote:
In theory, PCB never needs to know how an entire pcb assembly is
composed. That's the fab's job. IME most multi-PCB projects involve
socket/plug combinations so that the different components can plug
into each other and you don't have to worry about
On Mon, Sep 13, 2010 at 12:28:53AM -0400, DJ Delorie wrote:
but we've still got a user-interface problem.
We're used to that.
So what happens for those users?
They get exactly one composite, which ends up acting just like what we
have today - one outline, one set of drills, all
On Mon, 2010-09-13 at 08:37 -0700, Andrew Poelstra wrote:
It would be nice to support multiple .pcbs open at once, and to allow
copy/pasting between them.
That wouldn't be so hard to support between PCB instances. Do it like in
gschem, and have the X11 / toolkit clipboard mechanism transfer a
Andrew Poelstra as...@sfu.ca writes:
On Sun, Sep 12, 2010 at 03:40:24PM -0400, DJ Delorie wrote:
With flex cable, top and bottom aren't limited to one layer each.
Aren't they?
No. Different areas of the cable may have extra layers or pcbs
attached, changing the number of layers in
Now, the question becomes which is more fundamental?. I think
it's geometry.
A hole is the same geometry regardless of what level of the heirarchy
it's placed at. So let me rephrase: Why have seven geometric holes,
one for each layer, when we can have one geometric hole applied to the
whole
In our previous example, you'd get (1 2 3 4 5 6 7 8 ...)
Okay, but where does that leave us in terms of having multiple drawing
layers on the same physical surface?
(1 2 3 4 5 6 7 8 ...)
grouping in a composite and assignment to physical layers are two
different things. An element, for
On Mon, Sep 13, 2010 at 04:29:07PM -0400, DJ Delorie wrote:
In our previous example, you'd get (1 2 3 4 5 6 7 8 ...)
Okay, but where does that leave us in terms of having multiple drawing
layers on the same physical surface?
(1 2 3 4 5 6 7 8 ...)
grouping in a composite and
On Sep 13, 2010, at 2:27 PM, DJ Delorie wrote:
Now, the question becomes which is more fundamental?. I think
it's geometry.
A hole is the same geometry regardless of what level of the heirarchy
it's placed at. So let me rephrase: Why have seven geometric holes,
one for each layer,
DJ Delorie d...@delorie.com writes:
Now, the question becomes which is more fundamental?. I think
it's geometry.
A hole is the same geometry regardless of what level of the heirarchy
it's placed at. So let me rephrase: Why have seven geometric holes,
one for each layer, when we can have
So drills, stacking order and physical layer geometry will be defined
in terms of composites, and drawing layers will be tagged to physical
layers?
Do we need a concept of layer groups in this setup?
In that example, the layer groups would be implied - drawing layers[*]
mapped to the same
I think that an object that spans more than one layer cannot
sensibly be considered primitive in a layer-centric description of
geometry.
Then stop thinking in terms of being layer-centric.
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On Mon, Sep 13, 2010 at 06:16:47PM -0400, DJ Delorie wrote:
So drills, stacking order and physical layer geometry will be defined
in terms of composites, and drawing layers will be tagged to physical
layers?
Do we need a concept of layer groups in this setup?
In that example, the
On Mon, Sep 13, 2010 at 04:29:07PM -0400, DJ Delorie wrote:
In our previous example, you'd get (1 2 3 4 5 6 7 8 ...)
Okay, but where does that leave us in terms of having multiple drawing
layers on the same physical surface?
(1 2 3 4 5 6 7 8 ...)
What's the physical meaning of an
What's the physical meaning of an eight-layered composite?
A board with eight copper layers, assuming the eight drawing layers
each map to a different physical layer. Making the structure flat
just means that all your drills and outlines apply to all layers
equally.
So wouldn't a better
On Mon, Sep 13, 2010 at 08:58:54PM -0400, DJ Delorie wrote:
What's the physical meaning of an eight-layered composite?
A board with eight copper layers, assuming the eight drawing layers
each map to a different physical layer. Making the structure flat
just means that all your drills and
I don't think we're ready for code yet :-)
Besides, I was hoping to switch to C++ before doing any major internal
changes. Then, a composite is just a container of objects, one of
which may be itself a composite, but might include drills, drawing
layers, etc.
[*] We need a better term for drawing layers, since layer means
something specific in PCB design. Or another name for physical
layers. Or something ;-)
How about overlay?
Canvas comes to mind. It hints that you draw on it. Or this could
just be the fact that I have
On Sep 13, 2010, at 6:45 PM, Andrew Poelstra wrote:
On Mon, Sep 13, 2010 at 08:58:54PM -0400, DJ Delorie wrote:
What's the physical meaning of an eight-layered composite?
A board with eight copper layers, assuming the eight drawing layers
each map to a different physical layer. Making
On Mon, Sep 13, 2010 at 07:24:57PM -0700, Steven Michalske wrote:
On Sep 13, 2010, at 6:45 PM, Andrew Poelstra wrote:
/*** BEGIN ***/
/*
* The layer structuring works as follows:
* 1. At the physical level, PCBs are composed of composites. These
* composites have an
C2 and C3 is set to thickness 1mm.
C1 is set to thickness 5mm.
There is a discrepancy! How should we resolve this?
By telling the user they're wrong, or by just ignoring the problem
until the data's needed.
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Okay, courtyard. Thanks for the nomenclature help :-)
I'm just thinking of a couple of parts for a design that I'm working on
where I need to make sure that I don't put any more parts in between
areas of the footprint, but traces are ok because they're part of the
board and won't
PCB has nothing special for keep-outs of any sort.
I just use the silkscreen to show where the part goes, including the
courtyard.
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Hi all,
-Original Message-
From: geda-user-boun...@moria.seul.org
[mailto:geda-user-boun...@moria.seul.org] On Behalf Of Bob Paddock
Sent: Sunday, September 12, 2010 1:40 AM
To: gEDA user mailing list
Subject: Re: gEDA-user: next PCB release - 1.99za vs 4.0
In Protel
On Sun, Sep 12, 2010 at 12:24 AM, DJ Delorie [1...@delorie.com wrote:
The top/bottom magic are needed to map footprints on
import
Don't over look buried components. Becoming more common.
I think it would be better to just have layers, that you assign a
function to, rather
On Sun, Sep 12, 2010 at 12:55 AM, DJ Delorie [1...@delorie.com wrote:
I suspect that in the main GUI you'd get a simplified set of
options,
like add layers or remove layers to switch from, say, 2-layer
PCBs
to 4-layer PCBs, etc.
In Protel there is such a dialog.
On Sun, Sep 12, 2010 at 1:40 AM, Jonathon Schrader
jlsch...@jlschrad.net wrote:
That is, a footprint (such as the battery mount mentioned previously) with a
requirement not to place any parts between the tabs, but traces are fine?
It would be good to be able to say place no component
Hi all,
-Original Message-
From: geda-user-boun...@moria.seul.org
[mailto:geda-user-boun...@moria.seul.org] On Behalf Of Bob Paddock
Sent: Sunday, September 12, 2010 1:52 PM
To: gEDA user mailing list
Subject: Re: gEDA-user: next PCB release - 1.99za vs 4.0
On Sun, Sep 12, 2010
Maybe you could add an attribute to an element defining the height.
Something like: Attribute (element_height=, 5 mm)
That would be required to do 3D also. There would also need to be a
clearance space above the actual part thickness as well.
Think about boards that are flexing/vibrating.
On Sun, 12 Sep 2010 14:49:02 +0900
timecop time...@gmail.com wrote:
Most places handle this with the assembly layer.
Of course, this wouldn't be part of DRC, but you'd have to be blind
put stuff overlapping assembly layers and not see it right away.
Imagine having to make a change to the
On Sun, Sep 12, 2010 at 12:55:54AM -0400, DJ Delorie wrote:
I suspect that in the main GUI you'd get a simplified set of options,
like add layers or remove layers to switch from, say, 2-layer PCBs
to 4-layer PCBs, etc. Outer special layers like silk and mask just
exist, but you can
I think it would be better to just have layers, that you assign a
function to, rather than have layers have magic properties.
As flexible as I'd like to be, I think it's implied when designing
circuit boards that there's going to be outside layers on them.
From a practical viewpoint,
When you say just exist, you mean they are there by default on new
boards, not that they're magic layers, right?
There by default on new boards - yes
not magic - well, I still think intended purpose is something that
PCB needs to know about, to do its job well. We can allow for
exceptions by
Vanessa Ezekowitz wrote:
Maybe you're tired, maybe the board just has a metric assload of
parts, maybe you're pressed for time. Who knows?
+1
This is what DRC is meant for. A reliable check for stupid errors. I
often feel like doh, how could I be so blind when DRC shows
violations.
On Sun, Sep 12, 2010 at 12:53:57PM -0400, DJ Delorie wrote:
Well, a both-sides silkscreen layer makes little sense. If a user
wanted that, he could duplicate the top silkscreen to get the bottom
one. I don't think that would be common enough to require special
code.
Outlines for
Well, a both-sides silkscreen layer makes little sense.
Actually it does make sense. Think about a transformer with through-hole pins.
You want the top silk to show the courtyard, for clearances. You want
the bottom silk to show the pin numbers/labels.
--
http://blog.softwaresafety.net/
On Sun, Sep 12, 2010 at 12:38 PM, DJ Delorie d...@delorie.com wrote:
I think it would be better to just have layers, that you assign a
function to, rather than have layers have magic properties.
As flexible as I'd like to be, I think it's implied when designing
circuit boards that there's
Alright, we'll allow a top and bottom layer group.
With flex cable, top and bottom aren't limited to one layer each.
I think that if we want components on multiple layers (or all
layers), that should be a property of the component, not a layer
group/physical layer thing.
What's
Flex Circuit in a Mobius configuration.
They still have outsides, just not two of them.
I'm going to go out on a limb and state that I refuse to support
non-flat layers :-)
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On Sep 12, 2010, at 10:35 AM, Bob Paddock wrote:
Well, a both-sides silkscreen layer makes little sense.
Actually it does make sense. Think about a transformer with through-hole
pins.
You want the top silk to show the courtyard, for clearances. You want
the bottom silk to show the pin
On Sun, Sep 12, 2010 at 01:56:43PM -0400, DJ Delorie wrote:
Alright, we'll allow a top and bottom layer group.
With flex cable, top and bottom aren't limited to one layer each.
Aren't they? All layers except the top-most and bottom-most are
considered inner layers. This whole
On Sun, Sep 12, 2010 at 01:57:32PM -0400, DJ Delorie wrote:
I meant ONE silk layer printed on BOTH sides of the pcb. Much like
fabs often have an option for same mask both sides - one layer, used
twice.
Okay, I see what you're gettting at here with same layer, multiple
physical layers. And
With flex cable, top and bottom aren't limited to one layer each.
Aren't they?
No. Different areas of the cable may have extra layers or pcbs
attached, changing the number of layers in that area. So one drawing
layer might be top on the left side of the cable, but inner on the
right side.
Now, how is the relationship between drawing layers and physical layers
going to be shown to the user?
I think dual-color traces would be nice. (That is, have the main color
correspond to the physical layer, with a stripe on the left side (say)
corresponding to the drawing layer.)
What
At 03:42 PM 9/10/2010, you wrote:
On Sep 10, 2010, at 1:01 PM, DJ Delorie wrote:
I figure we need each layer to specify:
* type (copper, silk, mask, anti-copper, keepout, etc)
There are no types, there are only properties.
The conductors may not be copper. I've even worked with a board
At 03:45 PM 9/12/2010, you wrote:
Interesting thought - for buried vias, the top and bottom layers
correspond to inner physical layers, yet they need to be treated
differently as the annulus often needs to be bigger on layers where
the trace connects. So an internal buried via element, before
Bigger??? Why do you need an annulus on an inner layer that doesn't
connect to a trace?
Depending on the fab technique, you may need an annulus just to fill
the gap between fr4 layers so that the electroplating is reliable.
Either that, or you need to keep *other* copper far enough away that
On Sun, Sep 12, 2010 at 03:45:18PM -0400, DJ Delorie wrote:
Interesting thought - for buried vias, the top and bottom layers
correspond to inner physical layers, yet they need to be treated
differently as the annulus often needs to be bigger on layers where
the trace connects. So an
On Sun, Sep 12, 2010 at 03:40:24PM -0400, DJ Delorie wrote:
With flex cable, top and bottom aren't limited to one layer each.
Aren't they?
No. Different areas of the cable may have extra layers or pcbs
attached, changing the number of layers in that area. So one drawing
layer
On 09/12/2010 03:17 PM, Windell H. Oskay wrote:
On Sep 12, 2010, at 10:35 AM, Bob Paddock wrote:
Well, a both-sides silkscreen layer makes little sense.
Actually it does make sense. Think about a transformer with through-hole pins.
You want the top silk to show the courtyard, for
At 04:06 PM 9/12/2010, you wrote:
Bigger??? Why do you need an annulus on an inner layer that doesn't
connect to a trace?
Depending on the fab technique, you may need an annulus just to fill
the gap between fr4 layers so that the electroplating is reliable.
Either that, or you need to keep
On Sun, Sep 12, 2010 at 01:56:43PM -0400, DJ Delorie wrote:
http://download.wpsoftware.net/code/pcb/layer.h
I would add a LayerPos to each Layer, and store the Layers separately.
Okay, here is the structure: attached to the PCB is a physical layer stack.
This has a well-defined stacking
On Sep 12, 2010, at 12:29 PM, Andrew Poelstra [1]as...@sfu.ca wrote:
On Sun, Sep 12, 2010 at 01:56:43PM -0400, DJ Delorie wrote:
Alright, we'll allow a top and bottom layer group.
With flex cable, top and bottom aren't limited to one layer
each.
Aren't they? All layers
On Sep 12, 2010, at 1:49 PM, Rick Collins wrote:
At 03:42 PM 9/10/2010, you wrote:
On Sep 10, 2010, at 1:01 PM, DJ Delorie wrote:
I figure we need each layer to specify:
* type (copper, silk, mask, anti-copper, keepout, etc)
There are no types, there are only properties.
The
And I think the only way to do ... in a non-kludgy way
Yet another example of you automatically putting down any idea that
isn't yours. Please stop that. Please consider the possibility that
someone might come up with a better (or even equally good) idea than
yours. Constructive criticism is
On Sep 12, 2010, at 7:53 PM, DJ Delorie wrote:
And I think the only way to do ... in a non-kludgy way
Yet another example of you automatically putting down any idea that
isn't yours. Please stop that. Please consider the possibility that
someone might come up with a better (or even
Thinking about drills...
If a cutout is a property of an insulating layer, the a drill through
the whole PCB is really a composite of 2N+1 drills through N insulating
layers and N+1 conductor layers.
That seems kludgy to me. Drilling is a single operation, why do we
have to represent it as
On Sun, Sep 12, 2010 at 11:09:25PM -0400, DJ Delorie wrote:
Thinking about drills...
If a cutout is a property of an insulating layer, the a drill through
the whole PCB is really a composite of 2N+1 drills through N insulating
layers and N+1 conductor layers.
That seems kludgy to me.
...but your number of sub-composites grows exponentially. In
theory, whatever the lowest-level composite is, your sub-composite
set is the power set of that!
No, because fabs can't drill that way. You can't have a copper layer
that's part of two separate sub-assemblies before those
Hi all,
We use Cadence Allegro at work, and how they implement keepouts may be
interesting. There are several non-copper layers that are used to control the
keep outs and keep-in. In this tool the keep in / keep out is related to how
courtyards are defined.
Each library symbol (called a
On Sun, Sep 12, 2010 at 11:49:33PM -0400, DJ Delorie wrote:
...but your number of sub-composites grows exponentially. In
theory, whatever the lowest-level composite is, your sub-composite
set is the power set of that!
No, because fabs can't drill that way. You can't have a copper layer
but we've still got a user-interface problem.
We're used to that.
So what happens for those users?
They get exactly one composite, which ends up acting just like what we
have today - one outline, one set of drills, all copper/insulator are
on the one plain-built board.
In our previous
Peter Clifton wrote:
Yes, indeed.. magic silk (and other) layers should probably go
and die.
Please do. My local list of warts and rooms for improvement contains
many complaints about things that can't be done with silk. Worst of
all: You can't selectively print top-silk and bottom-silk like
Peter Clifton wrote:
Just how useful is anti-copper?
I'd use it for text in copper (less space demanding than regular,
positve text). Anti-text in mask would be neat, too. It is even less
space hungry. Letters look fine if the exposed copper surface is HAL or
even better, gold plated.
Real
On Sep 11, 2010, at 1:28 PM, kai-martin knaak wrote:
Peter Clifton wrote:
Yes, indeed.. magic silk (and other) layers should probably go
and die.
Please do. My local list of warts and rooms for improvement contains
many complaints about things that can't be done with silk. Worst of
On Sat, Sep 11, 2010 at 02:18:09PM -0600, John Doty wrote:
On Sep 11, 2010, at 1:28 PM, kai-martin knaak wrote:
Peter Clifton wrote:
Yes, indeed.. magic silk (and other) layers should probably go
and die.
Please do. My local list of warts and rooms for improvement contains
On Sat, 2010-09-11 at 21:44 +0200, kai-martin knaak wrote:
Peter Clifton wrote:
Just how useful is anti-copper?
I'd use it for text in copper (less space demanding than regular,
positve text). Anti-text in mask would be neat, too. It is even less
space hungry. Letters look fine if the
(Can someone who uses / has used keepouts on another package
describe
for me how they work, or how you use them?)
In Protel there is a keep-out layer. A object, square, polygon etc, on
that layer prevents traces from being run through that area, either
manually or by the
On 09/11/2010 07:07 PM, Bob Paddock wrote:
(Can someone who uses / has used keepouts on another package
describe
for me how they work, or how you use them?)
In Protel there is a keep-out layer. A object, square, polygon etc, on
that layer prevents traces from being
In Protel there is a keep-out layer. A object, square, polygon etc,
on
that layer prevents traces from being run through that area, either
manually or by the auto-router (which sucks so bad I never use it).
Hmmm... Can we have multiple keep-outs for a single copper
On 09/11/2010 06:39 PM, Bob Paddock wrote:
Yes, the 'keep-out' should be per layer. In Protel it blocks all
layers which is frequently what you do not want.
Are you sure? A per layer keep-out doesn't let you automate routing.
a per layer-group keep-out would allow more automation,
Bob Paddock wrote:
Lets not forget to add Blind and Buried Visa to the Wishlist.
yes, please!
This is one of the few features where eagle is in the lead.
---)kaimartin(---
--
Kai-Martin Knaak
Öffentlicher PGP-Schlüssel:
http://pgp.mit.edu:11371/pks/lookup?op=getsearch=0x6C0B9F53
On Sat, Sep 11, 2010 at 7:55 PM, John Griessen [1]j...@ecosensory.com
wrote:
On 09/11/2010 06:39 PM, Bob Paddock wrote:
Yes, the 'keep-out' should be per layer. In Protel it blocks all
layers which is frequently what you do not want.
Are you sure?
Yes.
On Sat, Sep 11, 2010 at 08:57:21PM -0400, Bob Paddock wrote:
How about a keep-out layer with a layer enable list? This keep-out
applies to layers 1,2,4,7,8, and a This keep-out applies to all
layers.
Realistically I've wanted to 'keep-out' Top Layer, Bottom Layer, or All
Layers in almost
My thoughts were that each drawing layer (copper, silk, keepout,
whatever) could belong to a specific physical layer, top, bottom
all inner, or all. I suppose we'd need an all outer for
orthogonality. The top/bottom magic are needed to map footprints on
import, but I suspect things like silk
On Sun, Sep 12, 2010 at 12:24:26AM -0400, DJ Delorie wrote:
My thoughts were that each drawing layer (copper, silk, keepout,
whatever) could belong to a specific physical layer, top, bottom
all inner, or all. I suppose we'd need an all outer for
orthogonality. The top/bottom magic are
I suspect that in the main GUI you'd get a simplified set of options,
like add layers or remove layers to switch from, say, 2-layer PCBs
to 4-layer PCBs, etc. Outer special layers like silk and mask just
exist, but you can enable/disable them.
So most users just see one copper drawing layer per
I apologize in advance if this has already been suggested somewhere in
this thread, but one thing that I've thought about footprints while
reading the thread is keepouts.
Allowing for putting keepouts in the footprints is a very important
addition to whatever gets decided, but what about
I think the term you're looking for is a courtyard - the part of the
PCB's airspace that's owned by the component.
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Most places handle this with the assembly layer.
Of course, this wouldn't be part of DRC, but you'd have to be blind
put stuff overlapping assembly layers and not see it right away.
On Sun, Sep 12, 2010 at 2:40 PM, Jonathon Schrader
jlsch...@jlschrad.net wrote:
I apologize in advance if this
On Fri, Sep 10, 2010 at 01:00:34AM +0100, Peter Clifton wrote:
Gah, you perhaps saw my comments on geda-dev about that. I've got half a
mind to bulk rename as appropriat:
max_layer - max_copper_layer
OR- max_group
They happen to be the same number, but the context is different
Having said that, I'd do you one step further, and move /all/ the
layers into their own list structure. Each layer would have flags
set to indicate if it was a copper, silk, keepout or virtual (ie,
ratsnest) layer. They would also be tagged as being always on top or
always on bottom, in the
On Fri, Sep 10, 2010 at 01:31:48AM +0100, Peter Clifton wrote:
PS.. have you tried any of the GL stuff?
http://www2.eng.cam.ac.uk/~pcjc2/geda/trans_poly.png
http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-1.png
http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-2.png
On Fri, 2010-09-10 at 11:03 -0700, Andrew Poelstra wrote:
It's a PITA to find and read the geda-dev archives, and given the relatively
low volume, I don't usually bother. So I missed your comments.
If you're developing, ask Ales to get you signed up to geda-dev. As you
say, it is pretty low
On Fri, 2010-09-10 at 11:05 -0700, Andrew Poelstra wrote:
On Fri, Sep 10, 2010 at 01:31:48AM +0100, Peter Clifton wrote:
PS.. have you tried any of the GL stuff?
http://www2.eng.cam.ac.uk/~pcjc2/geda/trans_poly.png
http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-1.png
On Fri, Sep 10, 2010 at 01:31:48AM +0100, Peter Clifton wrote:
PS.. have you tried any of the GL stuff?
http://www2.eng.cam.ac.uk/~pcjc2/geda/trans_poly.png
http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-1.png
http://www2.eng.cam.ac.uk/~pcjc2/geda/pcb+gl_3d/pcb+gl_3d-2.png
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