kai-martin knaak wrote:
Karl Hammar wrote:
Running gnetlist -g drc2 on a schematic I get:
input/output -- pwr
input and output are meant to refer to signals. The DRC assumes that
signals should never be connected to power lines. With analog circuits
there is no strict
Tying a digital input directly to a power rail is a bit like doing a
crossword puzzle in ink. You need a lot of confidence to do that in
a real design. I typically use a resistor to pull them up or
down. That can always be hacked, power connections can be hard to
access to modify them.
I am curious about the reasoning for picking values of design
rules. I have not found the assembly houses to be very useful for
this sort of info. They seem to be willing to work with whatever
they are sent and will only give feedback when something causes real
trouble for them.
At 12:51
Just 10 minutes ago I had my 1st talk with my first assembly house.
Guess what! I'm asked to provide rotation data.
In the other mail I'm currently editing, I'm trying to provide
definitions on
where X- and Y-axis is on a part, including where X+ is on mechanically
doubly symmetrical polar
I had to go through all this some time ago and recently I wanted to
iron out all the difficulties so that the assembly house could use my
XYRS file (location and rotation data) directly without
alteration. That ended up being a fool's errand, but I did learn a
few things. IPC has a standard
Mask should be 3 mil away from copper, and slivers should be at least
6 mil wide. That means, if there's less than 12 mil between pads you
go with a gang-opening.
Where did you get these numbers? Did a manufacturer give this as
their capability limit?
Yes. I've found this to be the
On Mon, Sep 27, 2010 at 9:56 AM, Rick Collins gnuarm.2...@arius.com wrote:
They [Assembly houses]
seem to be willing to work with whatever they are sent and will only give
feedback when something causes real trouble for them.
You have to ask, unfortunately. When you send a new project in to a
Andrew Poelstra wrote:
2. We need to have a minor release (1.99za?) to get all the little
crap out of the pipeline before we break everything.
And please, please apply as much of Peter Cliftons pcb version as possible
before you start. It is not only about the openGL and 3D hack for
Folks,
In response to a question on the chat, I've been playing around with pins of
zero graphical length. It turns out that these work quite well. Why would
anyone want such? Well, they allow you to put a connection point on any
graphic, not just the end of a line of a particular style. The
I've done that. I go to the assembly house to test my boards so they
can be repaired before I accept delivery and talk with them all the
time. The only complaint they have is a connector that hangs over
the edge of the board which I can't do anything about unfortunately,
it is due to an old
Kai-Martin Knaak wrote:
And please, please apply as much of Peter Cliftons pcb version as possible
before you start. It is not only about the openGL and 3D hack for visuals,
but a huge bag of little useful improvements. Let's not loose them on the
way.
I hope this won't break the Lesstif
Hi Karl,
El dom, 26-09-2010 a las 11:33 +0200, Karl Hammar escribió:
[snip]
Checking pins without the 'pintype' attribute...
Checking type of pins connected to a net...
WARNING: Pin(s) with pintype 'output': U2:9
are connected by net 'unnamed_net61'
to pin(s) with pintype
The developers are pleased to announce the next stable release in the 0.9
series, version 0.9.3. Icarus Verilog is a mostly complete implementation
of the hardware description language Verilog, as described in IEEE Std
1364-2005. It also includes a number of user requested extensions. It is
John Doty wrote:
Appending the following line to your .sym file will get you started:
P 100 100 100 100 1 0 0
Nice. I added this to the wiki.
http://geda.seul.org/wiki/geda:faq-gschem#is_it_possible_to_have_zero_length_pins
Unattached, it looks like a little red flag, while with a net
kai-martin knaak wrote:
The unconnected pins can be left unconnected, how can I make it
accept that?
I don't know. I put my own nc.sym at pins that are deliberately not
connected. This symbol contains just one pin and no net. However,
DRC still complains, because the generated net is
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