Stefan Salewski wrote:
On Thu, 2010-12-02 at 16:13 -0500, Bob Paddock wrote:
Peter, while all of this sounds great, could we fix the collective
problems that we have now first?
To many of us PCB is used to ship products, preferably today.
Fixing problems is not always fun, especially
On Sun, Dec 5, 2010 at 10:02 PM, Armin Faltl armin.fa...@aon.at wrote:
There are blackboards for freelance engineers, to make a defined feature in
opensource software. This seems a good model of payment to me. The problem
to me in our case is atm:
- the writer of a certain feature is not
Yes, if you were having difficulty with the END_LOOP macro, I can
understand why you didn't venture any deeper into the code.
I just saw the rest of the crap in the header file containing #define
END_LOOP }}
and I'm with Armin on that one, this is pretty ridiculous.
Fixing problems is not
On Mon, Dec 6, 2010 at 3:40 AM, timecop time...@gmail.com wrote:
Yes, if you were having difficulty with the END_LOOP macro, I can
understand why you didn't venture any deeper into the code.
I just saw the rest of the crap in the header file containing #define
END_LOOP }}
and I'm with Armin
Anthony Blake wrote:
Yes, if you were having difficulty with the END_LOOP macro, I can
understand why you didn't venture any deeper into the code.
I had no difficulty finding or understanding the macro, but I have a
huge problem
to work on code, where others deliberately introduce stuff,
Is there a method to automatically apply chamfer to an entire board?
George
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On Mon, Dec 6, 2010 at 4:18 AM, Armin Faltl armin.fa...@aon.at wrote:
Anthony Blake wrote:
Yes, if you were having difficulty with the END_LOOP macro, I can
understand why you didn't venture any deeper into the code.
I had no difficulty finding or understanding the macro, but I have a huge
I don't think a few 'maintenance nightmares' or matching '{' problems
are good reasons for giving up and just doing nothing instead. You
don't have to like the macros and so on to fix bugs, and IMO just
nutting up and dealing with the matching '{' issues
Not using the real braces make style
So I tried adding an Arc statement to my footprint, but I am getting a
syntax error on import. Here is a snippet of the pcb file, that was
generated from my footprint with an Arc inside it.
Element[ soic-08-d.fp U? unknown 0 0 0 0 0 100 ]
(
Pad [-12204 -15000 -12204 -15000
Arcs aren't allowed in footprints. You can overlay rectangular pads
along an arc if you need to.
The footprint I use for fiducials is below. The request from the
assembly house was 1mm pad with 3mm clearance. The board that
assembled my last board did not mention any problems (and the
board
On Sun, 5 Dec 2010 12:54:00 -0500
John Luciani jluci...@gmail.com wrote:
Arcs aren't allowed in footprints. [...]
This begs the question, since arcs can be placed on the silk layer in a
footprint, is there a particular reason why PCB couldn't be tweaked to allow
them on copper layers?
--
Am 05.12.2010 um 18:54 schrieb John Luciani:
Arcs aren't allowed in footprints.
D'oh. Neither me nor my copy of PCB knew that so this rectangle with
rounded corners worked fine:
ElementLine [-46000 -12450 46000 -12450 1000]
ElementLine [-46000 12450 46000 12450 1000]
ElementLine
This is in the silkscreen of the footprint.
Steve
On Sun, Dec 5, 2010 at 10:29 AM, Markus Hitter m...@jump-ing.de wrote:
Am 05.12.2010 um 18:54 schrieb John Luciani:
Arcs aren't allowed in footprints.
D'oh. Neither me nor my copy of PCB knew that so this rectangle with rounded
corners
The problem with this approach is exactly what started off my quest for
the Arc. Namely the autorouter is routing through the keepout space on
the fiducials.
Oliver
__
From: John Luciani jluci...@gmail.com
To:
I don't think chamfering is available. Other related features are
available though:
Mitering is available from Connects-Optimize routed tracks-Miter.
Only works for intersections with one vertical trace meeting one
horizontal trace.
A puller is available from Connects-Optimize routed
On Sun, Dec 5, 2010 at 2:20 AM, Peter Clifton pc...@cam.ac.uk wrote:
On Sat, 2010-12-04 at 11:15 +1100, Stephen Ecob wrote:
branch.. sorry).
[...]
So, a mix of NOT LEAKS, and might be leaks. We need back-traces of the
cases where callers are allocating things repeatedly and not freeing
them.
Anthony Blake wrote:
Any chance, this is going to change?
I'm busy with school work at the moment.. I'll get to it eventually,
if someone else doesn't do it first..
I'll take this as a no.
---)kaimartin(---
--
Kai-Martin Knaak
Öffentlicher PGP-Schlüssel:
On Mon, Dec 6, 2010 at 10:03 AM, kai-martin knaak k...@familieknaak.de wrote:
Anthony Blake wrote:
Any chance, this is going to change?
I'm busy with school work at the moment.. I'll get to it eventually,
if someone else doesn't do it first..
I'll take this as a no.
Yep, thats a no. Most
Hi,
Attached is a fiducial example.
Enjoy!
--
Levente Kovacs
http://levente.logonex.eu
fidu.fp
Description: Binary data
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On Mon, 2010-12-06 at 10:53 +1300, Anthony Blake wrote:
Yep, thats a no. Most people who use PCB prefer a MS paint style
interface where they spend a long time drawing lots of straight lines
by hand, so I can't really be bothered. Good luck with that!
Best wishes,
Anthony
:-[
I must
Stefan Salewski wrote:
Fixing problems is not always fun, especially if one is not really
suffering from these problems oneself.
It is even less fun if the fix is ignored or not liked by the regular
developers. BTDTGNT
---)kaimartin(---
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Kai-Martin Knaak
Öffentlicher PGP-Schlüssel:
On Mon, Dec 6, 2010 at 11:25 AM, Stefan Salewski m...@ssalewski.de wrote:
I must have missed a lot of that postings?
See pcjc2's thread on a futuristic interface.
You may be disappointed that no other people have continued working on
your great router -- I guess the reason is that many of us
Anthony,
I look forward to your hard work, it is very impressive, and reminds
me of the layouts from years ago, where they were taped out and
pretty. None of this manhattan grid.
I know that Adding via's are non trivial for an auto router, with
your topological auto router, will it use a via
Joshua E. Lansford wrote:
I noticed that the refdes_renum does not take note
of the slot attribute of components.
ack.
This is on my list of most useful work-flow improvements.
It is written in java
My experience with utilities written in java is mixed. More often
than not, the
Well that was interesting. The tracks-Miter made it look very sloppy
and the completely hung PCB. Using version 20100929.
George
On 12/05/2010 03:40 PM, Stephen Ecob wrote:
I don't think chamfering is available. Other related features are
available though:
Mitering is available from
On Mon, Dec 6, 2010 at 12:10 PM, Steven Michalske smichal...@gmail.com wrote:
I look forward to your hard work, it is very impressive, and reminds
me of the layouts from years ago, where they were taped out and
pretty. None of this manhattan grid.
Yeah, I love the curvilinear hand layouts in
On Mon, Dec 6, 2010 at 9:28 AM, George M. Gallant, Jr.
ggallant...@verizon.net wrote:
Well that was interesting. The tracks-Miter made it look very sloppy
and the completely hung PCB. Using version 20100929.
look very sloppy - could you be more specific ?
A couple of notes on using the Miter
I've had a tidy up of my branches for the sake of user sanity:
RENAMES:
master - pours
before_pours - pcb+gl --- This is the one you want!
My head-name is pcb+gl, and I've set repo.or.cz to check this branch
out by default when you do:
git clone git://repo.or.cz/geda-pcb/pcjc2.git
If you use (or intend to use) lib dmalloc with PCB you will find the
following useful.
I've uploaded a patch against current heaad to sourceforge, ID
#3129279, described as follows:
PCB supports the use of the dmalloc library as a configuration option.
This patch makes the PCB source code more
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