Hello,
Total gEDA noobie here, but my first encounter with EDA workstations was
about 1983, so I know the vocabulary and the work flow. But I have a
long learning curve to climb in terms of how gEDA does it.
This is probably a FAQ, but after searching the archives I couldn't see
DJ Delorie wrote:
Yes, I get that. I asked my question poorly. There is an attribute
in the symbol that points to the correct pin mapping. I get the concept,
but I don't know where all the ascii lives, and how it should be split
up across various files.
Ah. Set the footprint attribute to
Yes, I've had the same thought. Programs (and other things) that were
named before the days of internet search engines may have a sub-optimal
name in the current environment.
-dave
Hugo Elias wrote:
Hi all,
Has anyone wondered if Pcb might not be the best name
for this program? Googling
DJ Delorie wrote:
No, but gpcb for gnu pcb might.
Although, are we really part of the GNU project? We can't just say
we're gnu! without getting accepted by them first.
Yeah, I was thinking that.
opcb? for Open PCB?
-dave
___
geda-user
So, for this project I'm doing, I wanted a footprint providing a hole
for #4 hardware, with a pad that would clear the corners of a hex
stand-off that is 1/4 inch across the flats.
Of course, being an Old Time Unix Programmer(TM), instead of creating a
trivial 4-line text file with vi, before
DJ Delorie wrote:
Is this feature planed for future, if not currently implemented?
It's not implemented, and we'd like to have it but have no immediate
plans to add it.
Has anyone thought about doing a footprint rotating utility? Of course,
it would lead to library explosion, but as an
Bob Paddock wrote:
What I always wonder about with these tools, or similar X/Y machines is why
no one ever optimizes the travel to save time. Seems like it should be simple
mater of sorting the vectors? Instead the machine goes at random from
place to place.
Probably not so simple.
Dave McGuire wrote:
On Oct 4, 2006, at 6:48 PM, Robert Fitzsimons wrote:
Do you still have the code? would you share? I have an old plotter and
learned some HPGL years ago, even wrote some simple plotting tools.
Now I
would use HPGL as an example exporter with the scriptable PCB project.
DJ Delorie wrote:
I'm guessing it's using a variant of HPGL embedded in a PCL data
stream. I.e. a mode switch between languages. The PCL5 spec has
commands for this.
That would make sense for driving the laser. It is just an X-Y device.
The laser can be turned on and off, of course,
simple question:
I have a situation where I want one pin on the schematic symbol to get
netlisted to two pins on the footprint. IOW, both physical pins must be
connected to the same net, but it is PCB designer's choice as to how.
(The exact situation is duplicated power rails on a header.)
John Griessen wrote:
Dave N6NZ wrote:
Short them with a net, and make sure your footprint has the extra pin
numbered to expect it's own connection to the net.
I find that statement a little confusing... but it is going to a
standard header footprint, so the footprint will have pin
In fooling with various practice layouts (partial layouts, actually) I
think I have the basics of polygons and rectangles sorted out. Now I'm
wondering about the practicalities is adjoining poly's.
Here is the situation: In my design, there wants to be a polygon patch
of analog ground that
Thought I just saw a thread on this topic, but I deleted the whole works
and can't find it in the archives.
I'm trying to reconcile a data sheet for a TSSOP-20, 0.65mm lead pitch
package with PCBexpress's design rules. The problem: 26mil l.p. and
10mil pad width leaves 16mil btw pads. The
Thanks, very helpful. That seems like the correct interpretation of
their use of the word swell.
-dave
DJ Delorie wrote:
Below a certain pitch, mask becomes almost useless, because the solder
will bride from pin to pin anyway. The challenge boards are 0.50m and
0.40mm pitch and neither has
the soldermask to be at least 8mills wide. The issues has
to do with alignment tolerences. Soldermask put on with a stencil has
worse tolerences the soldermask applied with a photo imagable process.
Steve Meier
Dave N6NZ wrote:
Here is the rule in question from PCBexpress web site:
Solder mask swell
Ales Hvezda wrote:
This one is better than the last .. enjoy!
and
This is some god stuff :)
Well, that sounds good, but is... how can I say this?... light on
specifics. :-)
Is there some place I can easily see a change log without having to
download the tarball? Basically, I'm
Off topic I know, but I need a pointer. Is there a decent FOSS 3D CAD
program that will create STL files for simple parts?
-dave
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Is there any free (as in speech) software that will convert gerber to .dxf?
Reason: I have access to a laser cutter through the TechShop and am
trying to work out a path to cut el-cheapo solder paste screens in
acetate sheet or similar material. I tried the path of creating a
PostScript
DJ Delorie wrote:
It's common to want to move PCB layouts into cad for chassis layout
work. What would be involved in giving PCB this feature?
Write an export HID. It's the same way we export gerber and
postscript.
.dxf would be very cool... but having been fooling with .dxf lately, i'd
hhmmm... QCAD only opens .dxf, pstoedit only opens PS, not EPS. But I
guess if I don't do 'fill page' I should be OK.
-dave
DJ Delorie wrote:
PCB is free, and it'll export .eps.
Oh, right. EPS, not PS output. Both are Postscript, and thus
rasterized, but the PS output may be scaled to fit
John Griessen wrote:
There are a couple of python cad programs with open source to look at
that do some .ps and .dxf output, and no importing. Pythoncad and cadvas
source code might be helpful in learning curve to get PCB to write out
.dxf.
From an overall work flow perspective, it might
DJ Delorie wrote:
The advantage of going pcb-dxf and not gerber-dxf is that you only
have to worry about supporting the data we have, which is
significantly simpler than trying to support a generic gerber file.
Oh yes, I hear that. What's easy and what's most generally useful
seldom overlap.
DJ Delorie wrote:
After I verify a footprint I move it to a released for production
directory.
I've started grouping my library into vetted and not vetted, with
the vetted ones being the ones that have been fab'd and produce
working boards.
I suppose I could add more steps, like paper
Very interesting thread. Taking it a little off topic...
A question that has come up in the past is the idea of importing data
from a mechanical package to get board outline, etc. As it turns out,
I'm working on another project where I have been using dxflib, which is
a C++ dxf reading
Can you point me at some code to follow? Like perhaps a working plug-in
that I could gut and use for a skeleton?
-dave
DJ Delorie wrote:
Write a plug-in that reads the dxf and adds the items to the existing
outline layer.
It's far easier to just call the internal API than to create a .pcb
[EMAIL PROTECTED] wrote:
Dave N6NZ wrote:
If other people would find that functionality useful, I will look into
it.
It would seem handy to be able to import dxf files for certain hardware
modules, assemblies that mount onto a pcb and for some connectors.
What does import mean
.
-Oorspronkelijk bericht-
Van: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] Namens Carlos Nieves Ónega
Verzonden: woensdag 7 februari 2007 19:12
Aan: [EMAIL PROTECTED]; geda-user
Onderwerp: gEDA-user: Re: dxf?
El mar, 06-02-2007 a las 16:31 -0800, Dave N6NZ escribió:
Let me be clear about my
a study of the best reflow gizmo and found it to be $30
skillet!
gene
- Original Message -
From: Dave N6NZ
Date: Friday, March 2, 2007 1:11 pm
Subject: gEDA-user: home made hot plate
To: gEDA user mailing list
Seeing DJ's hot plate photo brought to mind a link I once saw,
where
al davis wrote:
Regardless of preference, at some time everyone will be
confronted with something else. Whether you like it or not, it
is important to be able to cope with it.
Gee... in the old days, that was simply assumed. Let's see...
My career as measured by operating systems on
What is the easiest way to create thermal vias? Not a via with a
thermal relief -- I can do that :) .. but a via with no thermal relief
punched into polygons on both sides of the board that ends up getting
filled with solder to help create a large thermal mass to be used as a
heat sink.
The
joe tarantino wrote:
On 3/7/07, *Peter Baxendale* [EMAIL PROTECTED]
mailto:[EMAIL PROTECTED] wrote:
On Tue, 2007-03-06 at 22:02 -0800, Dave N6NZ wrote:
What is the easiest way to create thermal vias? Not a via with a
thermal relief -- I can do that :) .. but a via
Stephen Williams wrote:
Philipp Klaus Krause wrote:
Is Icarus PAL still alive?
Not especially. No one seems to be programming pals these days,
and using FPGAs instead.
Are there any FPGA's that can be targeted by open source tools? I
realize the place/route issues with the typical FPGA
A while back we had a short discussion about doing cheap solder stencils
in drafting acetate using a laser cutter. As it turns out, I have
access to a laser cutter at the TechShop http://www.techshop.ws/ so I
gave it a try.
I took the postscript check plot for the paste layer, and converted
Was looking for something else and Google turned up this interesting
document:
http://www.jlab.org/accel/eecad/pdf/022pulliam.pdf
It is a presentation by AMD titled Quick and Easy Solder Mask Creation
that has been saved as .pdf.
I haven't gone through it in its entirety, but it looks like
DJ Delorie wrote:
Notably, it argues for rounded-end SMT land patterns. Can pcb do that?
Yes. Use the 'q' key toggle between square and round pins/pads. I
think there's a key binding for all selected pins/pads too.
Is there a flag to do it in the footprint definition?
-dave
DJ Delorie wrote:
Dave N6NZ [EMAIL PROTECTED] writes:
Notably, it argues for rounded-end SMT land patterns.
I think they go overboard in using round. The lands for sot-23 are
circles! Maybe rounded-corner pads, with the radius equal to the
difference between the lead edge and the pad edge
John Griessen wrote:
Dave N6NZ wrote:
Yes, some of them look a little odd. But... the title says Quick and
Easy
How should we decide to break a solder paste mask into smaller sections
to help them out? Larger than ? dimension? I guess this is for
better squeegee results
Steven Michalske wrote:
What rake angle are they applied?
err... u... it's hand-held, so I'd have to say variable
-dave
Steve
On Apr 2, 2007, at 2:52 PM, Dave N6NZ wrote:
professional hand-use sqeegees are very thin, very flexible stainless.
My expensive sqeegee is much less stiff
pcb --version reports:
pcb-bin: 1.99q
Which I admit is way behind CVS. But here is the bug:
The postscript check plot of the paste stencil for rounded end surface
mount pads is not emitted correctly. It appears to be a very thin line.
The gerber appears to be OK. Is this a known erratum?
DJ Delorie wrote:
The postscript check plot of the paste stencil for rounded end
^^
surface mount pads is not emitted correctly. It appears to be a
very thin line.
Seems OK to me. Which specific postscript page are you referring to?
Front
Don't know of one for Linux. But in my experience, a graphical editor
for NEC isn't of great value anyway. The amounts that the wire lengths
are changing while you are tuning antennas is too small relative to the
rest of the structure and to the screen size.
What *is* useful is symbolic
C P Tarun wrote:
When will gEDA start providing support for printed circuits? :)
Tarun
Modified ink printer churns out electronic circuits
* 18:24 18 April 2007
* NewScientist.com news service
* Tom Simonite
A desktop printer loaded with a silver salt solution and vitamin C has
I'm also using Syntech. It's been stable for me.
Since I have access to a laser cutter at a public machine shop, I cut
stencils in 5 mil drafting mylar and sqeegee the solder on, then reflow
in a toaster oven.
-dave
DJ Delorie wrote:
Where do you get your paste? How long is it lasting for
DJ Delorie wrote:
Since I have access to a laser cutter at a public machine shop,
Now that you've admitted that, you're going to have a lot more friends ;-)
Well, I've considered doing an el-cheapo stencil service, but it would
have to be plot-N-go to make it worth while. There are two
L.J.H. Timmerman wrote:
Hi Dave and all,
On Wed, 2007-06-06 at 11:24 -0700, Dave N6NZ wrote:
a) pcb paste layer gerber is directly from the pad layer, and I think in
many cases that lays down too much solder. I haven't experimented
enough to be able to say for sure. I'd like to see
DJ Delorie wrote:
That would be useful. Care to share it?
Attached.
Thanks!
You need cutting arcs, not stroking arcs, right? So each pad needs to
be outlines, offset by half the kerf? Should be easy enough to write
an exporter for that.
Yup. That's it. Just outlines cutting
Steven Michalske wrote:
On Jun 7, 2007, at 9:04 AM, Dave N6NZ wrote:
L.J.H. Timmerman wrote:
Hi Dave and all,
On Wed, 2007-06-06 at 11:24 -0700, Dave N6NZ wrote:
a) pcb paste layer gerber is directly from the pad layer, and I
think in
many cases that lays down too much solder. I
Dan McMahill wrote:
note new thread and change to bottom posting!
On Thu, 2007-06-07 at 16:06 -0400, DJ Delorie wrote:
Shouldn't the file format be forward compatible with a warning? if
an unknown parameter is introduced in the file format, pump out a
warning and continue?
The
DJ Delorie wrote:
Newbie question: Is it possible to rotate a component in increments other
than 90degrees?
In the CVS version of pcb, you can free-rotate the buffer.
Holy cow! So does that mean we can actually do 45 degree SMT parts now?
And the pads are OK? Cool.
-dave
Jeff Trull wrote:
It goes like this:
Composer .cdb file - EDIF - .sym
The EDIF file lives for less than ten seconds and
then /tmp fills up.
EDIF: Every Disk Is Full.
I haven't thought about EDIF in years. I'm sorry to hear it still
exists. I would have thought by now people
DJ Delorie wrote:
Yes, that's a stupid default,
It's not the default in pcb itself, though. Most likely, it's the
template that gsch2pcb uses, which is obsolete and weirdly configured.
Sorry for the late hit on this thread... I've been out of town for a week.
I need a how-to. I've always
Ben Jackson wrote:
On Tue, Jul 24, 2007 at 10:56:14PM +0200, [EMAIL PROTECTED] wrote:
In my board I used static pins (just for better hold with a rot-encoder) as
a
vias. Sadly I didn't figure out how to tell PCB not to complain that as
a
short circuit. Is there a way to prevent PCB
Stuart Brorson wrote:
Therefore, I wonder if I should withdraw the footprint doc and
point to the File Format section of the on-line PCB manual?
N! It's about the only PCB documentation that I regularly use. I
think it is a fine document.
Or
should I simply update the footprint
I've been using 0805 LiteON LTST-S220xxx parts, DigiKey 160-1220-1-ND in
red/org, 160-1218-1-ND in green, other colors available. I like these
because they have very wide angle viewing -- full 180 degrees pretty
much. I don't think there is a bi-color part in the LTST-S220 family,
though.
Hi,
I'm trying to put the gschem-gsch2pcb-pcb-gerbv tool flow onto my
MacBook. Following http://www.ghz.cc/charles/fink/ everything seems to
go smoothly, and pcb and gerbv seem to start up OK. gschem is not
happy, however. The menus are broken pictures, the status box is full of
Tried to
Dave N6NZ wrote:
Most recently read form: ([EMAIL PROTECTED] (build-path geda-rc-path
gschem-darkbg))
Failed to read init scm file [(null)/gschem.scm]
Is this indicative of some environment variable not being set?
-dave
This seems to be the topic of the day (see my earlier posts)
-dave
[EMAIL PROTECTED] wrote:
Howdy guys,
Setting up a new workstation for doing gEDA work on, and am running into
this error:
gEDA/gschem version 1.2.0.20070902
gEDA/gschem comes with ABSOLUTELY NO WARRANTY; see COPYING
Ales Hvezda wrote:
[snip]
Probably parenthesis mismatch in /sw/etc/gEDA/system-gschemrc
Most recently read form: ([EMAIL PROTECTED] (build-path geda-rc-path
gschem-darkbg))
Failed to read init scm file [(null)/gschem.scm]
Tried to get an invalid color: 0
Loading schematic
Steven Ball wrote:
/sw/etc/gEDA/gschem-darkbg exists, but you bring up a good point.
The older, working version of the geda-bundle uses:
(define gedadata (getenv GEDADATA))
(define gedadatarc (getenv GEDADATARC))
(load (string-append gedadatarc /gschem-darkbg)) ; dark background
The
Peter TB Brett wrote:
Please run gschem with the following lines in your gafrc:
(display (string-append gEDA data directory: geda-data-path \n))
/sw/share/gEDA
(display (string-append gEDA RC file directory: geda-rc-path \n))
/sw/etc/gEDA
-dave
Peter TB Brett wrote:
On Thursday 27 September 2007 17:26:34 Dave N6NZ wrote:
Peter TB Brett wrote:
Please run gschem with the following lines in your gafrc:
(display (string-append gEDA data directory: geda-data-path \n))
/sw/share/gEDA
(display (string-append gEDA RC file directory
John Doty wrote:
[1] The (not particularly complicated) definition of the build-path
function
is given in geda.scm.
Which you would expect live where?
/sw/share/gEDA/scheme/
But if it isn't there, the bomb out starts with:
Most recently read form: ([EMAIL PROTECTED] geda.scm)
Finally got around to rebuilding from source, and it seems to have
worked for me, too. At least, gschem comes up and appears normal, and
survived 10 seconds of testing...
-dave
Steven Ball wrote:
First off, I followed your page at http://www.ghz.cc/charles/fink/ to
configure my system
To recap: I have been experimenting with making solder paste stencils
from laser cut drafting mylar. The current implementation of paste
layers is not very flexible. The paste stencils that result from my
current workflow apply way too much solder (for various reasons).
So I've been
DJ Delorie wrote:
The paste layer is built from the pad layer directly, yes. I use the
ps-bloat setting to offset my paste holes,
Please explain this ps-bloat setting, sounds useful.
Search the archivies for multipad or multi-pad.
OK, I will look that up, it sounds related. But there is
forgot to cc list
Dave N6NZ wrote:
DJ Delorie wrote:
Maybe you could write a laser-paste exporter? Then, you could ask the
user for the offset they need, and output whatever language you need
to run the laser directly.
My current workflow is ps - dxf via converter.
But really
DJ Delorie wrote:
My current workflow is ps - dxf via converter.
Then ps-bloat will work for you.
Well, it reduces the pain, but it isn't sufficient to make the problem
go away. I could pick a bloat that helps TQFP's (or pick your pad
family) but still be left with hand editing others,
Bert Timmerman wrote:
Dave,
I guess I'm half way (or better) in writing a dxf HID.
Could we join efforts in some way ?
If I (we?) speed up development of the dxf exporter, DJ and you would
probably not have to tweak anymore ;-)
The dxf exporter is a good idea, but I don't see how
Bert Timmerman wrote:
FWIW, I think we could use the attribute mechanism (as in gschem) to
apply/override stuff to a pin/pad on a specified layer.
An example for pin to show the principle:
snip
Seems like a reasonable approach to the syntax. I don't know enough
about the internals to
John Griessen wrote:
Could a file-wide pad stack handle all cases of using a padstack? I
am thinking
Dave wants to vary the shape of paste layer from place to place...
What I want is simple. For any footprint, it needs to draw a paste
layer that cuts a reliable stencil. I don't need to
Peter TB Brett wrote:
On Monday 15 October 2007 18:10:05 DJ Delorie wrote:
It got me to thinking - maybe some of us could get together and
collaborate on a design? Each offering their expertise and time,
using a central CVS/SVN server to hold the (yay ascii!) design files.
Hmm, I'd
DJ Delorie wrote:
The data structures aren't that hard to understand, it's the code that
manipulates them that's tricky.
While I appreciate knowing that, your comment is 100% content free. It
is a non-clue.
Can't somebody simply say: Go look if file ___ and read ___.? That is
a clue.
It
DJ Delorie wrote:
Imagine, that you have a 431 pin BGA. Would you include 431 times
the same padstack in the footprint? I think one should bother with
the whatever shape, and size of the stencil, copper, mask, paste
layers. Those are just pads. Then we could link pads to a
padstack, and
joeft wrote:
For sanity's sake, let's let a footprint define its pad stacks for its
own pads, rather than trying to maintain a global cache of padstacks.
Then, a BGA footprint would have one here's what my pads look like
and 431 copies of put one here.
Yup. Right answer.
A
Chris Albertson wrote:
Have you looked at Prolog?
Yes, indeed. Quite fluent at one time in the past.
For DRC, I envision a language specific to the problem domain of
specifying DRC rules. It might compile into Prolog, or guile, or
whatever, but the typical user is not going to want to
they like.
Steve meier
Dave N6NZ wrote:
Chris Albertson wrote:
Have you looked at Prolog?
Yes, indeed. Quite fluent at one time in the past.
For DRC, I envision a language specific to the problem domain of
specifying DRC rules. It might compile into Prolog, or guile
Dan McMahill wrote:
From my point of view if libgeda and the scheme binding were
expanded to let you have a really full featured database access via
scheme, you could do all sorts of things. However, many of them may be
specific to a particular person, project or company.
You
I thought I'd try out the batchPCB service from SparkFun (see batchpcb.com)
But... their web page says they insist on getting a back silk gerber,
even if it is empty. So... what's the easiest way to get an empty back
silk?
-dave
___
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DJ Delorie wrote:
I just had an occasion to remove a bunch of SMT parts from a proto
board (so they can be moved to the production board). I used the
hotplate, because many of them had solder under the part, not next to.
What are you using for a hot plate?
The SparkFun site talks about
DJ Delorie wrote:
What's the work around?
Edit globalconst.h change MINSIZE
or use the lesstif GUI, which ignores the min/max settings ;-)
OK, well, I really should to a rebuild. I happened to run into this on
the machine that has the oldest install of PCB.
I'm thinking the same thing. I bought a hand full of cement encapsulated
power resistors at one of the local surplus houses. My plan is to epoxy
them to the back of an aluminum plate, and use a bench supply to supply
power.
-dave
Steven Michalske wrote:
How about an aluminimum plate on top
DJ Delorie wrote:
I think updating the PCB docs is going to be my next thing to focus on
in PCB-land. The existing docs are so out of date, I think it would
be best to just write new ones - especially as I think we need not one
but a couple of separate docs. I've set up a web page here:
DJ Delorie wrote:
2) developer's reference
Why? I see two parts to this: HOWTOs for common types of changes
(like writing a plug-in), and whatever doxygen spits out (eventually).
It's my #2 priority for selfish reasons :)
The source is not very approachable in it's current form.
Peter Clifton wrote:
snip/
We have a problem at CUED with various different formats / types of
gerber, and no means to panelise them effectively.
snip/
The thought occurred to me that gerbv is happy enough reading all of the
above, and all the primitives themselves will probably translate
Stuart Brorson wrote:
This discussion is very prescient. Dan and Julian have been
instrumental in helping me beat gerbv into shape over the last two
weeks. I plan on releasing a new version with 1 1/2 years of patches
applied. I hope to release tomorrow or the next day, depending upon
my
It doesn't look like there is a C-in-a-circle copyright symbol in PCB's
default font, unless I'm missing something. So... am I missing
something? Is there a sensible way to add it?
-dave
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DJ Delorie wrote:
It doesn't look like there is a C-in-a-circle copyright symbol in
PCB's default font, unless I'm missing something. So... am I
missing something? Is there a sensible way to add it?
You need to (1) choose an encoding for it. Best would be 0xa9, which
is where
A while back I located some GPL'd sources for scalable vector fonts. In
the form of C data structures (or easily converted thereto) IIRC.
Anyway... can't quite remember where I saw them, but if I dig around I
might find them again. In theory, somebody could write a C program to
turn those
TrueType (and possibly other)
fonts in files.
-Dave
On Nov 27, 2007, at 4:58 PM, Dave N6NZ wrote:
You know, it may have been freetype that I was thinking of.
-dave
Dave McGuire wrote:
It should be fairly trivial to integrate freetype into PCB for
font management. It looks
PolyFonts -- that's what I was thinking of.
http://gameprogrammer.com/polyfonts/polyfonts.html
Has stroke, outline, and polygon fonts available under various licenses.
Seems to me that the stroke fonts and associated API should be
relatively easy to integrate. The polygon fonts are made up
This is great! I'm glad to see gerbv is being actively developed again.
Will do my part by downloading and testing.
Thanks to the team!
-dave
Stuart Brorson wrote:
Hello!
This is to announce the fourth release in the stable branch of
gerbv, 1.0.3.
This release represents a point
Or at least can we name them something less obnoxious, or tuck them away
where I never, ever have to see them again in ls or accidentally include
them in a wild card again? The current .sch~ system causes too much
clutter for even my trivial projects, I'd hate to see what it does on a
project
?dave
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good point.
Steven Michalske wrote:
Pain in my ass, temporary auto backups belong in /tmp
On Nov 29, 2007, at 11:54 AM, Dave N6NZ wrote:
Or at least can we name them something less obnoxious, or tuck them
away
where I never, ever have to see them again in ls or accidentally
hmmm... pcb reports itself as: 20070912, the compilation date would seem
to indicate that I must have grabbed a fink package or something.
Anyway... printed to stderr:
unknown action `FreeRotateBuffer'
So I guess this build doesn't have free rotate? Is that newer than
September?
DJ Delorie
Peter TB Brett wrote:
On Thursday 29 November 2007 19:54:54 Dave N6NZ wrote:
Or at least can we name them something less obnoxious, or tuck them away
where I never, ever have to see them again in ls or accidentally include
them in a wild card again? The current .sch~ system causes too much
I think you are looking for hide -- position the cursor over the
element, and hit 'h', and it will hide the refdes. That is exactly what
I do for hardware.
-dave
Ben Jackson wrote:
I don't really want to have my mounting holes labelled with silkscreen,
but neither do I want to simply
Is there a reason why PCB's DRC pops a modal dialog for every violation
and refuses to move forward? That is... ummm tedious...
Would it be difficult to re-engineer DRC to operate in a batch mode?
What I would like to see is a new DRC reports window that all of the
violations are posted
DJ Delorie wrote:
Is there a reason why PCB's DRC pops a modal dialog for every violation
and refuses to move forward? That is... ummm tedious...
Because nobody had change it yet. We've talked about creating a drc
layer that's populated by the DRC engine and then managed through the
Randall Nortman wrote:
On Mon, Dec 03, 2007 at 10:07:23AM -0800, Lope De Vega wrote:
I'm trying to build a circuit with a cp2102, which has
0.5 mm between pins' center (actually 0.2mm between
pins). It is a qfn-28 package.
I have never played with toner transfer schemes,
Ditto for me...
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