I have some analog circuits in gschem that I want to layout in the
magic vlsi tool. Is there a good way to go from gschem to magic?
For example it would be nice to generate transistors automatically
(give w, l, and m) and then add port names for S,D,G,B. Likewise it
would be nice
-user@moria.seul.org
Sent: Sun, August 1, 2010 7:20:28 PM
Subject: Re: gEDA-user: gcshem to magic
On Aug 1, 2010, at 12:19 PM, Oliver King-Smith wrote:
I have some analog circuits in gschem that I want to layout in the
magic vlsi tool. Is there a good way to go from gschem to magic
/02/2010 11:47 AM, Oliver King-Smith wrote:
OK
So I am trying to generate a netlist for magic (I know this is not
quite gEDA), but I can't find any documentation on magic's netlist
format. Does anyone know what the format is.
It looks like it a net follows
I am trying to get some rules programmed into my magic tech file. In
particular I want to require metal to encompass the vias by 2um if the
metal is wide metal (10um x 10um). Otherwise I only need to
encompass the vias by 0.8um. Does anyone know how to specify this in
the drc
__
From: John Griessen j...@ecosensory.com
To: gEDA user mailing list geda-user@moria.seul.org
Sent: Sat, August 14, 2010 10:15:38 AM
Subject: Re: gEDA-user: edge4way rules in magic
Oliver King-Smith wrote:
I am trying to get some rules programmed into my
I am not sure what is the best way to handle multi-page schematics with
gschem.
I have schematic on one page where I have connected the power to VCC
and GND symbols. I have connected the non power inputs and outputs to
Input/Output Generic symbols.
So imagine I want to just hook
I may be opening up a can of worms here, but I think it makes sense to
have standard symbols for power rails in the sub schematics.
Admittedly this is not hard to create within gschem.
I know there has been some discussion about not having the power pins
on the schematic for
I am using ltspice as well
__
From: kai-martin knaak k...@familieknaak.de
To: geda-u...@seul.org
Sent: Tue, August 17, 2010 4:48:59 PM
Subject: Re: gEDA-user: Multiple pages
Oliver King-Smith wrote:
I have
Al,
I am under the probably incorrect impression that LtSpice is actually a
better than ngspice and gnucap. What do you think the benefits are
gnucap vs Ltspice?
Oliver
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The free FPGA compilers won't help much for an ASIC because they use
the internal structure of the FPGA when compiling VHDL or Verilog.
This doesn't exist on the ASIC.
Oliver
__
From: Peter Clifton pc...@cam.ac.uk
I am extending gnetlist and I dislike scheme. To work around this I
wrote a little program in C++ to do the heavy lifting and I am trying
to call it from my scheme extension to gnetlist.
I wrote the following function in scheme:
(define magic:write_nmos_fet
(lambda (w l m)
mailing list geda-user@moria.seul.org
Sent: Mon, September 6, 2010 12:22:31 PM
Subject: Re: gEDA-user: gnetlist quitting after execl call
On Sep 6, 2010, at 1:08 PM, Oliver King-Smith wrote:
I am extending gnetlist and I dislike scheme. To work around this I
wrote a little program
after execl call
On Sep 6, 2010, at 2:49 PM, Oliver King-Smith wrote:
John,
Ah much improved. I tried using system* but now I don't seem to be
getting my command line arguments. For example both
(system* /sw/share/gEDA/scheme/subfunction (string-append
--m
So I want to auto route a design for my ASIC, and magic is being a
little flakey (It seems it connects some nets together that don't
belong and fail to connect nets that do belong). I was wondering if
anyone has any references on how auto routers get written.
I know some stuff
Can gschem convert schematics to cdl format? I am not sure which
format that is, but a vendor is asking for it.
Oliver
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:32 PM
Subject: Re: gEDA-user: CDL Format
On Sep 15, 2010, at 4:51 PM, Oliver King-Smith wrote:
Can gschem convert schematics to cdl format? I am not sure which
format that is, but a vendor is asking for it.
CDL appears to be a SPICE-like netlist format, so with a little Guile
I think this is a different unrelated file format.
__
From: Thomas D. Dean tomd...@speakeasy.org
To: gEDA user mailing list geda-user@moria.seul.org
Sent: Thu, September 16, 2010 7:49:25 AM
Subject: Re: gEDA-user:
__
From: John Doty j...@noqsi.com
To: gEDA user mailing list geda-user@moria.seul.org
Sent: Tue, October 5, 2010 12:09:05 PM
Subject: Re: gEDA-user: Exporting symbols in gschem
On Oct 5, 2010, at 12:44 PM, Oliver King-Smith wrote
Maciej,
There is a small development script that allows you to drop into a
guile shell on the gEDA website. The shell auto completes so you can
see a list of all available commands. You can also try things live.
I found this very helpful when I was starting out with gnetlist.
Is it possible to create a symbol with two types of slots. For
example, in a 4 OR gates logic chip, one slot type would be the OR
gate, while the other slot type would be the power connections. I see
people typical wire the pins that are not part of a slot to nets, but
that seems
, Oliver King-Smith wrote:
Is it possible to create a symbol with two types of slots. For
example, in a 4 OR gates logic chip, one slot type would be the OR
gate, while the other slot type would be the power connections. I
see
people typical wire the pins that are not part
I am coming from the Eagle world, and I am trying the gEDA world for
the first time. In Eagle you don't need to think solder masks vs pad
sizes, or other such details. They were pretty much hardwired in the
program. Is there a good tutorial / reference documentation for
I am trying to place down some fiducials with a 40mil round copper
center with 88mills of clearance (from the center of the fiducial) and
80 mils of solder mask. I am doing it by using the following command
inside my footprint file.
Pad [-13188 -15000 -13188 -15000 4000 4800
Is there a way to protect the fiducial? For example I could attempt
to ring it with copper.
Oliver
__
From: DJ Delorie d...@delorie.com
To: gEDA user mailing list geda-user@moria.seul.org
Sent: Sat, December
So I tried adding an Arc statement to my footprint, but I am getting a
syntax error on import. Here is a snippet of the pcb file, that was
generated from my footprint with an Arc inside it.
Element[ soic-08-d.fp U? unknown 0 0 0 0 0 100 ]
(
Pad [-12204 -15000 -12204 -15000
The problem with this approach is exactly what started off my quest for
the Arc. Namely the autorouter is routing through the keepout space on
the fiducials.
Oliver
__
From: John Luciani jluci...@gmail.com
To:
I am sorry if this is a retarded question, but is there a way for
gschem to see new created symbols (placed in a local symbol directory)
without restarting?
Oliver
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Brilliant! Just what I needed
Oliver
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From: DJ Delorie d...@delorie.com
To: gEDA user mailing list geda-user@moria.seul.org
Cc: geda-user@moria.seul.org
Sent: Mon, December 27, 2010 11:30:41 AM
Subject:
Being lazy I am importing footprints other folks kindly made for pcb.
Unfortunately, I am not very trusting, so I want to check they are
correct.
I can measure the size of stuff using gerbv (there may be a better way
to do this in pcb), but I can't tell if the right pin numbers have
@moria.seul.org
Sent: Thu, December 30, 2010 12:27:28 AM
Subject: Re: gEDA-user: Seeing pin numbers in PCB
On Wed, Dec 29, 2010 at 11:48:00PM -0800, Oliver King-Smith wrote:
Being lazy I am importing footprints other folks kindly made for
pcb.
Unfortunately, I am not very trusting
Is there a way of specifying where your local spice files are in the
gafrc file, so gnetlist can pick them up, without giving the full path
for the spice file in your symbol definition?
Or do I do this somewhere else?
Oliver
___
__
From: John Doty j...@noqsi.com
To: gEDA user mailing list geda-user@moria.seul.org
Sent: Thu, December 30, 2010 9:08:48 AM
Subject: Re: gEDA-user: garfc spice files directory
On Dec 30, 2010, at 10:03 AM, Oliver King-Smith wrote:
Is there a way of specifying
I have been having problems with LTSpice simulating some components
from TI. I was thinking of looking at TINA-TI spice program. Has
anyone tried going from gschem to TINA? Which back end are you using
for this?
Oliver
___
geda-user
, Oliver King-Smith wrote:
I have been having problems with LTSpice simulating some components
from TI.
Why, what was not working? LTSpice with wine and Linux?
I was thinking of looking at TINA-TI spice program. Has
anyone tried going from gschem to TINA?
So gschem
j...@noqsi.com
To: gEDA user mailing list geda-user@moria.seul.org
Sent: Sat, January 1, 2011 11:23:18 AM
Subject: Re: gEDA-user: TI-TINA Spice and gEDA
On Jan 1, 2011, at 11:53 AM, Oliver King-Smith wrote:
I was having some problems with simulating a circuit with a
floating
I am continuing to have problems with multi part symbols. Here
I have an op amp define as thus:
v 20100214 2
L 200 800 200 0 3 0 0 0 -1 -1
L 200 800 800 400 3 0 0 0 -1 -1
T 700 800 5 10 0 0 0 0 1
device=SUBCIRCUIT
T 600 1100 5 10 0 0 0 0 1
slot=1
T 600 1300 5 10 0 0
I am trying to use the generic-power.sym in my schematic. I am
setting the net attribute to 5VA (for 5V analog). I was hoping this
would make all the nets with such a symbol. When I try to run gnetlist
with the spice-sdb backend I get this error printing out several times.
Got an
I have defined my diode with a model statement
model=Is=1e-22 Rs=6 N=1.5 Cjo=50p Iave=20m Vpk=5 type=LED
This works fine except the spice-sdb backend inserts a model statement
every time it finds one of the diodes. Is there a way to have the
model statement only once.
Oliver
Den 2011-01-03 23:37:23 skrev John Doty [1]...@noqsi.com:
On Jan 3, 2011, at 3:31 PM, Oliver King-Smith wrote:
I am trying to use the generic-power.sym in my schematic. I am
setting the net attribute to 5VA (for 5V analog). I was hoping
this
would make all the nets
What is the point of the command Make Inv Text Vis in gschem, other
than aggravating me. I mean putting next to the Show Hide Inv Text is
just plain mean. And there is no way to change a bunch of stuff back
to invisible if you fail to notice your error. You have to go through
On 01/15/2011 10:52 AM, Florian E. Teply wrote:
Hi folks,
I seem to recall that some guys here use gEDA for chip design. John
Doty comes to mind, but i think there are others too. I'd be
interested
in the workflow as i will have to make up some clever test chips in
the
I looked at Toped quiet a bit and did not think it was as good as magic
yet. I like the idea behind it, and it is much more modern feeling
that Magic, but it is still pretty immature.
Oliver
__
From: Bob Paddock
I extracted back out of
Magic and reran the extract circuit in LTSpice as my LVS checker.
You
can also run a simple LVS in Magic, but I did not find that
entirely
reliable.
I'd like to hear more about this. Are you meaning functional
simulation to decide
on
and dirty fashion. It also lacks any comments.
Having issued my disclaimers, I am happy to post it. How do I do that?
Oliver
Oliver King-Smith wrote:
There is no need to use the C++ code if you are a whiz at
scheme, but I really don't like LISP.
You are not alone :-)
Would you
I am trying to make a symbol with PCB. I followed the directions in
the manual. However, my text objects don't seem to be converting. Is
there a way to convert Text to ElementLines with PCB?
Failing that, is there a way to take some text and auto generate
footprint compatible
I am having trouble getting the alt and ctrl keys to have there
intended effect on OS X. I am running inside of X-Quartz 2.5.1 on OS X
10.6. Does anyone know how to make these key work?
Oliver
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I am trying to figure out the best way to make the drill size for a
footprint I am trying to make. The actual whole is^1/[4]-28 UNF 2A
which is about 1/4 of an inch drill size. What is the best way to do
this inside PCB?
Oliver
___
How do I make a whole that size in PCB?
Oliver
__
From: DJ Delorie d...@delorie.com
To: gEDA user mailing list geda-user@moria.seul.org
Sent: Fri, February 4, 2011 8:28:58 PM
Subject: Re: gEDA-user: Drill baby
So the :ChangeDrillSize(SelectedVias,=250,mil) would appear to be
exactly what I want, but it does not seem to change anything.
I tried selecting the vias and entering this, and I tried entering this
when I had the via tool active and then placing a via.
Any thoughts as to what I am
Ahh that helps, and the fact that I was specifying things in 0.01mils.
Thanks
Oliver
__
From: DJ Delorie d...@delorie.com
To: gEDA user mailing list geda-user@moria.seul.org
Sent: Sat, February 5, 2011 10:34:29
I have asked this before, but I don't think I saw an answer. Basically
I would like to create footprints that have text in them, so for
example a transistor might use a Q? Or a connector might use a CONN?
Is there an easy was to do this?
Oliver
So I have a 25 page schematic, and I want to do some rudimentary checks
on it. For example I would like to know if I wired power pins to gnd
pins or only have inputs or outputs on a given net.
What tools does geda have for this type of checking?
What
I have defined a number of symbols with an embedded part # for ease of
ordering. An example of such a part # is
T 700 1000 8 10 0 0 0 0 1
part_number=PMBS3904
This is visible on the schematic (if you turn on invisible text).
However when I run gattrib on the schematic with this
attributs in the schematic.
Therefore, this is a feature.
Stuart
On Tue, 8 Feb 2011, Oliver King-Smith wrote:
I have defined a number of symbols with an embedded part # for ease
of
ordering. An example of such a part # is
T 700 1000 8 10 0 0 0 0 1
part_number=PMBS3904
I am attempting to run the drc2 check with gnetlist. I have checked
each individual schematic separately, and drc2 works fine. But when I
tried to run them altogether I am getting the following crash:
In /sw/share/gEDA/scheme/gnet-drc2.scm:
518: 647 (if (null? list) 0 ...)
, 2011 6:48:02 AM
Subject: Re: gEDA-user: gattrib not showing part_numbers
On Feb 9, 2011, at 7:38 AM, Oliver King-Smith wrote:
It seems like gnetlist could be used to promote an attribute to the
schematic.
No. Gnetlist can't do that kind of schematic to schematic translation
__
From: Oliver King-Smith oliver...@yahoo.com
To: gEDA user mailing list geda-user@moria.seul.org
Sent: Wed, February 9, 2011 7:47:29 AM
Subject: gEDA-user: drc2 crash
I am attempting to run the drc2 check with gnetlist. I have checked
each individual schematic
Is there a way to get the pages symbol (or other equivalent symbol) to
automatically give the other pages it connects to?
Oliver
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I am getting this error when I run the DRC2
ERROR: Pin(s) with pintype 'open collector': U70:2 U70:4
are connected by net 'unnamed_net204'
to pin(s) with pintype 'open collector': U70:2 U70:4
The above statement is absolutely correct, these two pins are both open
10, 2011 4:11:42 PM
Subject: Re: gEDA-user: Pages symbol
Oliver King-Smith wrote:
Is there a way to get the pages symbol (or other equivalent symbol)
to
automatically give the other pages it connects to?
What do you want to achieve?
---)kaimartin(---
--
Kai-Martin Knaak
Does anyone have a PGA100 footprint made already?
I think the footprints are pretty standardized, but in case they are
not, this is the socket I am using:
[1]http://www.mouser.com/ProductDetail/Mill-Max/510-93-100-13-062001/?q
s=kJUkXSjFC7zF7XgyqhSPcw%3d%3d
If I layout the
I am trying to generate a pcb from my schematic using gsch2pcb. It is
generating syntax errors when I try to load it into pcb. The line in
question is ).fp(0603.fp,R229,87K). Here is a snippet of the listing:
#ElementLine[eval(-1*V1/2) eval(-1*V2/2) eval(-1*V1/2) eval(
V2/2)
(...)
type construction.
Oliver
__
From: Oliver King-Smith oliver...@yahoo.com
To: gEDA user mailing list geda-user@moria.seul.org
Sent: Wed, February 16, 2011 7:29:41 AM
Subject: Re: gEDA-user: Strange resistor
Is there a better work around for this rather than making my own
footprints?
__
From: DJ Delorie d...@delorie.com
To: gEDA user mailing list geda-user@moria.seul.org
Sent: Wed, February 16, 2011 7:39:07 AM
I am trying to add a keyboard shortcut for Select by Name - All
Objects.
I located my pcb-menu.res file and tried adding
{All objects Select(ObjectByName) active=have_regex a={Ctrl-N
CtrlKeyn}}
but it doesn't seem to do anything. Does anyone have any suggestions
as to what
Has this been done with the traditional autorouter of PCB?
---)kaimartin(---
_
Yes, I was screwing around to see how it would work. Overall I think
it might be better than the Eagle auto router. Do you recommend using
some else?
Oliver
If you are using the gtk gui, you have to modify the gpcb-menu.res
file. The pcb-menu.res file is for lesstif gui. This might be the
reason for the missing function. The syntax looks right to me.
Brilliant that was the problem! Thank you.
Oliver
I have managed to get my refdes for one component about 7 away from
the component. When I select the refdes I can seem to move it. How do
I get it back to my poor component?
Oliver
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geda-user@moria.seul.org
, February 19, 2011 6:51:50 PM
Subject: Re: gEDA-user: Help I can move by REFDES
On 02/19/2011 09:41 PM, Oliver King-Smith wrote:
I have managed to get my refdes for one component about 7 away
from
the component. When I select the refdes I can seem to move it.
How do
I
I hope this is not considered list abuse, but I am looking for someone
to layout a board in geda's PCB.
The board consists of approximately 100 ICs and associated components.
There is a lot of repetition on the board, and most of the ICs are
single opamps, so the board is not as
Is there a way to get a pin or netlist count for a multi-page schematic
in gschem?
Oliver
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__
From: John Doty j...@noqsi.com
To: gEDA user mailing list geda-user@moria.seul.org
Sent: Sat, March 5, 2011 5:37:37 PM
Subject: Re: gEDA-user: Get a pin or net list count
On Mar 5, 2011, at 12:24 PM, Oliver King-Smith wrote:
Is there a way to get a pin
How do I get the page number to show up in gattrib?
Oliver
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If you give a 1,000,000 monkeys 1,000,000 typewriters, and give them
1,000,000 years to write stuff, one monkey will eventual write a Java
program. The others just produce Perl scripts.
I find perl unreadable. Python, Lua, Java, Ruby, ... I like all those
types of languages.
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