Not around here anymore... The electronics go off to a recycling
facility where the copper and other metals are recovered.
Steve Meier
Karel Kulhavy wrote:
On Mon, Jun 26, 2006 at 10:53:02PM -0700, Steve Meier wrote:
There is also an environmental and a pcb friendly reason to leave copper
Or if this is like TDR... one can spot reflections comming from New
Hampshire, California and I think Florida?
Steve Meier
On Mon, 2006-07-17 at 17:20 -0400, DJ Delorie wrote:
just a Test
It's broken!
Hey! No talking during the test
Looks like fun and I am over in Fremont so I can get over there at least
to see the Exhibits.
Steve Meier
On Thu, 2006-07-20 at 12:09 -0400, al davis wrote:
Is anyone here going to the Design Automation Conference?
http://www.dac.com
___
geda
send me your test1.sym and I will run it for you.
Steve Meier
On Thu, 2006-07-20 at 18:43 +0200, Arvid Rosén wrote:
Ok. I am not sure what that means as I am not familiar with the PCB backend.
What happens if you run in on the top-level file (top.sch), which
includes test.sch as a subnet
to combine the nets.
unnamed_net9Rload-1 Rtop4-1 Rtop2-2
GND Rload-2 Vin-2
unnamed_net8Rtop3-2 Rtop1-1 Vin-1
unnamed_net4Utest/R34-1 Rtop3-1
unnamed_net3Utest/R34-2 Rtop4-2
unnamed_net2Rtop1-2
unnamed_net1Rtop2-1
Steve Meier
doesn't match that symbol.
Even better would be a system similar to slots where the user could pick
the foot print at shematic time and the shematic symbol would switch to
showing the matching symbol.
However, I suspect we can't idiot proof everything.
Steve Meier
I'll take the opportunity
I think there ought to be a functional test... so how about a simple
surface mount amplifier and input/output jacks.
Steve Meier
DJ Delorie wrote:
Is the intent to practice iron soldering, or test oven bake cycles
with solder paste?
Almost missed this comment.
The intent is to see how
the positioning of misplaced nets and then
copy the net schematic into your main schematic.
(* jcl *)
What I do is draw one net then set NET=DATA0 for that net then copy and
past that net + the bus ripper n times. Finally go down the row of nets
and edit each ones attribute.
Steve Meier
would read in the
file and swap the attribute information for the embedded symbols. This
would mean that none of the nets would need to be moved.
Also, I would suggest a move towards XML for these files (new netlist
and swapped pins)
Steve Meier
On Tue, 2006-08-15 at 15:51 -0400, Patrick Doyle
multiple identical gates which can be swapped. e.g.
7400 which has 4 two input nand gates.
pinlabel is used for the viewer as a way of defining what the pin does.
Steve Meier
Kai-Martin Knaak wrote:
Can someone enlighten me on the subtle difference of
* pinlabel
* pinnumber
* pinseq
If I want
ohhh i love the idea... this could be done with a clever hack... the
hack could use google to search for pcb references and geda refferences
and then send the web admin a suggestion for a change to the code.
Steve meier
DJ Delorie wrote:
a hidden link
Search engines are pretty smart
with alignment tolerences. Soldermask put on with a stencil has
worse tolerences the soldermask applied with a photo imagable process.
Steve Meier
Dave N6NZ wrote:
Here is the rule in question from PCBexpress web site:
Solder mask swell is at least .008 larger than copper surfaces to keep
mask off
using is IPC-SM-782A Surface Mount Design
and Land Pattern Standard
Steve Meier
On Sat, 2006-10-21 at 21:42 -0700, Dave N6NZ wrote:
Thought I just saw a thread on this topic, but I deleted the whole works
and can't find it in the archives.
I'm trying to reconcile a data sheet for a TSSOP
Did we pass?
Stuart Brorson wrote:
Sorry for the test...
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You got two puffs of magic smoke from one device and then it starts to work?
In this case I would replace the part. I have had voltage regulators
break a leg and then dump the voltage in into the voltage out taking a
lot of stuff with it.
Steve Meier
DJ Delorie wrote:
I have dead bugged voltage
DJ,
As a short term protection can you stack a series of zenor diodes
together such that if the V out is higher then say 3.7V the diodes kick
on and protect the other stuff?
By the way what is the part? Maybe I can sneak one in on my next digikey
order.
Steve M.
DJ Delorie wrote:
In this case
Be very very afriad of those 01005 capacitors... They seem to be virtual
quantum devices... either you know where they are or you don't. Seeing
as they have very small mass the heisenberg uncertainty principle is
working against you in that they are likely to soon be some where else.
Steve M.
On
My tech got his together other then those 01005's which were apperently
used to fill a couple of pico black holes.
Steve M.
Bob Paddock wrote:
On Tuesday 31 October 2006 13:25, Mark Rages wrote:
And I'm interested in hearing your initial reactions, as well as any
success stories :-)
Am
of one electron) coincide with those actually
observed.
So what was wrong? What occured that proved both theories were correct?
Steve M.
Steve Meier wrote:
Be very very afriad of those 01005 capacitors... They seem to be virtual
quantum devices... either you know where they are or you don't. Seeing
of one electron) coincide with those actually observed.
So what was wrong? What occured that proved both theories were correct?
Steve M.
Steve Meier wrote:
Be very very afriad of those 01005 capacitors... They seem to be virtual
quantum devices... either you know where they are or you don't
I will give you all a couple of clues..
The equation garbled as it may be is the more complex version of E = M*C^2
Next go see who received the Nobel Prize for Physics in 1936.
Steve Meier wrote:
I think I will drop into this group a brief passage fom Heisenberg's Quantum
Theory translated
, at 9:25 PM, Steve Meier wrote:
I think I will drop into this group a brief passage fom Heisenberg's
Quantum Theory translated into English in 1930.
Dirac has set up a wave equation which is valid for one electron
and is
invarient under the Lorentian transformation. It fulfills all
Sure why not here is a link to an individual who built a replica of the
Apollo Guidance System, using discrete components and wire wrap, in his
basement.
http://www.spaceref.com/exploration/apollo/acgreplica/
Steve M.
On Wed, 2006-11-01 at 17:49 +, Michael Sokolov wrote:
Karel Kulhavy
squeeze them into the board size we need.
But as you said Of course a discrete logic wire-wrapped computer is
cool or a bit nutty but more power to the builder.
As far as your project goes I am going to keep an eye on it as I am very
unhappy with my sdsl modem.
Steve Meier
On Wed, 2006-11-01 at 22
http://products3.3m.com/catalog/us/en001/electronics_mfg/electronic_handling/node_T8VK9BXQ8Mbe/root_GST1T4S9TCgv/vroot_8088DWF29Kge/gvel_RQ89J1RQDXgl/theme_us_ehpd_3_0/command_AbcPageHandler/output_html
Bob Paddock wrote:
On Sunday 12 November 2006 02:27, Steve Meier wrote:
To keep the board
of the copyrights to gschem and pcb should state
clearly if they desire that designs created using these tools be forced
to be also released under the GPL. If not then the verbage of the
licenses needs to state clearly how the symbols/land patterns may be
used.
Thanks,
Steve Meier
On Wed, 2006
of the owners of the copyrights need to be
respected. At this time, I suggest that a pardon be issued for old
designs that missued any symbol or land pattern and that the libraries
be organized to avoid such confussion in the future.
Thanks,
Steve Meier
The use of the schematic to generate a netlist and then the pcb is where
a copyright violation might occure.
For those interested in these issues have a look at the following site.
http://www.jenkins-ip.com/serv/serv_6.htm
Steve M.
On Tue, 2006-12-19 at 15:22 -0500, DJ Delorie wrote:
I also
relief as the plane would transfer and disipate the soldering
heat.
Steve Meier
On Thu, 2007-01-11 at 23:52 +0100, David Kuehling wrote:
Hi,
I just noticed that punching a via into a large ground pad does not
produce a non-copper (clearance) ring around the via, as it would do for
vias inside
DJ is absolutely correct.
Steve M.
On Fri, 2007-01-12 at 09:43 -0500, DJ Delorie wrote:
If that's impossible, what would be a good workaround?
Put in a via without a thermal. The only reason you'd need a thermal
is if you're hand soldering it, and even then you'd just need a bigger
iron
I had to read this twice before I realized it did not say the ID is
perpetually attached to the PCB Design Engineer
By registering with http://www.microgrouppcb.com/ , a division of
OZT, the design engineer receives a unique registration identifier
(ID)
administered from the client
Thank you Ben for yet another ;) shameless opening for self promotion
try this document for an understanding of PCB landpatterns and yes there
are scripts available http://www.brorson.com/gEDA/land_patterns_20050129.pdf
Steve meier
Ben Jackson wrote:
I need a PCB element for a Molex 71661-2068
answer was incorrect and so I finally (18 years
later) accept the test results.
These are the places that GEDA belongs in Science and Engineering
Curriculum of a Good University.
Steve Meier
Jorge Ernesto Guevara Cuenca wrote:
Hi everybody,
I'm working with a friend in a some basic examples
To southerners a Yankee is a northerner who visits the south and a damn
yankee is one who stays
Stuart Brorson wrote:
On Sat, 10 Mar 2007, [EMAIL PROTECTED] wrote:
It's great to hear the words yankees and bostonian in the same
sentence :)Go Yankees!!!
*Chuckle*
Warning -- this is wy
geda and pcb don't care if the pinnumbers are numbers or strings. As
long as they are the same.
From a preference point of view I like the pin numbers to match the
component data sheet.
Steve Meier
On Tue, 2007-03-13 at 11:35 -0400, Stuart Brorson wrote:
Change the pin names to numbers
The only time I have noticed a slow start on PCB is when I have large
quantities of polygons. An issue that is independent of file format.
Steve Meier
On Tue, 2007-03-13 at 12:36 -0500, John Griessen wrote:
C P Tarun wrote: The startup time of the version of PCB I have is so huge
Wow DJ, much improved.
To start PCB empty it takes about 2 seconds. To start PCB with our
backplane it takes about 3 seconds. Tested another board with large
quantities of polygons... about 2 seconds.
I retract my last email.
Steve Meier
On Tue, 2007-03-13 at 12:01 -0800, Steve Meier wrote
I am building a board with a couple of 1020 pin BGAs the pins are
normally numbered by a row column system that uses letter for one axis
and numbers for the second axis. Both PCB and gschem use character
strings for the pin numbers and it works well. This implies that both
Y21 and 14 can be valid
Why?
Michael Sokolov wrote:
Steve Meier [EMAIL PROTECTED] wrote:
And while I am at it. I would like to see all of the geda and pcb text
files get converted to xml.
I would have to fork if this were ever done.
MS
___
geda-user
I really am interested in why or why not going with XML? So a few more
details would be nice. Also, which office suite do you use? I assume it
isn't open office which uses xml as its basis.
Thanks,
Steve Meier
Michael Sokolov wrote:
Steve Meier [EMAIL PROTECTED] wrote:
Why
M.
On Wed, 2007-03-14 at 20:03 +, Michael Sokolov wrote:
Steve Meier [EMAIL PROTECTED] wrote:
I really am interested in why or why not going with XML?
How would I use XML with punched cards or paper tape?
So a few more details would be nice.
OK, here are a few more details
On Wed, 2007-03-14 at 20:03 +, Michael Sokolov wrote:
But I have chosen the 1970s technology, philosophy and
paradigm. *HAVE CHOSEN* are the operative words.
Does this include only 1979 and earlier components?
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and green. All except the
hierarchy-disabled are used for generating boms.
Steve Meier
On Thu, 2007-03-15 at 17:38 +0100, Philipp Klaus Krause wrote:
I'm creating my first schematic using gschem (previously I schematics
were in my head or on paper only and I only used pcb to create the pcb
I always ignore the netname attribute.
By the way that pull down list is derived from the file system-gschemrc
which in my instalation is in /usr/local/share/gEDA.
Steve Meier
On Thu, 2007-03-15 at 18:40 +0100, Philipp Klaus Krause wrote:
Steve Meier schrieb:
Philipp,
Standard gshem
format or other does the job and has the parsers
Steve Meier
On Thu, 2007-03-15 at 15:10 -0400, Ryan Seal wrote:
DJ Delorie wrote:
Good to know. Should we put up a little list on the gEDA home page
where the developers, contributors and users of gEDA can state if they
are pro or con XML
On this I absolutely agree. Requirements then solution not the other way
around.
Thanks,
Steve M.
On Thu, 2007-03-15 at 15:35 -0400, DJ Delorie wrote:
I am not saying it is broke I am saying it lacks capabilities that I
need (and by comments on why geda isn't used more in universities i
Learning PCB layout doesn't take that long if it has a reasonable GUI...
opps sorry, right, no guis for you ;)
Steve M.
On Thu, 2007-03-15 at 20:44 +, Michael Sokolov wrote:
Dave McGuire [EMAIL PROTECTED] wrote:
I remember back in the good old days when it was considered a
good
How about a hid similar to nethack?
Steve M.
On Thu, 2007-03-15 at 17:12 -0400, DJ Delorie wrote:
Learning PCB layout doesn't take that long if it has a reasonable
GUI... opps sorry, right, no guis for you ;)
I thought of doing a DJGPP-based (DOS) gui, but that won't work on an
ASCII
John,
Keep this up and we are not only going to think you are paying attention
but that you are taking notes as well.
Steve Meier
John Griessen wrote:
John Griessen wrote:
So, What do you want?
The gschem gnetlist PCB gsch2pcb gattrib gerbv wants mentioned
recently and needing discussion
do you want?
The gschem gnetlist PCB gsch2pcb gattrib gerbv wants mentioned
recently and needing discussion are:
Steve Meier:
1) hierarchical data and file structures (xml or other)
2) an integrated hierarchical netlister
3) use of a better supported scripting language
4) a method
DJ Delorie wrote:
Did I mention the ability to cut out areas of
layers such that I can resese components into lower layers?
Assuming you know a fab that can mill layers before assembling
them... is that what you're talking about? That would mean having
elements and pads on layers
DJ Delorie wrote:
From PCB, I would like to seperate the hierarchy from the rest of
the refdes. I would like to be able to layout a hierarchical
section. I would like to be able to save that section as a seperate
collection. I would like to be able to paste a copy of that section
into a
One practical solution for very small parts is to hid the refdes on the
board but make a large assembly drawing that has them.
Steve Meier
DJ Delorie wrote:
S2/S2/L1 S2/S2/C1 and S2/S2/U1
is the RenumberBlock funtion capable of this?
It currently pulls the last string of digits
go look in your /tmp directory for unintentional back ups
Mikael W. Bertelsen wrote:
On Sat, Mar 17, 2007 14:01, DJ Delorie wrote:
If you edit the .pcb file and remove all the Rats[] entries (they're
all at the end) it will at least load. However, all the layer
information is missing,
Any standard is better then none?
With that Idea in mind and a short story about a company for whom I once
worked where i found that some one had repaired a board by arbitrarily
replacing a component with another and their critical thinking seemed to
be as long as it had the same number of pins
Jeremy,
Create a polygon around your via. Make sure you have the polygons layer
active. Now use the therm tool to click on the via.
Steve M.
Jeremy Pedersen wrote:
Ok, so the solder mask is a coating, and if I choose I could simply
order a board without one. I suppose the advantages would be
Hey, cut out the noise. I was sleeping.
On Wed, 2007-03-28 at 11:26 -0400, David Kerber wrote:
I haven't had a message show up on this list since Monday. Did it really go
that quiet all of a sudden, or have I not been receiving what I am supposed
to receive?
Dave
Simulations and physical layouts are dangerous. If you have anything
more than schematics and you might have to demonstrate feasability and
functionality.
Steve M.
On Thu, 2007-03-29 at 14:47 -0400, al davis wrote:
On Thursday 29 March 2007 14:45, al davis wrote:
n Thursday 29 March 2007
of us to
each do 90 symbols over the course of a year.
Steve Meier
On Fri, 2007-03-30 at 13:30 +0100, Peter Clifton wrote:
On Thu, 2007-03-29 at 23:59 +0200, Alessandro Baretta wrote:
[snip] But it has features I need and cannot do without: a full
standards compliant library of IEC
On Fri, 2007-03-30 at 18:05 +0100, Peter Clifton wrote:
I've no idea what the scope of the IEC standard is. Standard electronic
components appear to be covered, as do control system components. We'd
need people familiar in various fields to submit symbols (or
descriptions). Assuming the
DJ Delorie wrote:
That clock advances one *day* at a time.
I am going to a commune in Vermont, and will deal with no unit of
time shorter than a season.
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slot=2.
Best Wishes,
Steve Meier
Craig Niederberger wrote:
Could someone please explain how to use slot= slotdef= in tragesym
for symbols with multiple identical components in a symbol/chip?
Thanks super in advance,
Craig Niederberger
Way back in the winter of 1985 (i think). Knoxville TN hit a low of -25
F which was more then one of the bank clock/thermometers could handle.
The thermometer was display 107 F.
Showing my usual level of sanity, I went off to North Carolina for some
Ice climbing.
Steve Meier
On Wed, 2007-04-18
How does a Theremin differ from a pickup on an electric guitar?
Steve M.
Ales Hvezda wrote:
Hi,
Sorry for the OT post, but this at least _one_ theremin fan here
that might find this somewhat interesting. There's a radio show on
NPR (National Public Radio) here in the USA called ... Open
seem to be on the right tract.
Steve Meier
Ben Jackson wrote:
I created this for LT1764A and friends, it's a DD5. This is exactly their
recommended footprint, plus an outline I made up. It's very tight to the
part, more so than some I looked at on professionally made boards using
the same
Ben Jackson wrote:
On Fri, Jun 01, 2007 at 09:47:42PM -0700, Steve Meier wrote:
I don't see anything inherently wrong. But it is probably a little
dated. Were you using my doc?
Yes, I was using one updated by Stuart Brorson.
Using sub mill capabilities is needed as you move
week.
Steve Meier
L.J.H. Timmerman wrote:
Hi Steve and all,
So if I understand this correctly, you are asking for someone to write
an exporter for pcb which outputs a file with XY-values of pads(pins)
with an ID-reference to be able to check for copper conductivity etc.
and maybe even
, not because
of the altera, in stead the issue is an ethernet chip.
best wishes,
Steve Meier
Stefan Salewski wrote:
Hello,
is it possible and useful to divide a gschem symbol with very many pins
in multiple smaller symbols?
I plan to make a pcb-board with a FPGA chip which has 208 pins
to be in a commercial eda format?
2) Do you need hierarchical Buses?
3) Do you need back anotation?
If you answer yes to any of these then geda/pcb isn't there yet and may
never be. If you would like to discuss your project requirements either
here or more privately don't hesitate to ask.
Best Wishes,
Steve Meier
That is fair.
A lot of the component companies (altera, analog etc) provide patterns
and footprints for the main commercial tools.
However making a symbol isn't that hard (unless its a 1020 pin fpga) .
Steve Meier
Ales Hvezda wrote:
If those are the only three serious limitations, then gEDA
Anne,
I think you can accomplish this now by using a combination of a pin and
a surface mount pad.
Steve Meier
On Tue, 2007-07-03 at 16:06 +0100, anne Vanhoest wrote:
Hello,
As a tread of wishes has started I thought I'd add mine in the list. But
I couldn't do so without first expressing
work that isn't neccessary with commercial tools.
Please, don't think I am running down GEDA that is not my intention.
GEDA is a tool and a tool should be used with an understanding of its
capabilities.
Thanks,
Steve Meier
On Tue, 2007-07-03 at 18:12 +0100, Peter TB Brett wrote:
On Tuesday
that is
incomprehensible or one could split it up into segments that are
meaningfull. Such as a symbol for power, another for configuration, one
or more for each io bank. Believe me we havn't even started.
But you claim it is easy? Demonstrate?
Thanks,
Steve Meier
*
Igor Izyumin wrote:
On 7/3/07
. Connect that pin
then defines which net the rest of the hidden net belongs too.
This works very well. I have a board with a pair of Stratix II Altera
FPGAs up and running right now using this method.
However, I am not using standard geda I am running a custom version.
Cheers,
Steve Meier
Jonatan
then has to check a symbol to see if any of the pins are
vissible and connected to an external net and if so then connect the
rest of the hidden net to the correct net.
Steve Meier
Jonatan Åkerlind wrote:
think your post got stuck in a spam filter somewhere... forwards it to
the list since I
The external net name should over ride the internel net name.
Steve M.
Jonatan Åkerlind wrote:
On fre, 2007-07-13 at 06:10 -0700, Steve Meier wrote:
Jonatan,
You missed my point. One pin from the net is vissible. The other net
pins are hidden thus reducing symbol bloat.
Sorry
my file structures and geda that a scripted front end and back
end would allow easy porting between the two. Plus importing from other
sorces projects might become feasable.
Steve Meier
On Fri, 2007-07-13 at 09:14 -0600, John Doty wrote:
On Jul 13, 2007, at 8:07 AM, Jonatan Åkerlind wrote
I agree. It goes with DJ's idea to have bus pins have multiple pin
numbers as well.
Steve Meier
On Fri, 2007-07-13 at 09:58 -0600, John Doty wrote:
On Jul 13, 2007, at 9:42 AM, Jonatan Åkerlind wrote:
On fre, 2007-07-13 at 09:14 -0600, John Doty wrote:
Sorry if I was unclear, actually got
of io pins.
I think that this type of device can be done in as few as 12 layers
(probably pain staking layout) and in say 16 layers comfortably.
Have fun,
Steve Meier
p.s. my current project uses 1020 pin fpgas and was layed out on 12
layers. One key is to be willing to swap io pins at layout time
How about a picture from the past?
This was a 900 pin fpga where I used via in pad.
http://www.alchemyresearch.com/bga.jpg
Steve Meier
On Sat, 2007-07-14 at 10:41 -0700, Ben Jackson wrote:
On Sat, Jul 14, 2007 at 08:19:34AM -0700, Steve Meier wrote:
p.s. my current project uses 1020 pin
last note, this was done on a much earlier version of pcb and was
only an 8 layer board.
Steve Meier
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Hmmm,
This is an area that writting some code could be very usefull. How about
a limited auto router that takes the bga io traces out just past the
nearest edge?
Steve Meier
On Sat, 2007-07-14 at 11:41 -0700, Steve Meier wrote:
Ben,
I think you have the correct idea.
I would hand route
Harold,
Can you check that again. 45 mills is 1.143 mm.
Thanks,
Steve Meier
On Sat, 2007-07-14 at 15:43 -0500, Harold D. Skank wrote:
Steve,
You're pretty much right about every thing except the pin density.
We're using Vertex 5, with pins spaced at 0.5 mm, pin to pin. This
limits
Hmmm,
How about an unstable distribution where it is guaranteed that nothing
will work? Cool, that is my standard practice.
Steve M.
On Sat, 2007-07-14 at 17:52 -0400, DJ Delorie wrote:
Fedora is meant for cutting edge :) where bug fixes are pushed.
Fedora DEVELOPMENT is for cutting edge.
If you have 25 mils of open space between pads then you can route two 5
mill width traces with 5 mills of clearence on either side and between
which meets the design requirements of my usual fab shop.
Steve M.
Steve Meier wrote:
Harold,
Can you check that again. 45 mills is 1.143 mm.
Thanks
picture was for a 1mm pitch bga. We had a fantastic
yield (almost 100%).
Best Wishes,
Steve Meier
Harold D. Skank wrote:
Steve,
Sorry about that. I checked the Xilinx footprint info and you're
correct, the spacing is 1 mm. Even so, the problem doesn't change, as
we have to use drilled pads
Putting a via in pad isn't necessary you can put the via between pads
and then run your traces under the pads. The via in pad just gives you
better usage of the surface that your device is mounted to.
Steve Meier
Harold D. Skank wrote:
Steve,
Sorry about that. I checked the Xilinx footprint
Looks like i need a remedial course in elementary school math.
make the pads 17 mills (.43 mm) then you have 5.2 mills between the
copper traces and the pads.
Steve M.
Steve Meier wrote:
Harold,
Try this geometry. 1 mm pitch is ~39.4 mills
Make the 2 traces 4 mills make the spacing between
It looks like it is partially working.
Your net list has S2/R2-1 which is one hierarchical level down from
SW1-2.
Is the U?-? the symbol that has the lower level schematic?
Steve Meier
On Tue, 2007-07-17 at 17:04 +0100, Peter Baxendale wrote:
Been experimenting with hierarchical design
be usefull. This doesn't have to be a built in pcb function it
could be a foot print generator capability. An argument for having it is
to reduce the errors caused by humans.
Steve Meier
Ben Jackson wrote:
As I mentioned in an earlier mail, the QFP208_28 footprint I used for
my board I later found
My suggestion would be to just dump the old libraries. Why build new
boards with obsolete land patterns.
Steve Meier
DJ Delorie wrote:
The current resolution of pcb being 0.01 mills which translates to 254
nano meters (~1/4 of a thousandth of a mm) should meet the requirements
for printed
Here, we never ever use them.
Dumping the low resolution land patterns would encourage replacement.
Steve Meier
On Mon, 2007-07-23 at 11:03 -0400, DJ Delorie wrote:
My suggestion would be to just dump the old libraries. Why build new
boards with obsolete land patterns.
Because
I suggest just adding a statement in the documentation and perhaps in
gsch2pcb that using the m4 (or other low resolution) libraries is
deprectated and not recomended for new designs.
Steve Meier
On Mon, 2007-07-23 at 19:10 +0200, Wojciech Kazubski wrote:
I propose to split old (m4) libraries
Britton,
you make one symbol lm324.sym.
for each pin you add a pin sequence.
typically you use the 1st slots pins and add a pinnumber=2 to the pin as
well
then you add an attribute
slot=1:2,4,6,8
then another attribute
slot=2:1,3,5,7
picking a slot at the schematic level substitues the pin
opps that should be a
slotdef=2:2,4,6,8
you might also need
a
numslots=2 in my example
Steve M
Steve Meier wrote:
Britton,
you make one symbol lm324.sym.
for each pin you add a pin sequence.
typically you use the 1st slots pins and add a pinnumber=2 to the pin as
well
then you add
Sure, it is much more fun to watch them vanish on a completed board as
you run to much current through them.
Steve M.
DJ Delorie wrote:
I've been thinking about a PCB Tetris plugin (or possibly it will
have to be a HID change).
I was thinking of a collect-things-by-regex where you
The contrast ratio also has to take into effect ambient light. So unless
the oled absorbes all incomming photons (no reflections) then it isn't
infinite. Ok maybe in a cave.
Steve Meier
DJ Delorie wrote:
How is this possible, when OLEDs have been shown to last longer than
incadescent
. They made really beautifull displays that
had a life of a hundred hours or so.
Ohh well,
Steve Meier
Bob Paddock wrote:
On Thursday 09 August 2007 21:16, Samuel A. Falvo II wrote:
On 8/9/07, David Griffith [EMAIL PROTECTED] wrote:
The story seems to be that they're all getting out because
gschem is suitable for most schematics, it does have limitations in
certain advanced usages.
Steve Meier
DJ Delorie wrote:
Is gschem suitable?
Yes.
If so, how do I go about downloading it?
http://www.geda.seul.org/download.html
.
Thanks,
Steve Meier
# release: pcb 1.99v
# date:Mon Aug 27 17:09:11 2007
# user:steve (steve)
# host:linux.site
# To read pcb files, the pcb version (or the cvs source date) must be = the
file version
FileVersion[20070407]
PCB[ 60 50]
Grid[1000.00 0 0 0]
Cursor[0 0
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