cool stuff. I'll be checking it out tonight. One thing I've been
wondering about is how one might have some hooks for a technology file if
you wanted to use gEDA for IC type schematics. Where you care about this
is the following:
You're doing a MOS transistor design. For a given
I'm a board designer, not a chip guy, so I may be on shakey ground
here. Please allow me to ask a couple of questions.
1. First off, what kind of netlist are you interested in? If it's a
SPICE netlist, can you just use a .INCLUDE card? If so, there is a
.INCLUDE block symbol which you can
As a more concrete example, suppose you have a standard CMOS process. You
may have only 2 models for transistors. One is NMOS and one is PMOS. If
you take a look at the line in a spice netlist for say the nmos
transistor, it looks something like:
M1 drain_node gate_node source_node bulk_node
