Hi,
The ROM contains predefined micro-code routines for purposes such as apic
interrupt handler (arch/x86/isa/insts/romutil.py).
If you are simulating a full system then basically the interrupt is
triggered by 8254 timer (dev/x86/i8254.py) and when it is triggered the core
fetches
Hi all, I'm trying to run a highly scaled CPU configuration and finding that
individual Gem5 instances are using up to 250GB of memory with my new
configuration!! I'm wondering if anybody knows the most impactful parameters
for memory usage so I can decide what to try and tone down while still
Hi everyone,
I'm attempting to add statistics to the Classic cache's mshr_queue.
There was no stats struct already so I tried to follow the steps in
Bootcamp to add one.
I see the following error though. Could you help?
src/mem/cache/mshr_queue.cc:59:48: *error: no matching function for call
