[gem5-users] Re: Dual load cause xbar busy

Thanks for the clarification. IMP, it is a common scenario for modeling a HPC core, can anyone provide some tips or sample programs? On the other hand, I found that multi-bank is supported in the RUBY cache model(ruby/structures/BankedArray.cc), how is the multi-load implemented in the RUBY model?

[gem5-users] Re: Dual load cause xbar busy

On 2/21/2024 5:04 AM, chengyong zhong via gem5-users wrote: Thanks for the clarification. IMP, it is a common scenario for modeling a HPC core, can anyone provide some tips or sample programs? On the other hand, I found that multi-bank is supported in the RUBY cache

[gem5-users] Re: Issues faced while running STREAM benchmark in SE mode.

Hi Pooja, It looks like an old version of gem5 (considering configs/example/se.py has been moved to configs/deprecated/example/se.py). As you are trying to run an Arm simulation, can I suggest you to use configs/example/arm/starter_se.py instead? Kind Regards Giacomo From: Pooja

[gem5-users] Chiplet Simulation with Gem5

Hi, Does anyone know how to do a chiplet based simulation on the latest Gem5 version with garnet? My basic requirements are: running distributed C++ applications (using multi-threading) on the Gem5 O3CPYU type, having the ability to control the number of cores on individual chiplet dies (even

[gem5-users] Limit debug output to certain instruction address range

Hi, I'm currently experimenting with Spectre on gem5, and I'm dumping debugging output using the O3PipeView flag. However, I get a lot of output for instructions that are not relevant to the attack sequence. I was wondering if it's possible to limit the debugging output to a certain

[gem5-users] Executing Binary Code in FS without a Kernel

Hello, I am new to GEM5 and I would appreciate any guidance. I would like to measure the performance of a assembly benchmark code. The benchmark accesses memory addresses where data is pre-dumped at these addresses in a RAW disk image. My current setup consist of the image disk (containing the

[gem5-users] Re: Limit debug output to certain instruction address range

Hi Hossam, > Yet another option is a way to enable/disable debugging in the config script mid-simulation. This would allow me to exit the simulation using an m5op before the instructions, enable debugging in the config script, continue, exit using an m5op after the instructions, disable

[gem5-users] Re: Chiplet Simulation with Gem5

The latest version of garnet in the gem5 repo allows you to model multi-chiplet NoCs. [The gem5_chips repo is deprecated - and was actually forked off an earlier version of HeteroGarnet]. Here is its documentation on the gem5 wiki:

[gem5-users] Re: Chiplet Simulation with Gem5

Dear Dr. Krishna, Thank you so much for your response. I read the documentation you linked to in your email and have a few questions. 1. Are there any example config files that you are aware of that can help me start with chiplet simulation (with some basic routing techniques and topologies)? If

[gem5-users] Re: Executing Binary Code in FS without a Kernel

Hello Jason, Thank you for your response. My benchmark tests memory access where I want to have a hard drive from which data is accessed (e.g., accessing data from a SATA hard drive). I have two more questions: 1- from the documentation of GEM5, I learned that in FS mode the kernel and disk

[gem5-users] Re: Executing Binary Code in FS without a Kernel

Hi Alain, I'm the gem5-GPT bot, here to assist with your queries about the gem5 simulator. Please note that while I aim to provide accurate information, my responses could be wrong or may have been slightly edited for clarity. You can access the gem5-GPT on chat.openai.com/g/g-o3y1y4t8J-gem5-gpt

[gem5-users] Re: Can I use RiscvO3CPU with TSO?

Hello, That *should* work, but my confidence isn't very high. I suggest running tests to see if you can produce TSO and non-TSO executions with and without the option. Cheers, Jason On Thu, Feb 15, 2024 at 12:32 PM Z HW via gem5-users wrote: > > I know that RISC-V assumes RVWMO. But if I want

[gem5-users] Re: Limit debug output to certain instruction address range

Hi Jason, Thanks for the very quick response! I managed to surround the ROI with m5op instructions to issue WORKBEGIN and WORKEND events, but now the stats.txt​ file is getting out of hand. It dumps stats every time the simulation pauses. Is there a way to make it not dump on every event or

[gem5-users] Re: Limit debug output to certain instruction address range

Hi Hossam, If you're using the stdlib, you can override the default ROI begin handler. See the documentation here: https://github.com/gem5/gem5/blob/stable/src/python/gem5/simulate/simulator.py#L145 If you're not using the stdlib, then look for where the code you're using calls m5.stats.dump()

[gem5-users] Re: Chiplet Simulation with Gem5

Hi Preet, 1. I am attaching a config file for Kite Large topology that you can use as a reference for building chiplet-based topologies. More info on Kite Large can be found in this paper: https://dl.acm.org/doi/abs/10./3437539.3437683 2. HeteroGarnet only handles the network traffic. So