[gem5-users] [Ruby memory model] Cache clusivity in MESI

Hi, The gem5 ruby introduction page refers that both MESI 2-level and MESI 3-level as strictly-inclusive caches. https://www.gem5.org/documentation/general_docs/ruby/ Is there any configurability in gem5 to change this behaviour to non-inclusive or it requires to be done by protocol state machine

[gem5-users] Running X86 processor in Real Mode

Hi, Is it possible to force x86 processor to run in Real Mode when simulating in SE or Protected mode is the only possible configuration? Thanks, Alain ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to