Hi Joel, Sorry for the confusion regarding the statistics. Some of the problems are related to some statistics that have been kept around for legacy purposes to match the original detailed CPU model.
To give you a brief summary (all of these apply to the Alpha architecture, and to a single core): sim_insts: Number of instructions simulated, excluding software prefetches and nops. commit.COM:count: Every committed instruction excluding software prefetch instructions commit.commitCommittedInsts: Every single instruction committed commit.committedInsts: Number of instructions simulated, per SMT thread, excluding software prefetches and nops. commit.committedInsts_total: Sum of commit.committedInsts over all SMT threads. Most likely sim_insts and commit.committedInsts_total will match on any specific CPU (assuming no software prefetches). I have not run an MP simulation in a while, but I believe when you specify a number of sim_insts to simulate for, it will simulate until one of the core hits that count, and then exit. I'm not sure if M5 currently has the ability to specify the total number of instructions across all CPUs to simulate for, though it shouldn't be too difficult to add. Kevin Quoting Joel Hestness <[EMAIL PROTECTED]>: > Hi, I am looking at instruction counts that are output in m5stats.txt for > a couple simulations that I have run. I am using ALPHA_FS with the detailed > core, and I am confused about the values that are output. In m5stats.txt, > the value 'sim_insts' claims to the the number of instructions simulated. On > further inspection, each of the cores also has commit statistics that include > 'commit.COM:count', 'commit.commitCommittedInsts', 'committedInsts' and > 'committedInsts_total'. I tried tracing through the code where these > counters are updated, and some of them seem to be redundant. The problem > that I am having is that when I sum any of these commit statistics over the > set of cores, none of them are equal to 'sim_insts'. In fact, the difference > is usually 5-10x. I am hoping someone could shed some light on the > discrepency, and let me know the purpose of all these seemingly redundant > counters. Thanks, Joel
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