Hi M5,
I'm practicing some little changes on M5 cache architecture and
replacement policy.
In file M5/src/mem/cache/cache.hh
bool access(PacketPtr pkt, BlkType *blk, int lat, PacketList writebacks);
Is the source (src) of pkt means the CPUid, which send this pkt
through bus to L2?
I want to
for it, but those aren't necessary for it to work
properly, they just help the simulator run faster. There's a
configuration option for the kernel that sets how many CPUs it supports.
That's probably set to 1.
Gabe
On 06/03/11 05:44, 冠男陳 wrote:
Dear M5,
I'm now trying to simulate a full system
Dear M5,
I'm now trying to simulate a full system with more than 1 core (CPU).
With image x86_64-vmlinux-2.6.22.9, I got following messages in m5term:
markcup:~/Gem5/m5_new$ ./build/X86_FS/m5.debug configs/example/fs.py -n 4
m5 slave terminal: Terminal 0
Linux version 2.6.22.9
Hi M5,
Few days ago, I got errors when running X86 FS and SE:
1. m5.debug: build/X86_FS/arch/x86/insts/macroop.hh:78: virtual
StaticInstPtr X86ISA::MacroopBase::fetchMicroop(MicroPC): Assertion
`microPC numMicroops' failed.
2. Segmentation fault
Today, I use another server and again go through
Hi, Mahmood Naderan,
I saw your mail in which you said your X86 full system simulation runs well.
I tried to follow the steps in your mail, but my X86 full system doesn't work.
Could you share some information about your environment, ex. OS version?
Thank you!
Mark Chen
Hi, Mahmood Naderan,
First, the link to that email:
http://www.mail-archive.com/m5-users@m5sim.org/msg04969.html
Second, there are information of my M5 and what I've done:
markcup:~/Gem5/m5-stable$ ls
AUTHORS README SConstruct build_opts disk m5out
parsetab.py tests LICENSE
