Can you give us some information about what you're running
configuration wise? Your config files would actually be good. You're
stressing something that hasn't really been stressed before, so the
first step is for us to be able to reliably duplicate the issue.
Ali
On Mar 12, 2008, at
Hi David,
There are a couple of inconsistencies here. Are you running MIPS
binaries? The error below says ALPHA, so I'm a bit confused.
Ali
On Mar 12, 2008, at 10:52 AM, David Robert White wrote:
Hi Lisa
Thanks for your help.
I've used the native GCC compiler, i.e. x86 targeted, to
The faults are served by palcode and if that fails then the OS gets
involved. We haven't made up the fault names, they're the the ones
defined in the Alpha ISA hardware reference manual. In particular a
dtb_miss_single fault is a normal data tlb miss, and a dtb_miss_double
is a fault that
to test the result at the end, it
outputs the
errors.
Everything else is the same.
command to run:
build/ALPHA_SE/m5.opt configs/splash2/run.py -n 4 -b Radix
- Sujay
- Original Message - From: Ali Saidi [EMAIL PROTECTED]
To: M5 users mailing list m5-users@m5sim.org
Sent: Wednesday
You'll need to read the options, the help doesn't actually provide
much help. -f I think is what you're looking for.
Ali
On Mar 26, 2008, at 12:05 PM, Geoffrey Blake wrote:
Doesn't seem to be very clear to me what to do. I see a -j option
for a
jobfile? What is that supposed to be?
On Mar 28, 2008, at 4:54 PM, Jeff Diamond wrote:
Our research group is evaluating M5 as a possible new simulator
standard. Some key information I have not been able to find
anywhere, so your help is greatly appreciated:
(1) Full system simulation on SPARC: The Docs imply this is
On Mar 28, 2008, at 6:43 PM, Jeff Diamond wrote:
Ali Saidi wrote:
I should clarify that full-system isn't supported for *SPARC* in
our out-of-order model (it does work for syscall emulation), and it
could work with full-system, but some of the ASI nastiness would
have to be handled. Our
Actually in our tutorial as ASPLOS 2008 we showed an example of adding
a variance to delay memory. Here is a diff to m5 that should do the
trick. Just set latency_var = 'XXns' on the Physical Memory object and
that should do the trick. It will still be deterministic for a given
latency
No, I'll commit it.
Ali
On Apr 9, 2008, at 6:29 PM, nathan binkert wrote:
Other than the FSConfig.py change, is there any reason this shouldn't
just be in the tree?
On Wed, Apr 9, 2008 at 1:53 PM, Ali Saidi [EMAIL PROTECTED] wrote:
Actually in our tutorial as ASPLOS 2008 we showed an example
There were a couple of patches sent to the list that should have
resolved this problem.
http://article.gmane.org/gmane.comp.emulators.m5.users/2608
http://article.gmane.org/gmane.comp.emulators.m5.users/2598
Ali
On Apr 13, 2008, at 12:49 AM, Clint Smullen wrote:
I have seen previously
You can modify the exit() syscall to not exits until the number of
CPUs in the system all have called exit(). That would solve the
problem, however it's not completely clear that's what you want to do.
If you're running a multiprogrammed workload you probably want to
capture time when all
You're the first person I know of to try and run spec2006 on M5.
(1) if you ran a Tru64 binary ftruncate would probably work just fine,
but the corresponding entry isn't in the linux syscall table. Adding
it might make things work, but the parameters may be different.
Changing ftruncate in
Hi Reza,
M5 doesn't is only single-threaded at this point. One of our goals is
to allow multi-core workloads to run faster on a multi-threaded
machine, but that hasn't been developed yet. The best you can do is
run 8 copies each one running a different experiment at this point
(or help
Hmm that sounds like a bug. What are you running? Can you give us a
snippet of the instruction trace around that instruction for both the
timing and the detailed cpu? The only thing I can think of is that the
o3 cpu speculates on a load or store, however it should realize that
was the bad
I've never seen anything like that. We're going to need more
information to figure out what's going on. An command line,
instruction trace, same bit of the instruction trace for a timing cpu,
etc.
Ali
On Apr 25, 2008, at 11:11 PM, Shoaib Akram wrote:
I have run most spec benchmarks using
All you see is aborted? Not an assert that is printed?
Ali
On Apr 26, 2008, at 9:22 PM, bipin kadel wrote:
hi,
I tried to simulate the 4 cpus with each cpu running the 2
benchmarks from spec cpu. I am
using spec cpu EIO trace. But before completing the simulation, it
aborts showing
Take a look at the util/m5 directory. There are examples of how we
execute those instructions you noticed in decoder.isa.
Ali
On Apr 30, 2008, at 11:54 PM, Reza Farivar wrote:
The Alpha ISA has a couple of reserved instructions. with opcodes
ranging from 01 to 0E. The support for these
Geoff Blake noticed that the alpha/linux cross compiler we posted on
the website was old enough to only support LinuxThreads. He has
compiled a new version that supports NPTL and I put it on the download
page. If you have no idea what I'm talking about then it probably
doesn't effect you,
You should look at the output files (build/ALPHA_FS/tests/opt/quick/
10.linux-boot/alpha/linux/tsunami-simple-atomic/*) and see what they
say.
Ali
On May 5, 2008, at 7:13 PM, Andrew Stanely wrote:
hi,
I am trying to compile m5_2.0b4 with ALPHA FS .
I can build m5 successfully by scons
alpha FS compile error (Andrew Stanely)
2. Re: How to dump m5stats per cycle? (jerry lrui)
3. Re: m5 alpha FS compile error (Ali Saidi)
4. Re: How to dump m5stats per cycle? (Lisa Hsu)
--
Message: 1
Date: Mon, 5 May
)
3. Re: m5 alpha FS compile error (Ali Saidi)
4. Re: How to dump m5stats per cycle? (Lisa Hsu)
--
Message: 1
Date: Mon, 5 May 2008 19:13:13 -0400
From: Andrew Stanely [EMAIL PROTECTED
I again want to point out that if you're interested in a couple of
statistics every cycle, this is not the optimal way to do it. Not only
will you end up with an extremely large text file, you'll also slow
down the simulation maybe 10x or more to dump stats in this manner.
What you
I would check your compiler and make sure you're using the newest
version of m5.
test.c:
#include stdio.h
int main( void )
{
double a[2];
a[0] = 2.3;
a[1] = 5.7;
printf( a[0] = %f\n, a[0] );
return 0;
}
11:46:39 [saidi:zeep ~/work/m5.dev] alpha-unknown-linux-gnu-gcc -
I've run lmbench in fs mode. I couple of the lmbench benchmarks will
probably work in SE, mode, but many of them stress kernel services so
they won't work at all.
Ali
On May 13, 2008, at 2:35 PM, Shoaib Akram wrote:
Does anyone tried to successfully run lmbench or linpack using m5 in
It could still be a cache bug because the O3 cpu will have multiple
outstanding cache requests while the timing cpu will not.
Ali
On May 13, 2008, at 6:11 PM, Shoaib Akram wrote:
I will come back to you soon with the benchmark and the point where
it occurs.
Actually, it happens way far
In the past people have hacked such things in, but there isn't
presently a way to do that. To introduce generic support for such a
thing you would need to do something like extending the AddrRange
class (and updating all associated member functions). I believe that
would break the RangeMap
I would guess that some file (probably the disk image) is corrupt.
Ali
On May 25, 2008, at 11:07 PM, nathan binkert wrote:
I even went back and started from scratch with 2.0b4. The exact
commands I
used were:
% scons build/ALPHA_FS/m5.debug
% build/ALPHA_FS/m5.debug configs/example/fs.py
root
permissions on the machines I'm using so I can't directly install a
newer version of libc. I just wanted to check if there was another
solution possible.
Thanks,
Brad
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On
Behalf Of Ali Saidi
Sent: Friday, May 23
directory.
Thanks for pushing me to think harder about it. :)
By the way, thanks for creating the wiki page...it is definitely
helpful.
Brad
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On
Behalf Of Ali Saidi
Sent: Tuesday, May 27, 2008 6:20 PM
To: M5 users
No, it's not generally need. It's used to load symbols of benchmarks
for debugging.
Ali
On Jun 9, 2008, at 2:40 PM, Sujay Phadke wrote:
Some of the rcs files contain the loadsymbol command. Are
the .symbol files like a table between the source code on the
debugger host side and the
On Jun 11, 2008, at 7:49 PM, nathan binkert wrote:
Is it possible to quantify the accuracy of the memory timing model
with a
real piece of hardware? Lets say we put in real numbers for the
various
latencies and other parameters to make it close to a real SDRAM.
Will it be
useful to
On Jun 23, 2008, at 1:23 PM, Sujay Phadke wrote:
Hello,
If I try to run O3 in SE mode directly, without using any
fastforwarding, it gives me the error:
build/ALPHA_SE/m5.opt configs/splash2/runsplash.py -d -n4 -b
OceanContig
warn: Increasing stack size by one page.
warn:
-
From: Ali Saidi [EMAIL PROTECTED]
To: M5 users mailing list m5-users@m5sim.org
Sent: Monday, June 23, 2008 5:39 PM
Subject: Re: [m5-users] error running O3 directly with more than 1 cpu
On Jun 23, 2008, at 1:23 PM, Sujay Phadke wrote:
Hello,
If I try to run O3 in SE mode directly
Hi Brad,
It seems that Nate was a little over-zealous with squashing swig
warnings. I've pushed a changeset to m5-stable that fixes the problem.
Sorry about that, we do intend to keep m5-stable as stable as possible.
Thanks,
Ali
On Jun 24, 2008, at 3:32 AM, Beckmann, Brad wrote:
Hi All,
On Jun 27, 2008, at 9:16 PM, Rick Strong wrote:
On Jun 26, 2008, at 7:01 PM, Rick Strong wrote:
1) If using just quiesce (without cycles or ns ... etc), m5sim.org
states that an interrupt is the means of waking up the core. Can any
interrupt be used or must there be a specific one? Also,
Hi Paul,
Now your question makes a lot more sense. The bus model was re-written
for 2.0 since the memory system was completely overhauled and the old
bus model would no longer work. What started as me hacking together
something to start testing things grew into the final product with the
I just added the linux-patches repository to repo.m5sim.org. It is a
Mercurial Queues repository of patches that we apply on top of the
Linux Mercurial repository (http://www.kernel.org/hg/linux-2.6/). The
standalone patches on the website will not be updated in the future.
If you would
It should compile just fine with gcc on Solaris.
Ali
On Jun 30, 2008, at 6:12 PM, Robert Pulumbarit wrote:
We have an UltraSPARC T1 running Solaris. Is it possible to compile
and run M5 on this machine? The M5 compilation page mentions that
M5 can be ported to Unix-like OSes. Are
] Error 1
scons: building terminated because of errors.
[EMAIL PROTECTED] ~/m5-2.0b3]$
What should I try next?
Thanks,
Robert Pulumbarit
On Sun, Jul 6, 2008 at 11:47 AM, Ali Saidi [EMAIL PROTECTED] wrote:
Using SunCC is not supported as a front end. If you really want to use
SunCC
In syscall emulation we do a reasonable job creating the
gettimeofday() syscall. I can't think of a reason why gettimeofday()
wouldn't work in full system.
Ali
On Jul 7, 2008, at 4:39 PM, richard strong wrote:
Hi all,
I was wondering how accurate time information gather from calls to
Seems pretty self explanatory:
gzip: tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz:
No such file or directory
For the EIO tests to run you need the the EIO trace file, which I
don't believe we can distribute. However, since you are at umich you
can find all the files on
I'm not completely certain as I've never done it, but looking at the
error message I would guess that a line like:
all_cpu_list.append('MyCPU')
isn't is a SConsopts file.
If that isn't the problem hopefully Kevin or Korey will respond with a
better answer.
Ali
dOn Jul 17, 2008, at 7:19 PM,
The wiki is correct.
Ali
On Jul 18, 2008, at 9:18 AM, nathan binkert wrote:
Can you fix the wiki?
Thanks,
Nathan
On Thu, Jul 17, 2008 at 10:16 PM, Meng-Ju Wu [EMAIL PROTECTED]
wrote:
Hi Ali,
Thank you very much. You are right. I should use
all_cpu_list.append('MyCPU') in the
The information is in the symbol table, so you could use the libelf
code to load that data somewhere. Generally I don't need all that
information so just typing in the symbol name into lxr.linux.no does
the job.
Ali
On Jul 18, 2008, at 3:01 PM, richard strong wrote:
Hi,
I was wondering
?
-Rick
Ali Saidi wrote:
The information is in the symbol table, so you could use the libelf
code to load that data somewhere. Generally I don't need all that
information so just typing in the symbol name into lxr.linux.no does
the job.
Ali
On Jul 18, 2008, at 3:01 PM, richard strong wrote
I think we would like to see those changes in m5 so MQ might be
better. With MQ you can still use hg view to see a list of all the
changes, I'm not sure that hg revert will work but you should be
careful about using it anyway, and you can commit changes in HQ with
hgqcommit.
Ali
On Jul
Hi Dengning,
You should take a look at the ASPLOS tutorial and video. In it we
describe the process, but in simple terms the py files are processed
and turned into header files which defile things like
PhysicalMemoryParams. The actual processed files are in the build
directory. If you
Hi Rick,
There isn't a mechanism built-in, however you could create one
reasonably easily by adding a PC based even (like the
DebugPrintkEvent) and have it break on the entSys symbol in the
kernel. You would have to do some more work to change the syscall
number into a name, but all that
Philip,
I think that is a pretty reasonably idea, however as you state the con
is reasonably high. I don't think we would want to distribute them
with M5 proper, because it would be difficult to verify that all the
configurations still work. I think the best option is to have a
Are you certain you have g++ installed? The only reason CXX could be
None is if it wasn't set in the shell you used to execute scons and
scons couldn't find g++ in your path. In retrospect we should probably
check that the CXX is found by SCons, but either way I imagine that
either g++
to add /usr/bin/g++ to it?
Aaron
Message: 2
Date: Thu, 4 Sep 2008 14:56:33 -0400
From: Ali Saidi [EMAIL PROTECTED]
Subject: Re: [m5-users] Question on Compiling M5Stable
To: M5 users mailing list m5-users@m5sim.org
Message-ID: [EMAIL PROTECTED]
Content-Type: text/plain; charset=US-ASCII
I think you have a misconception about the events. Events can be
reused, so as long as you don't have more than one event outstanding
for a specific task (and you really shouldn't ever do this), you
shouldn't need to dynamically create them. Of the top of my head I
can' think of what the
On Sep 22, 2008, at 7:45 AM, nathan binkert wrote:
Given a physical address of a word i want to find out the complete
cache-line. Meaning i want to find out the lowest address and highest
address of the word which is mapped to that cache line.
Now one easiest apporach is to just find out the
Try to apply the patch that Nate committed to the development
repository (id 26231e06f86d). That should fix your problem.
Ali
On Sep 23, 2008, at 12:00 PM, Aaron Williams wrote:
Hello All,
I am still having an issue. G++ is installed on my system, however
when I run scons to compile
Hi Meng-Ju,
You could define it in base/statistics.hh, however I'm not sure what
it would mean. I could see it working for a scalar statistics, but not
for any other type of statistic. Generally, statistics are only for
book-keeping or printing at the end of an interesting bit of
Hi Meng-Ju,
Thanks for creating that page. It's great and will probably help a lot
of people. Looking at the development repository we've implemented
ftruncate(), getrlimit(), and getcwd(), but we don't yet have code for
mremap(). I thought about including your code, however I don't
I'm going to commit a fix that verifies that the file is writable.
Ali
On Oct 2, 2008, at 12:32 PM, Eduardo Olmedo Sanchez wrote:
Hi Meng yes I got my config.ini, the problem was that M5 couldn't
write in /tmp/output and it didn't say anything, I just changed the
directory to a local one
procedure for running benchmarks in FS mode?
thanks a lot for taking time to answer my questions.
Ali Saidi saidi at umich.edu wrote: That error shouldn't be a
problem. The benchmark is almost certainly still running, just some
syscall it did attempted to load a module, however that module
Sure, you can. Also, if you don't want to run full system, the syscall
emulation side of M5 will happily run an osf/1 binary.
Ali
On Oct 2, 2008, at 4:32 PM, Hongbin Sun wrote:
Ali and Steve:
Thanks a lot for take your timing to answer my
question. Actually , I am a little
The bridge isn't supported in the middle of a coherent hierarchy.
Steve can probably comment more about why, but minimally it would need
to support passing the express-snoops and it currently doesn't.
Ali
On Oct 5, 2008, at 11:21 PM, Shoaib Akram wrote:
I am simulating a multiprocessor
The short answer is that there isn't one. If you look at (and re-
enable) the ThreadInfo printing work/m5/src/arch/alpha/linux/system.cc:
139. You can see how to get at thread information at any time. You can
use that to grab the statistics you want. However, you could probably
just compile
It won't be exactly 1.5GHz, but you can have 1.499GHz or 1.501GHz (667
and 666 ticks per clock, respectively).
Ali
On Oct 15, 2008, at 2:06 PM, Shoaib Akram wrote:
Is it possible for the bus to have 1.5GHz bus frequecy in m5. Given
global frequncy of ITHz, probably not?
It's a transition from S-E.
The cache has a block in a shared state and requires an exclusive copy
so it can write to it.
Ali
On Oct 16, 2008, at 4:26 PM, Shoaib Akram wrote:
what does memory commands UpgradeReq and UpgradeResp correspond to?
___
On Oct 21, 2008, at 2:06 PM, Rick Strong wrote:
Hi all,
I am attempting to generate all the stats necessary in the
SimpleTimingCPU model for our new power model. The last thing I need
to
know is the number of register accesses. However, src/base/cpu.hh,
there
are many functions that
On Oct 22, 2008, at 11:03 AM, jia wang wrote:
For M5 developper or anyone who can help:
This is Jiao, a student of ECE department of Northeastern Univ., and
I am trying to use M5 full system in my research. It is a great tool
for our research, but if we can have access to the M5 OS
It should work, although I generally use the checkpoint, restore,
switch method when sampling. There might be a problem with fast-
forwarding with multiple cpus. You should take a look at Simulation.py
and see what happens after the atomic cpu exits. All the atompc cpus
should be replaced
some
months back (dont know which release of m5 was it )...By the way,
when I use the method you describe, I get,
Restoring from checkpoint
fatal: Can't unserialize 'system.cpu1:_status'
Original message
Date: Fri, 24 Oct 2008 13:26:30 -0400
From: Ali Saidi [EMAIL PROTECTED
options.num_cpus=2
np=options.num_cpus
with np=2 was causing the problem...strange?
Original message
Date: Fri, 24 Oct 2008 15:48:20 -0400
From: Ali Saidi [EMAIL PROTECTED]
Subject: Re: [m5-users] switch cpus problem
To: M5 users mailing list m5-users@m5sim.org
It seems like your
when I tried different patches on each kernel, some make it go
through all steps on m5 webpages, some cause errors uring compiling.
Thanks, and your help is really appreciated.
Jiao
--- On Wed, 10/22/08, Ali Saidi [EMAIL PROTECTED] wrote:
From: Ali Saidi [EMAIL PROTECTED]
Subject: Re: [m5
propagated, it seems. I think manually calling schedule on the Event
is more intuitive and what most code does anyways, but it might be
good to check and make sure that all users of EventWrapper have been
fixed.
- Clint
On Oct 27, 2008, at 6:57 PM, Ali Saidi wrote:
Hi Clint,
Nice catch
.
On Oct 29, 2008, at 12:39 AM, Shoaib Akram wrote:
I just want them to be set to constant number of cycles. And change
the frequency. for instancem bridge should queue requets for 5
cycles, at 2GHz or at 4GHz...
Original message
Date: Tue, 28 Oct 2008 21:22:47 -0700
From: Ali
Another possible problem is we never actually free mmaped memory. So,
any memory that is freed isn't really unallocated.
Ali
On Oct 30, 2008, at 6:53 PM, Shoaib Akram wrote:
looks like this is whats happening. But cant speculate on the
reason. Its obvious to me that art is very
You should run M5 in a debugger and see where the segfault comes from.
Looking over the code you have below I don't see a problem. As for the
array, sure but you would have to insert each element in the array
separately.
Ali
On Nov 4, 2008, at 3:41 AM, Dean Michael Ancajas wrote:
Why do you need the src number of the cores? The Request object
contains a cpuid/threadid that you can use for identifying which
requests come from a CPU and what cpu that is.
Ali
On Nov 5, 2008, at 3:09 PM, Bob Nagel wrote:
Hi Steve thanks for your answer, how can I know the src number of
The linux scheduler can do all kinds of interesting things, especially
during short runs. As threads start, there are a lot of locks in the
memory system to allocate memory and map the pages for the threads.
Additionally, it can take some time (relative to the length of the
simulation) for
The device between the I/O and coherent space doesn't need to be a
cache, but it needs to do everything a cache does with the exception
of caching data. As Steve said, a full-block DMA write is the only
case that isn't problematic as a broadcast invalidate will do. Partial
block writes
Yea there would be a problem. The bridge, as it is currently written,
does not pass coherence messages.
Ali
On Nov 10, 2008, at 8:59 PM, Rick Strong wrote:
Would it affect coherency if I added a bridge between the membus and
iocache? I currently do checkpoints with a bridge between the
No it's probably from all the libc _start code that is executed. Even
if main() is a single line there is much more code that is included in
the binary to setup the environment properly, get the arguments in
order, see if the terminal is character or line buffered, etc. You
should be able
No, you don't need to have root privileges on the machine that you're
running M5 on, but you do need them on some system because the mount
requires root privileges. You could run linux inside a VM or with a
emulator such as Bochs for this purpose.
Ali
On Nov 12, 2008, at 3:44 PM, Bob Nagel
In this case cpu_side doesn't mean exactly what you think it means in
this case. CPU side means the I/O cache side, a better name would be
request side, while the mem_side is the response side. The cache
objects in general can't handle an uncached write going from the mem
side to the cpu
How about:
system.busAB = [[Bus () for i in xrange(c)] for i in xrange(c)]
However, I imagine that this configuration is going to get impossible
to think about quite quickly.
Ali
On Nov 17, 2008, at 1:52 PM, Shoaib Akram wrote:
Not related to m5 but just asking:
Currently, I have
You need to download and compile a new version of the console code
(alpha-system repository). There was a bug that limited the system to
2GB of memory.
Ali
On Nov 19, 2008, at 9:39 PM, Hongbin Sun wrote:
Dear:
I just got this problem and I will be appreciate if you can
offer
I'm not completely sure, but each packet has an opaque pointer that it
sends along with the packet that must be restored before the response
is send back to the host. In the case of a store for the o3 cpu, this
pointer contains information about the instruction, slot in the store
queue,
that is a problem of my old
kernel?. Thanks.
On Mon, Nov 24, 2008 at 6:24 PM, Ali Saidi [EMAIL PROTECTED]
wrote:
Why are you running such an old kernel?
Add the O3CPUAll traceflag and start tracing a bit earlier. You
should
figure out where that address is coming from.
Ali
repo; if someone feels that it's urgent
enough that they're willing to work with an untested bare patch let me
know.
Steve
On Sun, Nov 30, 2008 at 12:08 PM, Ali Saidi [EMAIL PROTECTED] wrote:
It helps if I include the patch...
Ali
On Nov 30, 2008, at 1:40 PM, Ali Saidi wrote:
Here
As the warning that is printed with the DRAM object says, no testing
or validation of the results has been done so there could be a bug in
the model. If you really need accurate DRAM timing, I would suggest
you get one of the other DRAM models people have ported to M5 that
haven't made it
I can't really give you any insights into the cache itself. However, I
would go about accomplishing this with a new packet type (e.g.
FlushReq). Are you executing some instructions to simulate the time to
do these operations or do they just happen instantly? If the former, I
would just add
On Dec 8, 2008, at 3:49 PM, Ryan Markley wrote:
Hello,
I have a system with 4 cpu and one L2 cache shared with all of the
cores, I am doing the simulations with the detail cpu. I am interested
in study how the cores access to the shared cache. I have been looking
in the code of mem/bus.cc
. Is there any
similar
for the cache?, where is the code that management the petitions to
the
cache?.
Thanks.
On Tue, Dec 9, 2008 at 6:56 AM, Ali Saidi [EMAIL PROTECTED] wrote:
On Dec 8, 2008, at 3:49 PM, Ryan Markley wrote:
Hello,
I have a system with 4 cpu and one L2 cache shared
An additional point is that read/write requests originating from a I/O
device don't have a CPU id/PC.
Ali
On Dec 10, 2008, at 8:19 AM, Joe Gross wrote:
Aah, I should clarify my comments then. I tried using the
Request::getPC() and similar functions, but I end up with an assertion
error
It looks like a serialization bug to me. What devices are you using?
Just the defaults? Can you print out event-getCount() to see what the
value is? i imagine that some object is double executing a drain
event, but the count would say for sure.
Ali
On Dec 11, 2008, at 9:30 PM, Bob Nagel
of the simulator, I have not done any
changes. The value of event-getCount() is 4.
Thanks.
2008/12/11 Ali Saidi sa...@umich.edu:
It looks like a serialization bug to me. What devices are you using?
Just the defaults? Can you print out event-getCount() to see what
the
value is? i imagine that some
'),
L1Cache(size =
'64kB',
assoc = 2, latency = '2ns'))
I did not do any other changes to the source code.
On Fri, Dec 12, 2008 at 4:21 PM, Ali Saidi sa...@umich.edu
wrote:
Have you changed the default configuration any? It appears
from your
command line that you would only get
they are stored?, Are they stored in the retry list that I
said in my first mail?.
Thanks.
On Wed, Dec 10, 2008 at 2:00 AM, Ali Saidi sa...@umich.edu wrote:
Ryan,
They are stored back in the bus and then at a later time the bus
attempts to resend the packet to the cache. Eventually, it should
it doesn't matter. Which I
think is probably better for this particular case.
Lisa
On Tue, Dec 16, 2008 at 1:35 PM, Ali Saidi sa...@umich.edu wrote:
Does Lisa's change always create a cpu 0? Is there a cpu 0 that is
always running? Otherwise, the only issue I see is that CPU 0 might
That's a pretty good find.
I'm not sure what the correct answer is and there is one more
possibility: It could be a compiler bug.
Anyway, to eliminate some possibilities, according to the architecture
manual:
SLL and SLLX shift all 64 bits of the value in R[rs1] left by the
number of bits
It's not supposed to pass it to the binary, it's supposed to pipe it
to the binary.
E.g.: some_prog input_file
Ali
On Dec 16, 2008, at 5:25 PM, Shervin Sharifi wrote:
Hi,
I have a problem regarding giving an input file to the binary run
in SE mode.
The script se.py in
I noticed that happening in the syscall stubs as well. Could you open
up a bug report on the website so thath we'll make sure and get this
handled at some point?
Thanks,
Ali
On Dec 16, 2008, at 6:09 PM, Jack Whitham wrote:
On Tue, Dec 16, 2008 at 04:51:55PM -0500, gbl...@eecs.umich.edu
an advice in which fields
should I use to differentiate the different caches, I only know
gedId(). I have seen that each device has a different port number, but
is there any way to know what port belongs to each cache?.
Thanks.
On Tue, Dec 16, 2008 at 11:20 AM, Ali Saidi sa...@umich.edu wrote
cache and the cpu, in that
way I can store the accesses and the cycles and get the stats that I
want. My interest in the retry list comes to know how those accesses
are clustered.
Thanks.
On Tue, Dec 16, 2008 at 3:38 PM, Ali Saidi sa...@umich.edu wrote:
Yes and yes.
As you said the interface
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