[m5-users] cache coherence protocols in m5

how to enable cache coherence protocol in m5 in present version b.5.i didnot get any file,in versions b.3 and b.2 there is a folder called coherence inside cache folder.but iam unable to run compile those versions. i am getting TypeError: putenv() argument 2 must be string, not instance:

Re: [m5-users] cache coherence protocols in m5

+0530, biswabandan panda biswa@gmail.com wrote: how to enable cache coherence protocol in m5 in present version b.5.i didnot get any file,in versions b.3 and b.2 there is a folder called coherence inside cache folder.but iam unable to run compile those versions. i am getting

[m5-users] coherence protocols evaluation

hi, i want to evaluate the performanec of coherence protocol,for that i find m5-v.b3 useful,but after 2 days of various problems i am still unable to build it?and in the current version as far as my knowledge i can't plug coherence protocol depending upon my need,so please suggest what can i

[m5-users] segmentation fault

hi all, (1)i am using M5 2.0 b3 where i have used this command: build/ALPHA_SE/m5.debug -d output configs/example/se.py -n 2 -d --caches --l2cache -c mcf00.peak.ev6 -i inp.in i am getting segfault,but its running fine with n=1, (2)is it possible to use splash2 folder in this

[m5-users] coherence protocol statistics

hi all, i am using m5v.b5 with splash benchmarks with run.py but i am not getting any statistics related to coherence protocol state transitions but thats there in version 3.can anyone tell how to get those statistics in version 5.please do reply thanks biswa

[m5-users] want to assign different workload to different cpu

here is my run.py modified file,i am getting error like this: File string, line 1, in module File /home/biswa/Desktop/m55/src/python/m5/main.py, line 331, in main filecode = compile(filedata, filename, 'exec') File configs/splash2/run1.py, line 213 system.toL2bus = Bus() this is

[m5-users] segmentation fault in m5

hi all, (1)when i am using run.py with 4 processors i am getting statistics for only one of them.as splash is multithreaded how it can be?how to solve this (2)when i tried 4 processors in version m5v.2.b3, i am getting segmentation fault,but its working fine for 1 processor.this time its for

[m5-users] page table fault during splash2

Hi all, i got these messages when i simulate splash2(LUcontig,Raytrace and all) with se mode in m5v.b3 .it ran well for FMM,FFT panic: Page table fault when accessing virtual address 0x30 @ cycle 4511258000 [invoke:build/ALPHA_SE/sim/faults.cc, line 65] Program aborted at cycle

[m5-users] splash2 with m5beta6

hi all, i have tried to run splash2 in beta 6 version this is my command: command line: build/ALPHA_SE/m5.debug configs/splash2/run.py --rootdir splash/splash2/codes -t --frequency 1GHz -n 4 --l1size 64kB --l2size 256kB --l1latency 4ns --l2latency 11ns -b FFM these are the errors i got:

Re: [m5-users] splash2 with m5beta6

through the code and couldn't see anywhere the mem parameter of the cpu object was actually used, so it might fix it to just comment that line out. I tried that, and after fixing your -b parameter (it should be FMM, not FFM) things seemed to work. Gabe biswabandan panda wrote: hi all

Re: [m5-users] splash2 with m5beta6

the latest code here http://www.m5sim.org/wiki/index.php/Repository. There's currently a compilation bug for X86_FS I'm waiting to check a fix in for, but if you don't use that it won't affect you. Gabe biswabandan panda wrote: Thanks, i have commented that line,then i got

Re: [m5-users] splash2 with m5beta6

), the serial initial phase can have several million to hundred million of instructions, varying from program to program. On Fri, Oct 15, 2010 at 1:58 PM, biswabandan panda biswa@gmail.comwrote: thanks a lot Gabe,can you just do me afavour asking this question,i mailed to lot of m5 users even

Re: [m5-users] splash2 with m5beta6

thanks lida for help,but i am still getting those zeros, please suggest me something.thanks On Sat, Oct 16, 2010 at 1:40 AM, Lide Duan leaderd...@gmail.com wrote: http://www.m5sim.org/wiki/index.php/Splash_benchmarks On Fri, Oct 15, 2010 at 2:26 PM, biswabandan panda biswa@gmail.comwrote

Re: [m5-users] splash2 with m5beta6

provided by the link. If so, you should observe stats for different cores. On Fri, Oct 15, 2010 at 3:25 PM, biswabandan panda biswa@gmail.comwrote: thanks lida for help,but i am still getting those zeros, please suggest me something.thanks On Sat, Oct 16, 2010 at 1:40 AM, Lide Duan

[m5-users] getting zeros in multicores with splash

Hi all, i am still getting zeros all the cores except one for multicore simulation with splash,some of the m5 users were getting the result,i do not know whats wrong with my m5,its latest beta 6 version only,splash i have downloaded form m5 splashbenchmarks page.please suggest

Re: [m5-users] getting zeros in multicores with splash

hi, its running for single core. On Sat, Oct 16, 2010 at 10:00 AM, Steve Reinhardt ste...@gmail.com wrote: Is the benchmark running successfully on a single core, or is it not running at all? On Fri, Oct 15, 2010 at 8:41 PM, biswabandan panda biswa@gmail.com wrote: Hi all

Re: [m5-users] getting zeros in multicores with splash

not trying to fork more threads. Steve On Fri, Oct 15, 2010 at 9:39 PM, biswabandan panda biswa@gmail.com wrote: hi, its running for single core. On Sat, Oct 16, 2010 at 10:00 AM, Steve Reinhardt ste...@gmail.com wrote: Is the benchmark running successfully on a single core

Re: [m5-users] getting zeros in multicores with splash

with an error. I'd think you'd end up with an error message somewhere (maybe in one of the output files). On Fri, Oct 15, 2010 at 9:57 PM, biswabandan panda biswa@gmail.com wrote: no its not doing for Cholesky,but its doing FMM and FFT, is it the problem with binaries which prevent

Re: [m5-users] getting zeros in multicores with splash

but for Cholesky the input file tk23.o which is there inside Cholesky/input On Sat, Oct 16, 2010 at 11:08 AM, Steve Reinhardt ste...@gmail.com wrote: On Fri, Oct 15, 2010 at 10:26 PM, Ali Saidi sa...@umich.edu wrote: Error opening file There is your error Perhaps you don't have the

[m5-users] stats of moesi coherence protocol

hi all, i am using m5 beta 6 version with splash benchmarks,is it impossible to get stats related to moesi coherence protocol which is there in present m5.because in the older versions it was displaying all the relevant satas of coherence protocol.if i am wrong please clarify me? thanks

[m5-users] dramsim with m5

hi, where i can find the patch for integration of dramsim with m5 for the current beta 6 version. thanks biswa ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users

[m5-users] formula to find ipc in m5

hi all, i am using this formula to find ipc no of ticks simulated/1000=cycle count no of instructions simulated/cycle count=IPC, please correct me if i am wrong,because i am getting some large numbers in terms of IPC thanks biswa ___

[m5-users] prefetchers in m5

Hi all, what is the difference between num of hwpf identified and num of hwpf issued in the stats file?How to find the accuracy of a prefetcher i.e. number hw pf/pf used by processor. -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http

Re: [m5-users] Cache miss rate Vs IPC

. -- Ashutosh Jain ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http

Re: [m5-users] Is gcc-4.4.3 supported in M5?

/mailman/listinfo/m5-users -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http://www.cse.iitm.ac.in/%7Ebiswa/ Happy new Year 2011 ___ m5-users mailing list m5-users@m5sim.org http

Re: [m5-users] Is gcc-4.4.3 supported in M5?

M5 remotely on another cluster machine. I got the same error information, however the gcc version on that cluster machine is 4.4.1. But I don't know what the problem is. Thanks, Yingying Tian On Mon, Jan 17, 2011 at 7:43 PM, biswabandan panda biswa@gmail.comwrote: i am using gcc

[m5-users] Physical memory size

Hi all, the output of traces for --traces-flag=MemoryAccess are of 20 bits. (1)These are physical address right? (2)If i am changing the physical memory size to 1GB also, those traces are of 20 bits only (3)How to integrate it with DRAMsim -- *thanksregards * *BISWABANDAN PANDA* *M.S

Re: [m5-users] Varying block sizes of L1 and L2

-- Sunitha.P 9092892876 ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http

Re: [m5-users] Varying block sizes of L1 and L2

yes but in real processors the block size used to be same at all the three levels On Sun, Jan 23, 2011 at 4:02 PM, sunitha p suniac...@gmail.com wrote: Thanks Is it possible for having different block sizes for different caches On Sun, Jan 23, 2011 at 9:30 AM, biswabandan panda biswa

Re: [m5-users] Varying block sizes of L1 and L2

: can u just help me out in dis regard..because we got an error if we have different block sizes for L1 and L2 On Sun, Jan 23, 2011 at 4:16 PM, biswabandan panda biswa@gmail.com mailto:biswa@gmail.com wrote: yes but in real processors the block size used to be same at all

[m5-users] Physical memory size

-- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http://www.cse.iitm.ac.in/%7Ebiswa/ Happy new Year 2011 ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman

[m5-users] cache memory traces corresponds to physical address ?????

Hi, i am using ALPHA architecture to get the traces of memory and cache.whether cache memory traces corresponds to physical address or virtual address ? if virtual how can i get physical address? -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS

[m5-users] functional access in cache and memory

: system.cpu1.dcache: functional WriteReq d1c80 all are in same clock tick with same address, what does it mean? -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http://www.cse.iitm.ac.in/%7Ebiswa/ Happy new Year 2011

[m5-users] address traces for functions related to coherence

Hi, can anyone suggest me the procedure to get the address traces related to coherence protocols. -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http://www.cse.iitm.ac.in/%7Ebiswa/ Happy new Year 2011

Re: [m5-users] functional access in cache and memory

at the same tick. Steve On Mon, Jan 24, 2011 at 1:33 AM, biswabandan panda biswa@gmail.comwrote: in the trace file of cache memory i got something like this 243399000: system.l2: functional WriteReq d1c40 243399000: system.cpu0.dcache: functional WriteReq d1c80 243399000: system.cpu0

[m5-users] statistics for prefetch on i cache

where i opted for both data and instruction prefetches. Please clarify -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http://www.cse.iitm.ac.in/%7Ebiswa/ Happy new Year 2011

[m5-users] stream based prefetcher for m5

Hi all, i was trying to put stream prefetcher in the prefetch module of m5, i have done the initial amount of coding for it related to MSHR and all, If anyone has any idea about implementation issues for stream prefetcher ,please do reply -- *thanksregards * *BISWABANDAN PANDA* *M.S

[m5-users] graph generation

Hi all, i read about automatic graph generation in m5, i read the python files inside util/stats .could someone please tell me how to use it? -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http

Re: [m5-users] building error with mysql support

/leofs/ms/cs10s003/scon/bin/scons build/ALPHA_SE/m5.opt actually its inside a cluster, so i was specifying the complete path to scons then the basics On Sat, Jan 29, 2011 at 10:46 PM, Nilay Vaish ni...@cs.wisc.edu wrote: On Sat, 29 Jan 2011, biswabandan panda wrote: Hi all

Re: [m5-users] help regarding cache replacement policy

but whatever policy i am giving it takes always LRU. Are you using Ruby? -- Nilay ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH

Re: [m5-users] building error with mysql support

i have tried with all stable and dev versions except the new one which is updated 5 days ago but there is no build folder in the latest one On Sat, Jan 29, 2011 at 11:03 PM, Nilay Vaish ni...@cs.wisc.edu wrote: On Sat, 29 Jan 2011, biswabandan panda wrote: /leofs/ms/cs10s003/scon/bin/scons

Re: [m5-users] building error with mysql support

/ALPHA_SE/base/mysql.cc:106: error: 'mysql_error' was not declared in this scope scons: *** [build/ALPHA_SE/base/mysql.o] Error 1 scons: building terminated because of errors. On Sat, Jan 29, 2011 at 11:13 PM, Nilay Vaish ni...@cs.wisc.edu wrote: On Sat, 29 Jan 2011, biswabandan panda wrote: i

Re: [m5-users] building error with mysql support

the problem is i donot have the superuser privileges for that cluster, any other alternative?please On Sat, Jan 29, 2011 at 11:59 PM, Nilay Vaish ni...@cs.wisc.edu wrote: On Sat, 29 Jan 2011, biswabandan panda wrote: hey i tried with the latest dev version, it ran for 1 min or so

Re: [m5-users] building error with mysql support

/inorder/pipeline_stage.o] Error 1 scons: building terminated because of errors. On Sun, Jan 30, 2011 at 12:22 AM, Jai Menon jmeno...@gmail.com wrote: On Sat, Jan 29, 2011 at 12:37 PM, biswabandan panda biswa@gmail.com wrote: the problem is i donot have the superuser privileges

[m5-users] region of interest for splash benchmarks

HI, is there any way to find out ROI for different splash benchmarks in SE mode, how could simpoint be helpful for this? -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http://www.cse.iitm.ac.in/%7Ebiswa/ Happy

[m5-users] interaction between processor and prefetcher

the prefetched block never transfered to L1 cache. Please correct me if i was wrong? -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http://www.cse.iitm.ac.in/%7Ebiswa/ Happy Republic Day --- http://www.youtube.com/watch?v

Re: [m5-users] interaction between processor and prefetcher

i mean to say prefetch queue On Mon, Jan 31, 2011 at 7:56 PM, Steve Reinhardt ste...@gmail.com wrote: There is no prefetch buffer... what code makes you think that there is? On Mon, Jan 31, 2011 at 5:08 AM, biswabandan panda biswa@gmail.comwrote: Hi all, It seem

Re: [m5-users] interaction between processor and prefetcher

. Steve On Mon, Jan 31, 2011 at 6:36 AM, biswabandan panda biswa@gmail.comwrote: i mean to say prefetch queue On Mon, Jan 31, 2011 at 7:56 PM, Steve Reinhardt ste...@gmail.comwrote: There is no prefetch buffer... what code makes you think that there is? On Mon, Jan 31, 2011 at 5:08 AM

[m5-users] ruby and coherence protocol folders

Hi all, Did anyone tried any of python files - MESI_CMP_directory.py, MOESI_CMP_directory.py, MOESI_hammer.py, MI_example. py, MOESI_CMP_token.py, Ruby.py? please suggest how to use it with m5? -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT

Re: [m5-users] ruby and coherence protocol folders

, biswabandan panda wrote: Hi all, Did anyone tried any of python files - MESI_CMP_directory.py, MOESI_CMP_directory.py, MOESI_hammer.py, MI_example. py, MOESI_CMP_token.py, Ruby.py? please suggest how to use it with m5? -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR

Re: [m5-users] help: regarding inclusive property in cache

http://m5sim.org/cgi-bin/mailman/listinfo/m5-users -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http://www.cse.iitm.ac.in/%7Ebiswa/ Happy Republic Day --- http://www.youtube.com/watch?v=Kk02qPlnS2E

Re: [m5-users] ruby and coherence protocol folders

hey i got it. i understood On Tue, Feb 1, 2011 at 6:43 PM, biswabandan panda biswa@gmail.comwrote: thanks nilay, one doubt let say i want to simulate a 4 core system with splash benchmarks, with coherence protocol as there in the protocol folder, what changes i have to do in the command

[m5-users] the dataflow from processor to cache

AT THIS STAGE. -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http://www.cse.iitm.ac.in/%7Ebiswa/ Happy Republic Day --- http://www.youtube.com/watch?v=Kk02qPlnS2E ___ m5

[m5-users] trace-flag Cache error

hi all, i have changed these two lines in cache_impl.hh to get the traces for address of the block and set no instead of packet-address only. lines 326-328 DPRINTF(Cache, %s%s %x %d %x %s\n, pkt-cmdString(), pkt-req-isInstFetch() ? (ifetch) : ,

Re: [m5-users] trace-flag Cache error

panda wrote: i didn't get u , u mean to say which of these are invalid right? Then the function is taking Blocktype *blk i have tried with (block)- set and all if i am not wrong ? On Thu, Feb 3, 2011 at 10:30 PM, Nilay Vaish ni...@cs.wisc.edu wrote: On Thu, 3 Feb 2011, biswabandan panda

Re: [m5-users] trace-flag Cache error

thanks On Thu, Feb 3, 2011 at 10:57 PM, Nilay Vaish ni...@cs.wisc.edu wrote: On Thu, 3 Feb 2011, biswabandan panda wrote: first i thought for this,but when i was able to build it successfully without an error, i thought it may work. i want the stats at this point only, could u plz tell me

[m5-users] getting block address, set nos for misses

),blk ? hit : miss); -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http://www.cse.iitm.ac.in/%7Ebiswa/ ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi

Re: [m5-users] getting block address, set nos for misses

miss to a particular block in a particular set On Fri, Feb 4, 2011 at 8:34 PM, Nilay Vaish ni...@cs.wisc.edu wrote: On Fri, 4 Feb 2011, biswabandan panda wrote: Hi all, i want to generate block address and set nos for the misses also in line no 326 to 328 cache_impl.hh. i have

Re: [m5-users] getting block address, set nos for misses

hey thanks,that i know but the problem is how to find the block within the set, because all the codes are written in such a way that it takes care of hits only On Fri, Feb 4, 2011 at 8:41 PM, Nilay Vaish ni...@cs.wisc.edu wrote: On Fri, 4 Feb 2011, biswabandan panda wrote: miss

Re: [m5-users] getting block address, set nos for misses

Vaish ni...@cs.wisc.edu wrote: On Fri, 4 Feb 2011, biswabandan panda wrote: hey thanks,that i know but the problem is how to find the block within the set, because all the codes are written in such a way that it takes care of hits only On Fri, Feb 4, 2011 at 8:41 PM, Nilay Vaish ni

Re: [m5-users] getting block address, set nos for misses

no it impossible. i messed up with different functions. you told right. thanks On Fri, Feb 4, 2011 at 9:00 PM, biswabandan panda biswa@gmail.comwrote: initially by using findBlock it gets the block and then invalidated all the blocks, my point is when a cpu requests, it will check the tag

Re: [m5-users] getting block address, set nos for misses

no i think its not possible also. If the block is not there in the cache how you will find the address? On Fri, Feb 4, 2011 at 9:12 PM, Nilay Vaish ni...@cs.wisc.edu wrote: On Fri, 4 Feb 2011, biswabandan panda wrote: initially by using findBlock it gets the block and then invalidated all

Re: [m5-users] command line options in Option.py

mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http://www.cse.iitm.ac.in/%7Ebiswa/ ___ m5

Re: [m5-users] command line options in Option.py

= L2Cache(size='2MB') Thanks -Sheng On Fri, Feb 4, 2011 at 11:35 AM, biswabandan panda biswa@gmail.comwrote: yeah u can implement of your own like this: class L3(BaseCache): size = 8MB block_size = 64 latency = 24ns mshrs = 8 tgts_per_mshr = 4

Re: [m5-users] command line options in Option.py

) self.l2cache = l2c self.l2cache.cpu_side = self.toL2Bus.port self._mem_ports = ['l2cache.mem_side'] Thanks! -Sheng On Fri, Feb 4, 2011 at 11:48 AM, biswabandan panda biswa@gmail.comwrote: no if you want to use l3 it will create 2 levels at that time else u need

Re: [m5-users] getting block address, set nos for misses

hey one more thing, for prefetching case, there is no function which tells this prefetched address mapped to this block or block within set? any idea about this? On Fri, Feb 4, 2011 at 10:46 PM, biswabandan panda biswa@gmail.comwrote: yeah i got that when i thought it carefully, anyways

[m5-users] cache ports= 200

* *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ http://www.cse.iitm.ac.in/%7Ebiswa/ ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users

[m5-users] cache inclusion

hi, anyone tried cache inclusion in m5?any ideas how to go for it? -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ ___ m5-users mailing list m5-users@m5sim.org http

[m5-users] prfetch with cpuid

HI all, in the options specified for prefetcher, there is a option called prfetch_use_cpu_id= true, so in the stats file, i am getting stats of prefetcher per cpuid, but whn it comes to last level cache its not showing that, any idea what to do to get the stats for prefetcher with cpuid

Re: [m5-users] Cache coherence protocol

mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ ___ m5-users mailing list m5-users@m5sim.org

Re: [m5-users] Cache Stats

()), or do I need to take care of something else? Adwait ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT

[m5-users] max instructions

--l2latency 10ns -I 25000 -b bzip2 bzip2cache2core.txt -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi

[m5-users] max instructions, fast forward

Hi all, has anyone successfully tried max instructions and fast forward options, because for me it's not working -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa

[m5-users] ---fast-forward and --max---insts in SE mode for detailed simulation

Hi, could anyone plz tell me whether it is possible to use the above commands in SE for detailed mode of simulation. I read in the mailing list but still not clear. If its possible tell me how to do it, because i was using the same commands as there in the M5 slides.

[m5-users] prefetched blocks

Hi, i want to know when a block which is HWPrefetched (prefetched but unaccessed) comes to upper level cache (say L1), it should replace a block at the L1 but the the function insertBlock() in lru.cc always moves that block to head of the LRU stack. May be i am wrong but the demanded

[m5-users] stats according to cpu core id

Hi, Is it possible to get the stats for shared LLC(Last level Cache) with their cpu core id e.g: instead of system.l2 something like system.cpu0.l2 If yes, please do suggest how do it? -- ___ m5-users mailing list m5-users@m5sim.org

Re: [m5-users] Out of Order in Ruby

___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa

[m5-users] multiple prefetchers for last level

Hi all, Is it possible to assign more than one prefetcher in the last level shared cache? ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users

[m5-users] how to use bloom filters in m5?

hi, has anyone used bloom filters in m5? if yes, tell me how to go for it? ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users

Re: [m5-users] SPEC 2006 in FS Mode

://m5sim.org/cgi-bin/mailman/listinfo/m5-users -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman

[m5-users] stride prefetcher stats

Hi all, whwn i am specifying stride prefetcher as my prefetching policy, i am not getting the stats for instruction caches, but the stats for data cache and LLC is there. Then i observed the traces of HWPrefetch and i found there are prefetched blocks for I-Cache, then why the stats

Re: [m5-users] MRU

university. My life has been an open book. I have no secrets and I encourage no secrets --M.Gandhi ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users -- *thanksregards * *BISWABANDAN PANDA* *M.S

[m5-users] blob error

Hi all, i got this error fatal(readBlob(0x%x, ...) failed, addr); . Actually i have implemented some new prefetching algos and i am getting this error after some cycles of prefetching. Does anyone know what is the cause and how to fix it --

Re: [m5-users] blob error

thanks nilay, the address from that fatal is i.e. no address. Do u know how to fix it or i will go back to codes of page table and all On Mon, Mar 21, 2011 at 6:49 PM, Nilay ni...@cs.wisc.edu wrote: On Mon, March 21, 2011 7:40 am, biswabandan panda wrote: Hi all, i got

[m5-users] new prefetching algo stats

me out, as i was unable to figure it out where is the problem is. -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org

[m5-users] spec 2006 benchmarks completes before thread limit

hi all, i am using spec 2006 for 4 cores in a multiprogrammed fashion with max-insts per thread limit. but in my case the simulation used to over before all the threads simulated for the insts specified. in my case i have specified 250 million instructions for each thread, but the

Re: [m5-users] spec 2006 benchmarks completes before thread limit

():exitFunc)? Did you try running with the Exec traceflag on and figuring out what's the last instruction that each CPU runs? In any case, you'll have to do some digging to explain your results... On Mon, Mar 28, 2011 at 1:08 PM, biswabandan panda biswa@gmail.com wrote: hi all

Re: [m5-users] Snoopy Cache Coherence Protocol with cache-to-cache transfer

* *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/m5-users

Re: [m5-users] Snoopy Cache Coherence Protocol with cache-to-cache transfer

at 3:16 PM, prasanth_iitd mcs092...@cse.iitd.ernet.inwrote: biswabandan panda biswa.uce at gmail.com writes: Hi, It's really difficult to change the coherence protocol but you can try some older versions of m5 where coherence protocol was a separate module but you may end up

[m5-users] current status of DRAM module

Hi, What is the current state of DRAM module. Is it worth using it or it has some bugs in it as some mail says it's not tested. -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa

[m5-users] GHB prefetcher patch

Hi, Anyone has patch for GHB prefetcher because the way it's written in the m5 is quite different from the idea proposed. There is no index or GHB entries. Plz someone help me out -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http

Re: [m5-users] python script for spec2006

you can't get spec benchmarks for free. It's a commercial one you have to buy it On Fri, Apr 15, 2011 at 6:58 AM, Meng Dong dongmeng0...@gmail.com wrote: Hi all How or Where can I get SPEC2006 for free? 2011/4/13 Nilay Vaish ni...@cs.wisc.edu On Wed, 13 Apr 2011, biswabandan panda wrote

[m5-users] assertion failed for radix benchmark

. Program aborted at cycle 23154192500 I am unable to fix it out. i need help regarding how to fix it. -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ ___ m5-users mailing list

Re: [m5-users] Assertion `needsExclusive !blk-isWritable()' failed even after applying the corresponding patch

no On Tue, Apr 26, 2011 at 11:18 PM, Nilay Vaish ni...@cs.wisc.edu wrote: On Tue, 26 Apr 2011, biswabandan panda wrote: i am getting this Assertion `needsExclusive !blk-isWritable()' failed for some splash benchmarks even after changes made by Dave as in http://permalink.gmane.org

Re: [m5-users] Assertion `needsExclusive !blk-isWritable()' failed even after applying the corresponding patch

know if any of them would address this problem. If you are seeing it in a clean copy of the tip, then it's clearly a bug. Otherwise, it's hard to tell. Steve On Tue, Apr 26, 2011 at 10:50 AM, biswabandan panda biswa@gmail.comwrote: no On Tue, Apr 26, 2011 at 11:18 PM, Nilay Vaish ni

[m5-users] panic: Tried to execute unmapped address 0

Hi, could anyone tell me how to resolve this error? -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ ___ m5-users mailing list m5-users@m5sim.org http://m5sim.org/cgi

[m5-users] halt not implemented in PARSEC

HI , During simulation of PARSEC benchmarks, i am getting this error. Any idea how to resolve it. *panic: Halt not implemented! * -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa

[gem5-users] confusion between findVictim and InsertBlock functions

. Any suggestions -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa/ ___ gem5-users mailing list gem5-users@m5sim.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] parsec with gem5

[setName:build/ALPHA_FS/base/statistics.cc, line 176] Memory Usage: 1468884 KBytes Program aborted at cycle 0 Aborted -- *thanksregards * *BISWABANDAN PANDA* *M.S.(RESEARCH SCHOLAR)* *RISE LAB* *IIT MADRAS* http://www.cse.iitm.ac.in/~biswa

Re: [gem5-users] parsec with gem5

. Gabe On 06/04/11 22:02, biswabandan panda wrote: Hi gem5, I was using latest m5 dev along with parsec, i was able to build it successfully, during simulation i was getting something like this:. I haven't changed anything at all. Any clue how to resolve it. panic: invalid

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