All times in the config.ini have been converted to ticks. Bandwidths
to bytes per tick. The default is that a tick is 1ps, so 2GHz is
500ps and thus 500 ticks. I've been meaning to improve the config.ini
output to display both values, but I haven't gotten to it yet. Please
file a bug report if
.
- Sujay
- Original Message -
From: nathan binkert [EMAIL PROTECTED]
To: M5 users mailing list m5-users@m5sim.org
Sent: Tuesday, March 25, 2008 12:06 AM
Subject: Re: [m5-users] Troubel running Spec2K
Did you get this figured out? I understand the bug in M5 that allowed
tracking
the changes to the patch file though.
Geoff
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On
Behalf Of nathan binkert
Sent: Wednesday, March 26, 2008 12:18 PM
To: M5 users mailing list
Subject: Re: [m5-users] Full System Checkpoints
I'll take
Did you figure this out? If not please say so and maybe we can get
someone to actually respond.
Nate
On Fri, Apr 4, 2008 at 8:00 PM, Shoaib Akram [EMAIL PROTECTED] wrote:
How are source ids assigned to different components in m5 beta 5? I have been
using if dest_id==0 meaning membus, do
I want to run the following multiprogramming workload. Two different
programmes with multiple threads running on the same multiprocessor system.
Looks like m5 only supports runing one programme with multiple threads on a
multiprocessor system .
I'm not an expert in the syscall emulation
I want to find a full system simulator which can be used to test the access
of multicore architecture to the cache, main memory, harddisk or even
flash. Can M5 help me realize it?
Yes, though the model for the hard disk isn't particularly
sophisticated. If you need very accurate timing,
Are you sure that the permissions are correct? If you do cat
/dist/m5/system/binaries/vmlinux /dev/null, does it work?
On Tue, May 6, 2008 at 7:39 AM, Andrew Stanely [EMAIL PROTECTED] wrote:
Hi, thanks,
I have checked it,
in
build/ALPHA_FS/tests/opt/quick/
I've done this hundreds of times and the instructions on the webpage
are correct. My best guess is that there is some strange permissions
issue that is masked, or you've corrupted the image file somehow.
Nate
On Thu, May 8, 2008 at 4:01 PM, Mike Anderson [EMAIL PROTECTED] wrote:
thanks,
The exit system call is handled, so you can hack into the exitFunc()
function in src/sim/syscall_emul.cc if you want to do it in C++. In
python, the simulate function returns an ExitEvent object. Right now,
you can see that we generally call only getCause() on that object.
There is also a
by zero.
I guess what I would need is to be able to prevent the simulator from
ignoring this. Any ideas?
Thanks
David
--
Message: 7
Date: Fri, 9 May 2008 06:03:55 -0700
From: nathan binkert [EMAIL PROTECTED]
Subject: Re: [m5-users] Return Code
To: M5
That is very odd. Does the fault also occur if you put a[0] into a
temporary variable before sending it to printf? What compiler/library
are you using?
2008/5/10 fractal218 [EMAIL PROTECTED]:
hi,
I found why the error of panic: Page table fault when accessing virtual
address 0 will occur.
I don't believe that there is a fundamental reason that you can't
build M5 with visual studio 2008 or visual studio 2008 express (don't
try an earlier version). That said it would probably take a few days.
If you do decide to go down this road, please share your experience
with the list as I
Google for mercurial. It's a separate project.
Nate
On Mon, May 12, 2008 at 4:46 PM, Mike Anderson [EMAIL PROTECTED] wrote:
hi, thanks
But I can not find the mercurial manual in the m5 download page.
It is not in the linux-patches tarball .
thanks
May 12 2008
Message: 4
The statements are equivalent. It is written the way it is because it
can fail after just one comparison. In the version that you've shown,
two comparisons must be made.
Nate
2008/5/13 fractal218 [EMAIL PROTECTED]:
Hi,
Do you think the following program in function void
nathan binkert [EMAIL PROTECTED]:
I have a new tree based event queue that I've been using for several
months. A side effect of the new design is that it's now FIFO. I'll
get it committed when we get our source tree sorted out.
Nate
2008/5/13 Steve Reinhardt [EMAIL PROTECTED
s/multiprocessor/parallel/
2008/5/13 nathan binkert [EMAIL PROTECTED]:
It will be particularly important in multiprocessor simulation.
Nate
2008/5/13 Steve Reinhardt [EMAIL PROTECTED]:
Great. It'd still be nice to have the property that all significant
ordering constraints
I would like to pass an argument from the python front end to a rcS script
and I noticed that the M5ops page
(http://www.m5sim.org/wiki/index.php/M5ops) states that the initparam
utility is deprecated. Is there a functional replacement to initparam?
Not really. There is a workaround in
This is definitiely a problem with your setup and not a problem with
M5. What is the output of ls -l linux-latest.img? What about the
permissions of the parent directories?
I never run M5 as root and I use Ubuntu every day and have used it
on every version for the last 3 years.
Nate
On
I haven't done this in quite a while, but when I did cross tools, it
always fetched everything that was necessary for me. I believe that I
had to do something special to make that happen though.
Nate
On Wed, May 28, 2008 at 10:36 AM, Beckmann, Brad [EMAIL PROTECTED] wrote:
The wiki says the
Is there a way to pass config parameters to create a .rcS file to use those?
For example I want to pass the number of cpus parameters to the rcS file,
which will invoke the benchmark with that parameter.
There's no great way currently. I think the best option is to add
things to the linux
Which command do I modify to mount it in read/write mode?
You need to remove the copy on write disk image that's in there.
Basically, the disk model connects to the COW image which is layered
on top of the real image. If you instead just directly connect the
disk model to the real image, writes
You won't get a prompt if you ran one of the rcS scripts. If there is
no script to run, you get to a bash prompt.
Nate
On Wed, Jun 11, 2008 at 1:51 PM, Sujay Phadke [EMAIL PROTECTED] wrote:
I connect to M5 running in FS mode using m5term. It display all the console
output messages but I
Is it possible to quantify the accuracy of the memory timing model with a
real piece of hardware? Lets say we put in real numbers for the various
latencies and other parameters to make it close to a real SDRAM. Will it be
useful to run memory intensive benchmarks and see how the timing numbers
This question is not really related to m5 but general multicore design.
Since the number of processors in a multicorer system are constrained by
total chip area (400mm^2 for power4 etc), is there a way to estimate the area
of O3CPU based on certain parameters like size of LS Queues, reorder
Dear M5 Users,
Today, it is our pleasure to announce the public availability of the
M5 repository.
It was quite a bit of work, but we've managed to get the copyright
holders on M5 code to agree to a single BSD style license for M5. The
one major exception to this is the new x86 code. This code
So I downloaded and attempted a build and it gets pretty far but I get
the following error. Any ideas?
Must be Friday the 13th. I think I fixed the problem. Can you update
(hg pull -u) and recompile?
___
m5-users mailing list
m5-users@m5sim.org
I didnt understand what you mentioned about connecting a disk model
directly to the real image.
The lines from fsconfig.py are:
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk0.childImage(mdesc.disk())
Ah, I know what the problem is. I only committed half of the fix.
Ali's reversion is fine, and I'll fix it correctly later.
Nathan
On Tue, Jun 24, 2008 at 12:52 PM, Ali Saidi [EMAIL PROTECTED] wrote:
Hi Brad,
It seems that Nate was a little over-zealous with squashing swig
warnings. I've
The problem is that some of the regressions in the stable directory
require some outside files which you don't have. When we our previous
releases, we would remove those which we knew wouldn't work, but now
that we're releasing our repository, we need to fix our regression
framework to not error
Is it possible to put m5ops into a binary that is being simulated in m5
full system? In this case, I want very accurate timing of a getpid, and
want to do resetstats, the system call, and then dump stats. So it would
be nice if I could put these calls into a binary without actually
inacting
thanks. I know about the extras option. But if its used in the tests,
shouldnt it be included in the scripts?
The tests stuff in general is broken if you don't have everything in
place. In the past, we just didn't release that stuff, but now that
our repository is open, we have to fix it. It's
I've committed a new event queue datastructure that should greatly
improve simulator performance for those simulations that frequently
schedule many events at the same tick/priority. This was a pretty
common thing for me to do when I was building a mesh network model. I
suspect that in the
.
It is like nonuniform cache. When the L2 cache receives a different address
request, It assigns a different latency. Which codes describe such kind of
process?
Thanks
Gary
On Mon, Jul 14, 2008 at 3:28 PM, nathan binkert [EMAIL PROTECTED] wrote:
If I want to let the latency of accessing
Can you fix the wiki?
Thanks,
Nathan
On Thu, Jul 17, 2008 at 10:16 PM, Meng-Ju Wu [EMAIL PROTECTED] wrote:
Hi Ali,
Thank you very much. You are right. I should use
all_cpu_list.append('MyCPU') in the SConsopts file. I modified the
Sconsopts directly and didn't notice that I use
I want to run different benchmarks in different cpu in m5 full system
simulation. Does anybody have the experience? Please give me a help.
To do this, it's mostly writing scripts that run in the guest OS that
bind processes to CPU cores. This can be done with the
sched_setaffinity system call.
Gary (any everyone else for that matter),
Several of the M5 developers are currently working on ASPLOS papers
right now, so responses might be somewhat thin until the deadline has
passed.
The output that you have pasted is the output of the console (alpha's
version of BIOS). Basically the next
If an m5 simulation terminates due to a simulation limit being reached,
is it then possible that buffered I/O will not be sent out to the
terminal? I noticed that output appears to buffered for quite a while
until I see it hit the output terminal. Is there a simple way to flush
the output to
The statistics package seems to only support scalars that use integers.
The only double values I have seen are the result of a Formula type
being used. However, I would like to be add type double energy values
every cycle. Has any support for double been added to the scalar type?
There hasn't
The wiki is what I had in mind. I don't think you'd want to maintain a
bunch of contributions as you'd pretty much have to if you distributed
them because whatever disclaimer to the contrary, if they were in the
distro, someone would complain if one didn't work.
Starting with a wiki would be
These basically tell you about DMA transactions done for disk transfers.
iceaxe% cd m5/src
iceaxe% find . -name *.cc | xargs grep dma_read_bytes
./dev/ide_disk.cc:.name(name() + .dma_read_bytes)
iceaxe%
Hi, When I tried m5, I am not sure about the meaning of these metrics in
I want to run a full system simuation. There are two cores and each core
runs 2 thread. Can I run 4 benchmarks simultaneously and allocate one for
each thread? Only O3cpu supports SMT? Thanks.
Yes, and currently only O3 supports SMT. For examples of how to use
it, look at the SMT regression
Thanks for your response.
I work on fs simulation. Is there any sample python config file in m5 like
example/se.py to tell us how to set SMT? I assume it is a very different way
to use SMT workloads in fs and se simulation.
I don't know that anyone has worked on using SMT in full system, so
it passes p-max_insts_any_thread which is of Counter type and I'm a little
bit confused as to where the translation happens from Counter(which is an
instruction count) to Tick(which is in picoseconds). My purpose for this is
I'd like to create an Event that will be scheduled when a particular
All busses have a width parameter. Check out config.ini.
Nate
On Wed, Aug 27, 2008 at 3:00 PM, richard strong [EMAIL PROTECTED] wrote:
Hi,
I am trying to determine the bus width of the bus connected to a cache.
Is this just the address range of the port connected to the cache?
-Rick
If someone wants to give me an account on a machine with gcc 4.3 on
it, I will fix this problem before we ship the stable release. I
don't have the time to set it up on a new machine.
Nate
On Fri, Aug 29, 2008 at 4:28 PM, Meng-Ju Wu [EMAIL PROTECTED] wrote:
Hi all,
I got a better machine
That is a bug, there should be a function something like this in the
BPredUnit:
template class Impl
std::string
BPredUnitImpl::name() const
{
return cpu-name() + .BPredUnit;
}
Although the branch predictor doesn't have a cpu pointer so that would
have to be added as well. I don't
Thanks for your response. I do not use any share cache. In my configuration,
each processor has private L1 and private L2 cache. Then I want to find
which pages are accessed by processor 1 or processor 2. In this case, can
you give me some ideas?
I'd probably just create a big array in the
Actually, events should probably have the copy constructor disabled.
As Ali said, it just doesn't make sense.
Nate
On Thu, Sep 18, 2008 at 8:50 AM, Ali Saidi [EMAIL PROTECTED] wrote:
I think you have a misconception about the events. Events can be
reused, so as long as you don't have more
Given a physical address of a word i want to find out the complete
cache-line. Meaning i want to find out the lowest address and highest
address of the word which is mapped to that cache line.
Now one easiest apporach is to just find out the nearest multiples of
64byte(cache line size) above
Can you put the data that you have gathered so far up on the M5 twiki?
Perhaps with some explanation of how you got as far as you have? I'm
sure that some people would like to pick up where you left off.
Nathan
On Mon, Sep 22, 2008 at 4:06 PM, Meng-Ju Wu [EMAIL PROTECTED] wrote:
I had
Fantastic.
On Wed, Sep 24, 2008 at 2:44 PM, Meng-Ju Wu [EMAIL PROTECTED] wrote:
Sure. I will write a page to show how to run the SPEC2006 alpha binaries on
M5.
(1) How to build the alpha binaries.
(2) The SPEC2006 commands.
(3) The system configuration.
(4) Missing system calls.
(5) Done
Hi Meng-Ju,
This request comes up periodically. When I developed the stats
package, I intentionally made it so that it wasn't easy to get a stat
value out from C++ because stats can be reset or swapped at almost any
time, making it hard to use these values correctly. Generally, I tell
people
An internal compiler error is a problem with the compiler, not M5. I
suggest you use a different compiler.
Nate
On Mon, Sep 29, 2008 at 9:21 AM, Eduardo Olmedo Sanchez
[EMAIL PROTECTED] wrote:
Hi whem I'm compiling the m5 with this option scons USE_MYSQL=False
build/ALPHA_FS/m5.debug,
thanks for your answer. I'm using g++ 3.4.3 version, do you
recommend to update the g++ to another version or use another one different
than g++?. Thanks.
On Mon, Sep 29, 2008 at 9:49 AM, nathan binkert [EMAIL PROTECTED] wrote:
An internal compiler error is a problem with the compiler, not M5
.
On Mon, Sep 29, 2008 at 9:55 AM, nathan binkert [EMAIL PROTECTED] wrote:
A newer version should work fine. I think you just got unlucky with
your version number. We generally always compile with versions =
4.0, but I do compile with 3.4.6 on one machine and it works.
Nate
On Mon, Sep 29, 2008
I don't know if anyone has ever done this, but it would certainly be
interesting. I'm not sure if Alpha is going to be a problem with this
or not. Please keep us posted. I am very interested.
Nate
On Wed, Oct 8, 2008 at 8:42 AM, abc def [EMAIL PROTECTED] wrote:
I have an application
That's easily possible. Depending on which CPU model you use, you can
expect something like 1000x slowdown for SimpleAtomicCPU to 5x
slowdown for O3CPU.
Nate
On Wed, Oct 8, 2008 at 12:30 PM, Eduardo Olmedo Sanchez
[EMAIL PROTECTED] wrote:
Hi:
This is the first time that I simulate my
, is there any way that the M5 simulator can show me a little
of feedback of the simulation, number of cycles or how many of the
simulation lefts. Thank you.
On Wed, Oct 8, 2008 at 1:08 PM, nathan binkert [EMAIL PROTECTED] wrote:
That's easily possible. Depending on which CPU model you use, you
cscope (which of course only looks at the C++ code) and
found only the CPU option. So if it lives exclusively in Python and doesn't
have a help string then I could have missed it.
Steve
On Thu, Oct 9, 2008 at 8:06 AM, nathan binkert [EMAIL PROTECTED] wrote:
I still have it, I'll have to figure
could say
--progress=1GHz. At some point I was going to add this myself but never got
around to it.
Steve
On Thu, Oct 9, 2008 at 8:53 AM, nathan binkert [EMAIL PROTECTED] wrote:
There's m5.event.ProgressEvent.
It's not a command line option, the users's script would have to
create
Yes, this is true. Just so you know though, currently we only support
a very limited form of threading in SE mode right now to support
splash. I have lofty goals of getting pthreads working, but it will
be a few months. If you want to help, let me know. There is an
existing user level pthreads
You can certainly remove the -Werror. I'd like to know more if
possible. What version of G++? What version of swig? Can you send me
a copy of core_wrap.cc?
Thanks,
Nate
On Fri, Oct 10, 2008 at 12:09 AM, Dennis Yang [EMAIL PROTECTED] wrote:
Hi~
I try to install the new M5-2.0b6 simulator
Thanks for your reply~
My G++ version is 4.2.4.
The SWIG version is 1.3.29
However, I have successfully built M5 on another machine with G++ 4.1.1
If you still need my core_wrap.cc, please let me know.
I'd actually like to see it. I think this was because of the version
of swig, not gcc.
I don't quite understand the problem, but if there is a bug we need to
fix, a diff would be appreciated.
Nate
On Fri, Oct 24, 2008 at 2:46 PM, Shoaib Akram [EMAIL PROTECTED] wrote:
turns out that, changing
options.num_cpus=2
np=options.num_cpus
with np=2 was causing the problem...strange?
warning there ... ...
But I could be wrong...
On Wed, Oct 29, 2008 at 1:06 PM, nathan binkert [EMAIL PROTECTED] wrote:
I think that you're probably right that this number is too low.
Rather than just increasing this number, it would be nice if we could
move the instcount variable
Rick is correct. Kevin Lim started it, but never finished it. If
someone wanted to try to finish it up, that'd be great.
The idea of the ozone CPU was to create a CPU model that was an out of
order analog to the simple cpu model. Adding out of order allows this
model to get an MLP greater than
There are other options. You can do things like
foo.clock = 5 * Parent.clock.latency
This would mean that my clock is 5 times the latency of the clock of
any node found above me. And by found above, I mean, search the
object tree directly above me towards the root until I find something
that
There is no memtest directory under src/cpu/checker. There is one in
src/cpu/memtest. Did you accidentally move that directory?
Nate
On Wed, Nov 5, 2008 at 9:11 AM, Eduardo Olmedo Sanchez
[EMAIL PROTECTED] wrote:
Hello I have made some changes in the source code in the function
Are the block sizes of all of your caches the same? Can you fire up a
debugger and try to get more information about that assertion? What
are the two values that don't match? Are they both realistic numbers
or is one of them bogus.?
Nate
On Sun, Nov 2, 2008 at 2:32 PM, Paul [EMAIL
I'm pretty sure I've responded to this did you not investigate?
Look in /proc/meminfo
If MemFree + SwapFree is not greater than the number you've put in
that physmem times the number of physical memory objects you have plus
a couple hundred megabytes for M5 itself, you don't have enough
virtual
Can you explain to us why exactly you want to run i386 instead of x86_64?
On Wed, Nov 19, 2008 at 2:19 AM, Jack Whitham [EMAIL PROTECTED] wrote:
On Tue, Nov 18, 2008 at 08:35:50PM -0500, [EMAIL PROTECTED] wrote:
You are right that i386 programs won't work right now. There isn't anything
Cool. I suspect that this is your best bet. Glad you have things
working. We appreciate any comments or patches!
Nate
On Wed, Nov 19, 2008 at 8:55 AM, Jack Whitham [EMAIL PROTECTED] wrote:
On Wed, Nov 19, 2008 at 08:38:04AM -0800, nathan binkert wrote:
Can you explain to us why exactly
You are missing a #!/bin/sh at the top of your rcS file.
Yes, the disk image size shouldn't change. The disk image file is
always exactly the size of the disk that it represents. So, if you
want a 100GB disk, the image file would be 100GB. Some day, I'll add
the qemu qcow2 format, but not
Sorry for the late response, but there really isn't another disk
model. You should in theory be able to hang the disk device off
whatever bus memory hangs off of. You only need an io cache if you
want a separate IO bus.
Nate
On Wed, Nov 19, 2008 at 4:21 PM, Rick Strong [EMAIL PROTECTED]
There are people who have done this, but m5 itself currently only
provides the bus model. We hope to change this, but I'm not sure when
this will happen.
On Mon, Dec 8, 2008 at 11:34 PM, suixiufeng [EMAIL PROTECTED] wrote:
I have read some materials about the M5 simulator. It seems to me that
If the problem results from resuming from a checkpoint, I'd guess that
there's something still wrong with the serialization code. Try to
figure out where that address came from (turn on ExecTrace and search
for the address, then break on that cycle and figure out where it
comes from), and my
No, but there are things connected to the simple cpu that you might
not be scaling. There's the memory system, the devices, the frequency
of various interrupts, etc. In syscall emulation mode, there's not
much that needs to be scaled, but in full system, there's a whole lot.
Nate
On Mon,
M5 in SE mode doesn't support several of the system calls required for
implementing multithreading. To solve the problem, you need to
implement the system calls required by OpenMP. Also, depending on how
you want things to work, you might have to write a thread scheduler
for SE mode to load
Today I accidentally saw something called gem5 in the M5 repository with the
description 'M5 source code -- gems M5 integration'. If anybody can give me
a
brief explanation n current status of that it would be grateful. Hope M5
administrators will bear me being impatient and I apologies if
I want to find information about virtual memory in m5. Is there any code
in m5 related to such experiment? For example, I want to find the time
of the paging, and then set a delay to handle the paging. Can you give
some hints to deal with virtual memory in m5? Thank you.
It's not really clear
, Sitos Lin sitos@gmail.com wrote:
Hi:
I have built the page SpecOMP at
http://m5sim.org/wiki/index.php/SpecOMP. If anyone try the steps and
it doesn't work, please notice me. I will try to correct it. Thanks.
regards,
sitos
2009/2/10 nathan binkert n...@binkert.org:
I am not very sure
I am trying to run SPEC00 and SPEC06 on M5 FS mode (Alpha architecture,
Linux OS). I have the following questions:
(1): Can SPEC00 or SPEC06 be run on M5 FS mode?
If you can compile it, you should be able to run it.
(2): Is there any procedure I can follow to do that?
You basically just need
Hi Meng-Ju,
I'm just catching up on my inbox and I was wondering if you ever made
more progress on this that you can share.
Thanks,
Nate
On Wed, Oct 1, 2008 at 12:20 PM, Meng-Ju Wu mengj...@gmail.com wrote:
Hi Ali,
I know that my implementation of mremap() is not correct. I let
remap()
Generally, we don't checkpoint things that are timing related. Can
you use PhysicalMemory to generate your checkpoint and DRAMsim to
resume? Actually, resuming from a checkpoint wouldn't really work
then. Is DRAMsim not derived from PhysicalMemory?
Nate
On Wed, Feb 18, 2009 at 4:18 PM,
Hmm...it is derived from PhysicalMemory, so from that viewpoint all it
needs is to be rebuilt using the same parameters and have the
underlying PhysicalMemory data restored correctly. If PhysicalMemory
currently works with checkpointing, I am unclear what in my DRAMsim
code prevents it from
Veydan,
We're happy to have you ask questions on the mailing list, but can you
please in the future fix the subject line so it is actually
meaningful?
Thanks,
Nathan
On Fri, Feb 20, 2009 at 6:05 AM, Veydan Wu veyda...@gmail.com wrote:
Hi, could anybody tell me how exactly to build a image
I agree that there are way too few details, but from the sounds of the
message, he's editing files in the build directory. You should never
do that. You should only edit files in the source directory because
SCons will copy over them as you're seeing.
On Sat, Feb 21, 2009 at 1:48 PM, Steve
Do you have console=ttys0 in the boot_osflags configuration variable?
On Mon, Feb 23, 2009 at 4:30 AM, Veydan Wu veyda...@gmail.com wrote:
Hi, Ali, Thanks for you help. I have created a blank image and copy Gentoo
stage 3 in it. Everything seems OK, but when I used it to run M5 in FS mode,
I
--max-inst does not work with simple cpu? is there a way to stop a
simulation running simple cpu?
Steve,
If this indeed does not work, can you please submit a bug report to
the bug tracker?
Thanks,
Nathan
___
m5-users mailing list
Out of curiosity, are there any devices in /dev on the image? My
guess is that one of the steps in installing the image is to create
all of the devices. I'm don't have a good connection right now, and I
can't remember what I did, but take a look at the gentoo alpha
handbook and see if you can
Thanks for your replay, Ali. I read the file in src/arch/alpha/tlb*. The
only function that related to uncache access seems the checkCacheability()
that mark the uncache flag of a request.
This is correct. If you pick a memory range that will match for this
function (or modify the function),
Yes it is. You're suppose to change /dev/ROOT to, for instance,
/dev/hda1. The BOOT and SWAP lines you can probably just remove entirely.
I also suggest that you don't use gentoo's init scripts, but rather
implement your own init script. This is so you can know exactly what
applications are
Hi, Nate, thanks for your reply,the mismatch between req-getPaddr and
req-paddr makes me diffident to pick an address range for my own structure.
Do you mean that it's the problem of gdb, the M5 still works correctly? Can
I just change the req-getPaddr() to req-paddr ? I guess then the
You have to be careful to differentiate the physical address space
from the virtual address space. The stuff you got from isa_traits.hh
is virtual address space and describes the superpage stuff that you
can find in the processor documentation. the address with the high
bit set that you've
The bit that marks the address as an uncached access is 43 bit, in the
0x fdxx that you mentioned, it's the highest bit of the d.
I supposed that the 0x fcff is the address mask.
In this cace, how should I specify an uncached access address ? Can I
specify the
Does M5 support similar mechanism to allow me to access my own structure
from user code? I thought a cacheable address is not suitable for accessing
my own structure, so I want an uncached address. Thank you !
In general, things that work in Linux should work in M5 FS mode. We
actually run
Somehow your CXX environment variable is messed up. Do you have it
set to anything? Do you have g++ installed? (Just checking.) What
exact version of M5 are you running?
Nate
2009/3/2 Mingliang Liu lium...@gmail.com:
When I tried to run
scons build/ALPHA_SE/m5.debug
I got error as
HI, Nate, could you give some more specific hints on how to implement an
extra structure in M5 and get it accessd from user code?
What exactly are you trying to provide to user code? You may have
mentioned this a while ago, but I forgot.
The major problem
may be the address allocation, how
I am wondering if there has any way to disable some statistics
recorded in the m5stats.txt. Basically, I don't want to go into every
file and mask out the related codes. Could I set up something when
registering the statistic counter, then m5 will not print this counter
into the m5stats.txt?
Hi Gabe, thanks for your reply. Do you mean that the image should contain a
kernel like vmlinux or something like that ? If it doesn't contain one, then
I should compile one myself, is that right ?
I downloaded the stage3 from the net, how can I possibly know what kernel
they use?
Thanks
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