Serguey Zefirov schrieb:
Of course, Reduceron in ASIC will require some cache memory, some
controllers, etc. So it won't be that small, like 230K transistors.
But, mzke it 2.3M transistors and it still be 2 orders of magnitude
less than Core2 Duo... ;)
Cool! Do you have plans how it can be
2010/12/4 Henning Thielemann schlepp...@henning-thielemann.de:
Serguey Zefirov schrieb:
Of course, Reduceron in ASIC will require some cache memory, some
controllers, etc. So it won't be that small, like 230K transistors.
But, mzke it 2.3M transistors and it still be 2 orders of magnitude
I decided to calculate Reduceron's number of transistors (I had to, we
have some argument here;).
Reduceron allocate 14% of 17300 slices of Virtex-5 FPGA. If we assume
that each slice correspond to 8 4-input NAND-NOT elements, we will get
2 4-input NAND. Each 4-input NAND contains 8
