On May 1, 2012, at 6:39 AM, Andrew Rowley and...@blackhillsoftware.com wrote:
I have read a few articles that say that multiple periods are not recommended
for batch service classes. Multiple periods seems to be considered a bit old
fashioned.
I haven't been able to find anything clearly
On Sun, Apr 15, 2012 at 12:29 PM, Micheal Butz michealb...@optonline.netwrote:
I am getting S0C4 04 within a wait which leads me to believe that the
storage key of the ECB storage key is not the same as the PSW STORAGE KEY
8- 11. Does the following code make sense to resolve this address
On Wed, Apr 11, 2012 at 1:07 PM, Micheal Butz michealb...@optonline.netwrote:
There is a reason I have CSA in KEY 8
Was just wondering If I have to do an explicit modeset to key=8
What you're doing is just stupendously wrong. As a privileged program, you
don't NEED to use key 8 storage and
On Apr 2, 2012, at 10:46 AM, R.S. r.skoru...@bremultibank.com.pl wrote:
The same with unauthorized code - maybe the system is not bulletproof, but we
have no documented case of such flaw.
Sorry, but you are totally wrong there. Absence of publicized cases does not
imply absence of
On Mon, Apr 2, 2012 at 4:32 PM, Binyamin Dissen
bdis...@dissensoftware.comwrote:
The various exits run in SRB mode. As a pants and suspenders guy, I would
like
to have the task receive a notification from the system if the SRB and its
FRR
fail.
SRB to TCB percolation is a feature that the
While z/OS is probably immune to executables being introduced from
outside, how vulnerable is
This really isn't a safe assumption, so all of the subsequent questions are
kind of irrelevant. Yes, it is possible to configure a z/OS system so that it
is extremely difficult to break into, but
On Mar 28, 2012, at 4:13 PM, R.S. r.skoru...@bremultibank.com.pl wrote:
The problem is we don't believe. :-)
W dniu 2012-03-28 22:45, Ray Overby pisze:
Yes, I believe I have a way to attack a mainframe system where I don't
have access.
Then would you believe me?
In the days before
On Sun, Mar 11, 2012 at 8:07 AM, John Gilmore johnwgilmore0...@gmail.comwrote:
Since this sort of thing is expected of me, I will note that we find
ourselves between Scylla and Charybdis here.
Chris Craddock's formulation was open to the exception that Peter
Relson took: there is
On Mar 8, 2012, at 1:15 PM, Ray Overby ray.ove...@kr-inc.com wrote:
Rob - How about: If your authorized program while executing in PSW Key 0-7
stores into an address provided by an unauthorized caller (as long as the
store operation uses the execution PSW KEY) then this is a violation of the
So basically, you're planning to create a product and you want us to describe
how to do it?
Sent from my iPad
On Mar 7, 2012, at 3:51 PM, Ed Mackmahon dropip...@gmail.com wrote:
Many thanks for your answers.
Let me provide some more information
I intend that the interface will logon to
On Tue, Feb 21, 2012 at 2:15 PM, Micheal Butz michealb...@optonline.netwrote:
If I adding the STOKEN of another address to either my DU-AL PASN-AL can I
specify PUBLIC on the ALESERV macro and bypass the authorization)
Typically when I get the alet of another address I do a AXSET to give
On Tue, Feb 21, 2012 at 7:01 PM, Charles Mills charl...@mcn.org wrote:
Also remember when perusing the LE publications that the inventors of LE in
their wisdom thought it would be too clear to the uninitiated to call the
languages dependent on Language Environment languages, choosing instead
On Tue, Feb 21, 2012 at 3:45 PM, Micheal Butz michealb...@optonline.netwrote:
Would any know the difference between (disabled reference storage) DREF
e.g.
subpool 215 and Page fixed storage e.g. subpool 223
From what I understand DREF means the program is running disable for
interrupts and
On Thu, Feb 16, 2012 at 3:33 PM, Scott Ford scott_j_f...@yahoo.com wrote:
Tony,
I dont want to knock IBM but for us developers this is UGLY ...
Maybe the problem is they never intended for it to be called that way ...
Yes, exactly right on both counts. Don't forget that TSO is older than
On Wed, Feb 15, 2012 at 2:55 PM, McKown, John john.mck...@healthmarkets.com
wrote:
If you really want do this this: run an APF authorized TSO command from a
COBOL program, even one which is linked AC=1. Well, you'll need to cheat
horribly. One way to cheat is to run your COBOL program under
On Mon, Feb 13, 2012 at 7:00 AM, Veilleux, Jon L veilleu...@aetna.comwrote:
I think that this paragraph is interesting:
We were previously using configuration management version control, which
required a lengthy code check-in process, said Clark Dudek, software
developer, IBM Systems and
On Mon, Feb 13, 2012 at 8:56 AM, Paul Gilmartin paulgboul...@aim.comwrote:
On Mon, 13 Feb 2012 07:21:11 -0600, McKown, John wrote:
Or, as the programmers at our shop would do:
SPACE=EAT-EVERYTHING-IN-SIGHT-AND-CAUSE-OTHER-JOBS-TO-ABEND-BECAUSE-MY-STUFF-IS-IMPORTANT-AND-YOUR-STUFF-ISNT.
On Feb 12, 2012, at 1:22 AM, Edward Jaffe edja...@phoenixsoftware.com wrote:
On 2/11/2012 8:31 AM, Dave Day wrote:
The idea of hiring temporary workers, the 'liquid' people referred to in the
article, seems to me to be at odds with long term, successful growth.
It's hard for me to
On Jan 25, 2012, at 9:08 AM, David Andrews d...@lists.duda.com wrote:
But what also caught my eye was unusually large CPU consumption by the
*MASTER* address space: 60-75% continuously while his sort was
executing. He cancelled it, and *MASTER* went back to its usual docile
self.
What is a
On Wed, Jan 18, 2012 at 11:25 AM, Leonard D Woren ibm-ma...@ldworen.netwrote:
snip
Which reminds me. ENQ/DEQ LINKAGE=SVC cannot be issued by AR mode
callers. Guess how I discovered that...
That has always been true for all SVCs unless specifically documented
otherwise.
The exception that
On Jan 5, 2012, at 5:48 PM, Graham Harris harris...@gmail.com wrote:
Intel Core i7 at 177,730 MIPs/sec
http://en.wikipedia.org/wiki/Instructions_per_second
or almost 180BIPs/sec ... which makes i7 equivalent of more than three
z196??
Interesting to read the cited reference against the
Steve, Peter is (of course) right. You're struggling with cases where most
people generally miss the distinction between the hardware architecture and
the software architecture implemented by any given control program. The
hardware knows nothing at all about what you would think of as
On Oct 27, 2011, at 8:19 PM, Micheal Butz michealb...@optonline.net wrote:
Would anyone know how to test the RTM routine of a SRB when I issue a
schedule even though SRB activity is asynchronous it takes off automatically
Michael, you're really playing with fire. Before you try any of that,
On Tue, Oct 18, 2011 at 10:20 AM, Micheal Butz michealb...@optonline.netwrote:
Is all that's required for setting a recovery routine for the SRB is
setting
a address in SRBFRRA ?
http://bama.ua.edu/archives/ibm-main.html
At the risk of sending you off on another tangent, yes.
But, what
ok, ok, I admit it! I know.
(sheesh, you guys)
Sent from my iPad
On Oct 16, 2011, at 11:37 PM, Shane ibm-m...@tpg.com.au wrote:
On Sun, 16 Oct 2011 13:07:26 -0700Edward Jaffe wrote:
Would anyone know if the SRB routine SRBEPA has to reside in common
No.
Lol - c'mon Ed, *some-one*
On Sun, Oct 16, 2011 at 4:53 PM, Micheal Butz michealb...@optonline.netwrote:
The normal sequence then is common when scheduling to a different address
space
just think about it for a minute. There is no magic. Put yourself in the
SRB's place. In order for it to run, the code has to be
On Mon, Oct 17, 2011 at 11:31 AM, Sam Siegel s...@pscsi.net wrote:
On Mon, Oct 17, 2011 at 9:27 AM, Chris Craddock crashlu...@gmail.com
wrote:
On Sun, Oct 16, 2011 at 4:53 PM, Micheal Butz michealb...@optonline.net
wrote:
snip On the other hand; If you are trying to schedule an SRB
On Mon, Oct 17, 2011 at 5:31 PM, Shmuel Metz (Seymour J.)
shmuel+ibm-m...@patriot.net wrote:
In
cakxahqwwofk2cmeed1akporkeytzvz-_iq5pk1kmi3bb8fx...@mail.gmail.com,
on 10/17/2011
at 11:27 AM, Chris Craddock crashlu...@gmail.com said:
On the other hand; If you are trying to schedule
No, you werent where you thought you were in the code. The system doesn't lie
about what happened. You can't issue any SVC instructions while you have an
FRR on the stack, regardless of what kind of FRR you have. And don't forget you
may be calling other system services whether you're aware of
Changing an allocated DDNAME is a recipe for a train wreck. Just don't.
The Allocation component is older than dirt. If you were meant to be able to do
such a thing there would be an interface for it.
Chris Craddock
Sent from my cell phone
281-770-1950
On Oct 7, 2011, at 12:29 PM, John
with MSM there was a conscious decision to follow IBM support policies, which
makes sense if you think about it. I have no idea whether anyone is running it
in an unsupported config. I would point out that if a vendor says release X is
required, it usually means just that. You can go off and
) cross memory
environment. Beware that the hardware will let you do LOTS of things that z/OS
doesn't formally support.
Chris Craddock
Sent from my iphone
On Aug 8, 2011, at 7:06 AM, Donald Likens dlik...@infosecinc.com wrote:
I need to update common storage from my IEFU85 SMF exit. I am
On Wed, Jul 20, 2011 at 10:18 AM, Paul Schuster pgs4ibmm...@pacbell.netwrote:
Hello:
The manual 'z/OS V1R12.0 MVS Assembler Services Guide' has this statement:
The case where an SDWA is not provided
is rare.
Is there a way to force this kind of condition in order to actually test an
ESTAE
On Sun, Jul 17, 2011 at 2:45 PM, michealbutz michealb...@optonline.netwrote:
Hi,
I have seen these terms EUT Enabled Unlocked Task /FRR and this my
understanding
I ASSUME Enabled means Enabled for I/O interrupts BIT 6 of Psw the only
way I know how
to set this is with the LPSW inst
On Thu, 23 Jun 2011 11:01:56 -0400, Andy Coburn a...@andycoburn.com wrote:
I question Walt's statement above in one case and one case only. The quote
below is from the z/OS V1R11 manual Using Data Sets SC26-74410-09:
quote
...snipped (by Walt)...
Note: VSAM OPEN routines bypass RACF
On Wed, Jun 15, 2011 at 6:50 AM, Micheal Butz michealb...@optonline.netwrote:
What if you Have a ss pc rtn and want to access data and inst from the
program that issued the ss pc rtn
That only takes a little bit of design forethought. Home-space ASC mode is
probably the last thing you should
On Fri, Apr 15, 2011 at 4:17 PM, michealbutz michealb...@optonline.netwrote:
Hi,
Would anyone know if installing a Address Space Terminating routine via
RESMGR works Under
all circumstances
Meaning normal Termination
Yes, Memory Termination resource managers always get control (in
On Tue, Apr 5, 2011 at 10:50 AM, Tom Marchant m42tom-ibmm...@yahoo.comwrote:
It is worth noting that the system provides a 144-byte save area when
a program is ATTACHed, as for example when a job step program is given
control.
true, and somewhat ironic given that it is one of the few
On Mon, Mar 14, 2011 at 5:38 PM, Stan Weyman stan.wey...@emc.com wrote:
having been down this road on numerous occasions I think Rob has it pretty
much nailed IMHO. Please send check payable to Rocket Software, etc,
etc... G
yeah bright lad is our Rob. The key takeway is if you fetch
On Tue, Feb 22, 2011 at 11:19 AM, Tony Lubrano tony.lubr...@neon.comwrote:
Yes...
LRx,PSAAOLD-PSA(,R0)
LRx,ASCBASXB-ASCB(,Rx)
LRx,ASXBITCB-ASXB(,Rx)
LRx,TCBFSA-TCB(,Rx)
LRx,SA_R1(,Rx)
CLC =CL4'ECP',0(Rx)
JEIMS BMP
CLC =CL6'DFSRRC',20(Rx)
JEIMS MPP
If you
On Tue, Feb 8, 2011 at 2:43 PM, Charles Mills charl...@mcn.org wrote:
Ah Binyamin, you are a man of few, but cogent, words. Thanks! Looks like
the
answer to my second question: how do permanent load?
Anyone have an answer to my first question (which is mooted if CSVDYLPA
lives up to its
On Fri, Feb 4, 2011 at 9:38 AM, Rob Scott rsc...@rocketsoftware.com wrote:
TCBTTIME is *not* updated when task is actually dispatched and executing on
a CPU, only when it gets interrupted by something like WAIT.
TCBTTIME will not include any fancy CPU stats either (Enclave SRB, zIIP
and
On Fri, Feb 4, 2011 at 10:38 AM, Charles Mills charl...@mcn.org wrote:
@Chris: Interesting. Do you suppose the technique you describe is cheaper
than TIMEUSED with ECT?
Hard to tell without benchmarking it and I wouldn't offer a
prediction. *HOWEVER* if you are of a mind to sample relevant
On Thu, Jan 27, 2011 at 12:19 PM, michealbutz michealb...@optonline.netwrote:
Would anyone know in what scenario
HOME id not = PRIMARY is not = SECONDARY
For any given unit of work HASN *never* changes. Initially PASN=SASN=HASN. A
space switch PC branches into another address space, so
On Thu, Jan 27, 2011 at 3:31 PM, Edward Jaffe
edja...@phoenixsoftware.comwrote:
On 1/27/2011 2:51 PM, Edward Jaffe wrote:
Instructions are always fetched from primary (see PoO).
Sorry. It is possible to fetch instructions from home if you switch to
home-space ASC mode.
Does anyone have any analysis (which can be shared) related to SuperC's
Search-For CPU usage?
Its not exactly a gauzy sheer chiffon dress, but who cares? You're only
going to use it now and then (when you need it) on moderate sized datasets
right?
--
This email might be from the
artist
On Thu, Dec 23, 2010 at 1:06 PM, Robert A. Rosenberg hal9...@panix.comwrote:
At 12:31 -0500 on 12/23/2010, Tony Harminc wrote about Re: X-memory POST
question:
On 23 December 2010 09:43, Binyamin Dissen bdis...@dissensoftware.com
wrote:
On Thu, 23 Dec 2010 08:30:25 -0500 Peter Relson
My question was that if you have an SVC that does stuff, can it use RACF to
check if a user has permissions? Based on your kind replies to my query,
the answer is yes.
Yes, it isn't just for dataset security. You can ask security questions
about any logical resource, even ones you make up
On Wednesday, December 22, 2010, Micheal Butz michealb...@optonline.net wrote:
Would anyone know what subpool load loads into
Yes.
--
This email might be from the
artist formerly known as CC
(or not) You be the judge.
--
For
On Wednesday, December 22, 2010, Mike Schwab mike.a.sch...@gmail.com wrote:
Speak of the Devil, and he makes time magazine.
http://newsfeed.time.com/2010/12/22/internet-legend-tron-guy-banned-from-seeing-tron-legacy-in-famous-suit/
My wife pointed that out to me and she was utterly shocked
On Mon, Dec 20, 2010 at 8:36 AM, Micheal Butz michealb...@optonline.netwrote:
Hi,
The paramd paramter on the SETFRR
Macro when adding a FRR you give FRR a address where to return a pointer to
a 24 byte area
Where would set what info you want passed to your recovery routine in the
24 byte
On Fri, Dec 17, 2010 at 8:20 AM, Dr. Stephen Fedtke
max_mainframe_...@fedtke.com wrote:
hi all,
if a programcode does not know anything about its environment, and needs to
determine its privilege level/status (i.e. problem or supervisor state,
key), it could use TESTAUTH. fact is that
On Wed, Dec 15, 2010 at 1:22 PM, Lorne Dudley dudl...@queensu.ca wrote:
I'm having problems getting the following batch program to run correctly.
It's running from an authorized library and abends with 0C4, reason code 4.
The book says the key of the storage area that the running program
On Wed, Dec 15, 2010 at 4:06 PM, Richard L Peurifoy r-peuri...@neo.tamu.edu
wrote:
On 12/15/2010 3:23 PM, Chris Craddock wrote:
Ok. Don't do it. It is basically a bad idea. While that field was
originally intended for user (i.e. customer) use, in practice it is
unusable. If you want
On Fri, Dec 10, 2010 at 6:50 AM, Peter Relson rel...@us.ibm.com wrote:
IOW, a PC-SS cannot examine the callers addresses via VSMLOC?
Correct, at least using documented interfaces (since secondary and home
ASC modes are not part of the documented programming interface, and as
such might or
On Thu, Dec 2, 2010 at 3:18 AM, Binyamin Dissen
bdis...@dissensoftware.comwrote:
On Thu, 2 Dec 2010 13:26:15 +0930 Anthony Thompson
anthony.thomp...@nt.gov.au wrote:
:ASCBINTS would be job start time, not current step.
True.
Oops. My bad. I didn't notice you wanted the step time. I don't
On Wed, Dec 1, 2010 at 10:25 AM, Tony Harminc t...@harminc.net wrote:
On 1 December 2010 10:46, Edward Jaffe edja...@phoenixsoftware.com
wrote:
You can use an ordinary branch instruction (e.g., BASSM 14,15) to branch
to
code above the bar. If you're running enabled, you won't execute for
On Wed, Dec 1, 2010 at 2:11 AM, Ron Hawkins
ron.hawkins1...@sbcglobal.netwrote:
If I remember rightly it was a bug in IMS 2.2 or 2.3. If I remember
correctly NAB (where I worked at the time) had found the bug in stress and
regression testing (TPNS for those that remember it) and were waiting
IIRC there is a field which has the timestamp of when the current step
started, but I cannot seem to find it.
ASCBINTS
--
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(or not) You be the judge.
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For IBM-MAIN
On Tue, Nov 30, 2010 at 10:39 PM, Chase, John jch...@ussco.com wrote:
-Original Message-
From: IBM Mainframe Discussion List On Behalf Of Shane
As if.
Can't you just imagine a major Aussie Bank doing that. You were at
Bank
of NSW when they had the IMS fiasco Steve - how much
On Tue, Nov 30, 2010 at 9:43 PM, Gerhard Adam gada...@charter.net wrote:
How would you branch to code above the 2GB bar, since none is allowed
there?
The obvious problem being how you would even get it loaded up there. If I
recall, the fundamental problem is that the PSW cannot be saved with
the E and L -
or
perhaps especially because of the E and L form - that I feel prompted
to
suggest a step further than the course proposed by Chris Craddock.
This step is, having studied the E and L forms of the macro, ditch the
pesky things and just code what is necessary in raw
On Sun, Nov 14, 2010 at 4:02 PM, Sam Siegel s...@pscsi.net wrote:
Hello,
What is the most efficient way to coordinate work in a synchronous fashion
between a problem state TCB and an enclave SRB? Pause, release? Wait,
Post, Latch services? Other?
The enclave SRB will be scheduled into
On Sun, Nov 14, 2010 at 4:30 PM, Sam Siegel s...@pscsi.net wrote:
On Sun, Nov 14, 2010 at 2:22 PM, Chris Craddock crashlu...@gmail.com
wrote:
If both are operating synchronously in the same address space, why
bother
to introduce the SRB (and communication/synchronization overhead) at
all
On Fri, Nov 5, 2010 at 6:58 AM, Micheal Butz michealb...@optonline.netwrote:
I know the field SDWASTAE tests for recursive entry for Esate(s) is there
to test for recursive entry for FRR's
there's no such thing as a recursive entry to a recovery routine. When an
error occurs the FRR stack
On Tue, Nov 2, 2010 at 11:24 AM, Robert A. Rosenberg hal9...@panix.comwrote:
At 09:32 -0400 on 11/02/2010, Charles Mills wrote about WTO ABEND D23 help:
There is a field in the WTO MF=L commented as WPX length. It assembles
as
104=x'68' and it's still x'68' in the dump. I don't find WQEBLK
On Sat, Oct 30, 2010 at 9:07 PM, Micheal Butz michealb...@optonline.netwrote:
Sorry by 2 I meant 1 parameter and 1 MVS Service DETACH
yes there ARE actually two parameters that you can specify that will result
in you having to issue DETACH for yourself.
ECB (as already noted) specifies the
Mike Butz writes:
If a main program uses a Estae rtn then does Multiple Attaches specifying
the same ESTAE rtn on the ESTAI parm of the attach can the recovery routine
determine the abending TCB
If you are getting control in any non-FRR recovery routine (ESTAI, ESTAE(x)
or ARR) then the
On Fri, Oct 15, 2010 at 10:43 AM, Ricc Harding ricc.hard...@gmail.comwrote:
SPFCopy's magic SVC went thru several iterations to make it secure too.
It
was one of those SVC's that was written to be serially secure but in
a
multi-tasking environment when two or more tasks could be set up
On Thu, Oct 14, 2010 at 11:13 AM, Bob Shannon
bshan...@rocketsoftware.comwrote:
I would think it means code that front-ends one of the First Level
Interrupt Handlers
That's how Amdahl implemented SE and SP assist years ago. I think IBM did
it to implement the IEEE floating point
On Thu, Oct 14, 2010 at 4:17 PM, Larry Crilley
larry.cril...@dino-software.com wrote:
Sure. I just want to determine if a page is fixed. I'm not saying I want
to free/unfix it. I just want to know...
so far as I know, there is no way to tell in general. There are some obvious
corner
On Tue, Oct 12, 2010 at 8:55 AM, Chris Mason chrisma...@belgacom.netwrote:
The archaic IEFSDPPT module is still valid, but for all practical
purposes it is
unusable.
Unusable for all except IBM would be more accurate - although implied by
your
emphasis on vendors. As far as I can tell
On Sat, Oct 9, 2010 at 12:20 PM, Chris Mason chrisma...@belgacom.netwrote:
Chris
[1] Your presentation doesn't actually mention a SCHEDxx entry as an
alternative to or override for a PPT entry - tut! tut!.
Erm... tut me no tuts! PPT entries are defined in SCHEDxx.
Erm. How about
On Wed, Oct 6, 2010 at 9:45 PM, Chris Mason chrisma...@belgacom.net wrote:
Edward
I detect some failure properly to make an effort to understand the point
*I*
was trying to make!
snip
[1] Your presentation doesn't actually mention a SCHEDxx entry as an
alternative to or override for a
Does anyone know if TESTAUTH runs in XMEM mode PASN not equal SASN
No it does not. You have to be in primary asc mode and with PASN=SASN=HASN
--
This email might be from the
artist formerly known as CC
(or not) You be the judge.
Tom, Chuck and Ed wrote:
On 9/9/2010 4:35 PM, Chris Craddock wrote:
yeah I know, I just didn't feel like going off on one of my normal
rants
about integrity exposures. It seems like nobody listens anyway.
and on 9/15/2010 Ed Jaffe wrote:
Some of us do... :-)
Yep. When Chris
On Thu, Sep 9, 2010 at 8:39 AM, Charles Mills charl...@mcn.org wrote:
Yeah, it's documented bottom-up and in the wrong place. APF is not an
authorized assembler service. APF authorization is in the realm of
operations and security, not assembler programming. Sure, it impacts
assembler
On Thu, Sep 9, 2010 at 3:39 PM, Tony Harminc t...@harminc.net wrote:
On 9 September 2010 12:39, Chris Craddock crashlu...@gmail.com wrote:
... I'd like a dollar for every loadlibrary that has AC(1) sprayed around
like confetti...
snip
Every one of those wished-for dollars is a potential
In response to Charles, Rob Scott said:
What SDSF is doing here is using the MGCRE service with the CART parameter
(the CART is the command response token) to send the operator command to
an EMCS console.
The expectation in most cases is that the code that eventually executes in
whatever
On Wed, Sep 1, 2010 at 8:56 AM, Charles Mills charl...@mcn.org wrote:
Wow, is this all confusing. (And yes, I imagine maintaining the source --
two sources, assembler and PL/S, right? -- for GETMAIN is even more
confusing.)
So STORAGE is just GETMAIN in disguise. I knew it provided the same
On Thu, Jul 29, 2010 at 1:39 AM, Edward Jaffe
edja...@phoenixsoftware.comwrote:
Amlan Prasad wrote:
hi,
Has anyone come across or heard of or actually worked on technical design
in mainframe where memory/address/data can be passed or shared in parallel
by two different jobs?
Yes. We do
On Thu, Jul 29, 2010 at 11:03 AM, Mark Steely mark.ste...@wnco.com wrote:
I have a ZFS file which is larger than a 3390 mod 2 volume. I would like
to split this file to fit on 2 3390 mod 2 volumes. What would the best
way to do this.
We are z/OS V1R11. Any help would be appreciated.
PDSEs have only one advantage: snip
Well, they do have at least one other advantage: they can store
program objects, which allows entry points with long, case-sensitive
names, which is sometimes handy.
http://bama.ua.edu/archives/ibm-main.html
No not really. Longer names may be
On Fri, Jul 16, 2010 at 12:10 PM, Rick Fochtman rfocht...@ync.net wrote:
Ben, that's very sound advice, but the exit writeing person MUST be aware
of any restrictions in the invoking environment. One example: you WILL use
the branch entry to WTO if you need to write messages to the operator
On Tue, Jul 13, 2010 at 10:01 AM, Hal Merritt hmerr...@jackhenry.comwrote:
For the opening shot in this, I'd argue: yes. While no system can ever be
totally idiot proof, human intervention can be counted on as a failure mode.
Besides, it should have taken more than one idiot to do the job.
On Mon, Jul 12, 2010 at 4:52 AM, Binyamin Dissen bdis...@dissensoftware.com
wrote:
Say I would like to get control when a specific PRB ends (while the TCB
remains). Are my choices to either poll or modify the return PSW?
There is no system service or exit that (directly) does what you
Perhaps I'm missing something here, but couldn't this be nicely done in
IEFDB401?
Some code would be necessary to rattle through the dynamic allocation
parameter
list, but on an allocation request, find the DSN (if present) and DISP (if
present)
and then, do the actual ENQ on SYSDSN
On Mon, Jul 5, 2010 at 10:48 AM, Paul Gilmartin paulgboul...@aim.comwrote:
On Mon, 5 Jul 2010 08:48:38 -0600, Robert Raicer wrote:
You have it just about right. When the sole remaining RB for the TCB
issues SVC-3 (EXIT), End of Task processing begins. This causes RTM
Does an RB issue
:In other words Can the communication ECB be posted in the subtasks as
well
I wouldn't think so a it is in key0 storage, but as there is bypass code
for
wait perhaps there is also bypass code for post.
The communications ECB is indeed in key 0 storage, but the system recognizes
attempts
On Mon, Jun 14, 2010 at 4:04 PM, McKown, John john.mck...@healthmarkets.com
wrote:
I don't like versions in LNKLST datasets.
I have no problem with them in maintenance or steplibs.
But, regardless of the HLQ, they should not have versioning
in the production environment, IMO.
I agree
On Tue, May 25, 2010 at 12:31 PM, McKown, John
john.mck...@healthmarkets.com wrote:
Depends. What are they running? How do they measure up time? We are still
stuck in the 1970s for all intents and purposes. We run CICS with VSAM. No
RDMS. No Websphere. 100% COBOL. We do run some 3270 screen
On Thu, May 20, 2010 at 2:15 PM, Art Celestini spamb...@celestini.comwrote:
A colleague has written me about a set of circumstances he is observing:
Program “A” is authorized, running in Key 7, TCB mode, and issues a LINK
for
Program “B”. When Program “B” gets control, it finds PSATOLD=0 and
On Wed, May 12, 2010 at 8:31 AM, Shane Ginnane ibm-m...@tpg.com.au wrote:
mounts hobbyhorse
As has been discussed here before, seems every half-baked software
developer (and more than a
few fully baked ones) seem to think ASID 1 is the perfect place to drop a
long lived RB rather than
make
On Wed, May 12, 2010 at 12:28 PM, Rick Fochtman rfocht...@ync.net wrote:
-snip-
Notice that I said Legal. Nothing else is supported by the z/OS software
architecture - regardless of whether something else is possible under the
On Tue, May 11, 2010 at 9:52 AM, Ray Overby rayove...@comcast.net wrote:
My understanding is if the target address space is non-swappable then you
can safely use non-srb code to obtain access to the other address space's
private area. I believe the unpredictability comes when the target
On Mon, May 10, 2010 at 4:37 PM, Rick Fochtman rfocht...@ync.net wrote:
-snip
Highly unlikely unless I'm missing something obvious. The only LEGAL way to
access memory in some other address space is via an SRB. You need to be in
On Sun, May 9, 2010 at 9:16 PM, Lorne Dudley dudl...@queensu.ca wrote:
The October 2001 issue of the Xephon MVS Update 181 contained REXX Cross
Memory assembler subroutine code allowing access to information in other
memory spaces by ASID.
I was never able to get this to operate properly.
On Fri, May 7, 2010 at 2:13 PM, Blaicher, Chris chris_blaic...@bmc.comwrote:
I have a TCB and a SRB process and want to suspend one and let the other
proceed and then reverse it and do that over and over.
The following pseudo code assumes knowledge of
IEAVAPE/IEAVPSE/IEAVXFR/IEAVRLS/IEAVDPE:
On Wed, Apr 28, 2010 at 12:58 PM, Kirk Talman rkueb...@tsys.com wrote:
what is the size (in mips?) are the datacenters or companies that it takes
to make the 1st, 2nd ... quintile? Is that published?
well if you figure on a single z10-EC engine being O(1K) old fashioned
meaningless thingies
On Sat, Apr 24, 2010 at 2:17 PM, Binyamin Dissen bdis...@dissensoftware.com
wrote:
: There is no way to dance around it or pretend
:otherwise. The only way you could avoid the exposure would be to
guarantee
:that no authorized code code could ever run within the
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