Hi,
Can anyone explain to me the significance of the ACCESS parameter on the
ALESERV MACRO
THANKS
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Hi,
Does AL=PASN on the ALESERV macro mean that the ALET is available to all
address spaces
Which is the same concept LXRES with SYSTEM=YES
Correct ??
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is
available to all units of work in the pasn address space.
--Dave
On 6/12/2012 7:09 AM, Micheal Butz wrote:
Hi,
Does AL=PASN on the ALESERV macro mean that the ALET is available to all
address spaces
Which is the same concept LXRES with SYSTEM=YES
Correct
Hi,
It's been a while since I scheduled an SRB If I use any IBM services in a
SRB I use the branch entry from but I just looked at some documentation
Cross memory for beginners
And it seems PC rtns are also okay in SRB mode didn't specify SSWITH (space
switch or not)
Just wanted to
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Of Micheal Butz
Sent: 10 June 2012 16:30
To: IBM-MAIN@bama.ua.edu
Subject: SRB mode question
Hi,
It's been a while since I scheduled an SRB If I use any IBM services in a
SRB I use the branch entry from but I just looked
Thank you
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Tony Harminc
Sent: Monday, April 23, 2012 6:25 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: EXTRACT,QEDIT macro
On 23 April 2012 17:30, Micheal Butz michealb...@optonline.net wrote
Thank you
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Gerhard Postpischil
Sent: Monday, April 23, 2012 8:49 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: EXTRACT,QEDIT macro
On 4/23/2012 5:30 PM, Micheal Butz wrote:
If after issuing
Hi,
I have a question regarding the usage of the Extract Qedit macros for
operator communication
I have started task looking to process a Flush Or Modify command via the
com/cib the pointer to the CIB is just for the current task
If after issuing the EXTRACT to get the address of the
Hi,
Was wondering If someone could clear up some things for me
A S0C4 reason code 4 means the storage key and the PSW key don't match
typically trying to access storage key 0 when the PSW key is key 8
Two questions arise from this
. Does it matter what the PSW key at the
Hi,
I am getting S0C4 04 within a wait which leads me to believe that the
storage key of the ECB storage key is not the same as the PSW STORAGE KEY
8- 11
Does the following code make sense to resolve this address
TESTAUTH FCTN=1 TEST APF AUTORIZATION
the key as determined by IVSK, why not
simply do it in Key 0?
On Sun, 15 Apr 2012 13:29:55 -0400 Micheal Butz michealb...@optonline.net
wrote:
:Hi,
:
:
:
:
:
: I am getting S0C4 04 within a wait which leads me to believe that the
:storage key of the ECB storage key is not the same as the PSW
: System completion code 201
On Tue, 10 Apr 2012 18:07:28 -0400, Micheal Butz michealb...@optonline.net
wrote:
Hi
I have a piece of CSA storage sp 241
That I am obtaining in key 8
(I know this is a no no)
When go to supervisor state should i code KEY=NZERO on the modeset I am
assuming
NZERO is 8
Hi
I have a piece of CSA storage sp 241
That I am obtaining in key 8
(I know this is a no no)
When go to supervisor state should i code KEY=NZERO on the modeset I am assuming
NZERO is 8 or should I specifically set the storage key to 8
As I am getting a system 201 durning a post/wait of an ECB
Hi,
I just got a hit and generated an SVC dump from a SLIP Storage Alteration
My memory sort of escapes me on what IPCS option I would find the culprit
that caused the storage overlay
From memory I do believe it would be one of the IPCS traces if someone could
help
I would
===
From:
Micheal Butz michealb...@optonline.net
To:
IBM-MAIN@bama.ua.edu
Date:
04/06/2012 03:42 PM
Subject:
SLIP PER Sotroage Alteration SVC dump
Sent by:
IBM Mainframe Discussion List IBM-MAIN@bama.ua.edu
Hi,
I just got a hit and generated an SVC dump from a SLIP
www.identityforge.com
On Apr 4, 2012, at 12:35 AM, Alan Altmark alan_altm...@us.ibm.com wrote:
On Tue, 3 Apr 2012 12:01:47 -0400, Micheal Butz michealb...@optonline.net
wrote:
When I get incoming connection via SELECT/ACCEPT I move the low order ½ from
retocde from the accept call which is the new
Hi,
I have an assembler concurrent server using the EZASMI interface, I am using
4 ports from my IP address 192.168.1.111 I do a socket,bind listen using
ip,port,socket
I create four subtasks (ATTACH) to process connection on these 4 ports, I
pass these task a parameter list of KEY 8 subpool
Hi,
I am trying to debug a TCP/IP server as a template I am using the following
flow chart from a document by Tony Thigpen
http://dinomasters.com/coolstuff/2004EZA.pdf
My Client is a Windows MFC C++ program
I have multiple connections going as per the document
The accept macro
Hi,
I have a two folded question First on debugging a TCP/IP program using the
EZASMI interface. Second a question about the EZASMI ACCEPT service
. I have been writing TCP/IP started task to communicate with
Windows MFC C++ The Assembler started task uses the EZASMI
Hi,
I am having problems with following coding generating a re-entrable version
of the WTOR below is the relvant code
LTORG
DEBUG_MESS DC C'THE BASE ADDRESS IS '
TBL DC240X'00'
DCC'0123456789ABCDEF'
this functionality.
Rob Scott
Lead Developer
Rocket Software
275 Grove Street * Newton, MA 02466-2272 * USA
Tel: +1.781.684.2305
Email: rsc...@rs.com
Web: www.rocketsoftware.com
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Of Micheal Butz
Sent: 19 March 2012 14:07
To: IBM-MAIN@bama.ua.edu
Subject: Re: WTOR problem
Rob,
I understand that however moving the model *statement* would be sufficient
if I coded WTOR MF=(E,WTOR_LIST) By coding
WTOR TEXT=(D_MSG,REPLYAREA,REPLY_LEN,REPLY_ECB),MF=(E,WTO_D_LX
ST
* Newton, MA 02466-2272 * USA
Tel: +1.781.684.2305
Email: rsc...@rs.com
Web: www.rocketsoftware.com
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: 19 March 2012 14:07
To: IBM-MAIN@bama.ua.edu
Subject: Re: WTOR problem
Rob,
I
Hi,
I am looking for information on the use of enclave SRB/TCB's maybe an
example of the usage
Thanks
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Sent: 16 March 2012 15:35
To: IBM-MAIN@bama.ua.edu
Subject: Enclave SRB's
Hi,
I am looking for information on the use of enclave SRB/TCB's maybe an
example of the usage
Thanks
-Original Message-
From: Micheal Butz michealb...@optonline.net
To: IBM-MAIN IBM-MAIN@bama.ua.edu
Sent: Tue, Mar 6, 2012 8:30 pm
Subject: Re: LAE instruction
Or a more practical use of LAE
s chaing thru control blocks from another address space
AC. 512
AM R3,R3
Hi,
I have two part question regarding the LAE instruction
. What would the sac value e.g. 256,512,768 have to be that when
using the LAE instructions with the following operands LAE 3,0(R4) would
AR3 get loaded with AR4
. Second what value does the displacement play
Software
275 Grove Street * Newton, MA 02466-2272 * USA
Tel: +1.781.684.2305
Email: rsc...@rs.com
Web: www.rocketsoftware.com
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: 06 March 2012 19:05
To: IBM-MAIN
Email: rsc...@rs.com
Web: www.rocketsoftware.com
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: 06 March 2012 19:59
To: IBM-MAIN@bama.ua.edu
Subject: Re: LAE instruction
Thanks
Regarding my questions
Sorry misspelled the name John McKown. Excuse me
Sent from my iPhone
On Mar 6, 2012, at 4:00 PM, Micheal Butz michealb...@optonline.net wrote:
John Mckiwns reply was a explanation of the SAC inst.Which I am aware of
The Doc for LAE says the inst the functionality is dependent on PSW
@bama.ua.edu] On Behalf Of Micheal Butz
Sent: Tuesday, March 06, 2012 3:00 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: LAE instruction
John Mckiwns reply was a explanation of the SAC inst.
Which I am aware of
The Doc for LAE says the inst the functionality is dependent
on PSW bits
16 17
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From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: Tuesday, March 06, 2012 3:07 PM
To: MVS List Server 1
Subject: Re: LAE instruction
Sorry misspelled the name John McKown. Excuse me
Sent from my iPhone
On Mar 6, 2012, at 4:00 PM, Micheal Butz michealb
But plays no role as far as access register value
Sent from my iPhone
On Mar 6, 2012, at 3:48 PM, Shmuel Metz (Seymour J.)
shmuel+ibm-m...@patriot.net wrote:
In 02fb01ccfbcb$fca77eb0$f5f67c10$@net, on 03/06/2012
at 02:04 PM, Micheal Butz michealb...@optonline.net said:
. What
Grove Street * Newton, MA 02466-2272 * USA
Tel: +1.781.684.2305
Email: rsc...@rs.com
Web: www.rocketsoftware.com
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: 06 March 2012 21:53
To: IBM-MAIN@bama.ua.edu
275 Grove Street * Newton, MA 02466-2272 * USA
Tel: +1.781.684.2305
Email: rsc...@rs.com
Web: www.rocketsoftware.com
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: 06 March 2012 21:53
To: IBM-MAIN@bama.ua.edu
PC
NUMBER
2B00 The Following PC number is for LX or linkage index 0 as The
high order 0's signify
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Peter Relson
Sent: Sunday, March 04, 2012 8:32 AM
To:
Hi,
I am trying to track some storage allocation thru IPCS using VSMDATA
There are four data areas described by VSMDATA DQE (descriptor Queue
element) FQE (free queue element)
SPQE (subpool queue element) SPQA (subpool queue anchors)
The DQE describes storage allocated
Got it
Sent from my iPhone
On Mar 4, 2012, at 1:47 PM, Ray Overby rayove...@comcast.net wrote:
Assuming this data is produced by a summary format in IPCS I believe the LX
is 2B and the EX is 00.
On 3/4/2012 11:46 AM, Micheal Butz wrote:
PC
NUMBER
2B00
Hi,
I got a return code of X'15' from ATTACH JSTCB=YES
14
Meaning: Program error. An authorized task that
specified JSTCB=YES is not a job step task.
, 4 Mar 2012 16:31:44 -0500 Micheal Butz michealb...@optonline.net
wrote:
:Hi,
:
:
:
:I got a return code of X'15' from ATTACH JSTCB=YES
:
:
:
:
:
:
:
:
:14
I ran it as command processor TESTAUTH ' ' CP
And it worked
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: Sunday, March 04, 2012 5:00 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Return code = X'14' from
Hi
Does anyone know how to display the linkage tables from an IPCS dump assuming I
dump PCAUTH address space
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Hi,
Does the TCBTQE contain the TQE (time slice for that task to run)
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Are these created by Z/OS or by the user or both
Sent from my iPhone
On Feb 26, 2012, at 3:50 PM, Edward Jaffe edja...@phoenixsoftware.com wrote:
On 2/26/2012 12:04 PM, Micheal Butz wrote:
Does the TCBTQE contain the TQE (time slice for that task to run)
TCBTQE points to the chain of TQEs
- DUCT
On Thu, 23 Feb 2012 20:35:52 -0500 Micheal Butz michealb...@optonline.net
wrote:
:In a ipcs dump where can I see a TCBs. DU-AL
:
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In a ipcs dump where can I see a TCBs. DU-AL
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Please explain I/O should not be done to DREF using DREF storage as buffer
area for I/O
When I used sysplex IXG macros to obtain member information the doc said use
DREF storage
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Edward
doc very carefully, and then use FIXED
storage unless the doc clearly explains why DREF will work.
Bill Fairchild
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From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: Wednesday, February 22, 2012 2:52 AM
To: IBM-MAIN
: Re: Difference between DREF storage and Page fixed storage
On 2/22/2012 12:51 AM, Micheal Butz wrote:
Please explain I/O should not be done to DREF using DREF storage as
buffer
area for I/O
Anything referenced by the I/O channel program should be fixed.
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Hi,
Would anyone have a link to POP's book/PDF with 64 bit instructions
thanks
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Hi,
If I adding the STOKEN of another address to either my DU-AL PASN-AL can I
specify PUBLIC on the ALESERV macro and bypass the authorization)
Typically when I get the alet of another address I do a AXSET to give myself
authorization to go there
Would adding PUBLIC entry for the ALET
Hi,
Would any know the difference between (disabled reference storage) DREF e.g.
subpool 215 and Page fixed storage e.g. subpool 223
From what I understand DREF means the program is running disable for
interrupts and thus no pagIing should occur so the doc say use DREF storage
While fixed
, 2012 at 2:15 PM, Micheal Butz
michealb...@optonline.netwrote:
If I adding the STOKEN of another address to either my DU-AL PASN-AL can I
specify PUBLIC on the ALESERV macro and bypass the authorization)
Typically when I get the alet of another address I do a AXSET to give
myself
authorization
Hi,
I know that if a program is re-entrant a subsequent ATTACH will use that
address as the entry point.
How about a non-reentrant program
If I do a ATTACH DISP=NO is the attached program LOADED and if so is there a
way to find the entry point
Hi
Again if I do a attach with disp=no
And r1 has the tcb address I can look at the TCBRBP or relating CDE for the
loadpoint of the module
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Hi,
I know EXTRACT FIELDS=COMM (using the ECB) for stop or modify command works
for the TCB your running dunning the course of my programming
I attach 4 other subtasks is there any parameter on the ATTACH e.g. like
ALCOPY( work for access lists) where I can share COMECBPT among subtasks
Hi,
Would anyone know how to subscribe to the assembler list
Thanks
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Do CICS Global User exits have to be loaded In CSA
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no
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From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Micheal Butz
Sent: Monday, January 09, 2012 3:52 PM
To: IBM-MAIN@bama.ua.edu
Subject: Cics Global User Exit
Do CICS Global User exits have to be loaded In CSA
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Yes Are Global Exits loaded in CSA
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From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Edward Jaffe
Sent: Sunday, January 08, 2012 1:21 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Debugging CICS Global User Exits
On 1/7/2012 8:12 PM, Micheal
Hi,
I have assembled and enabled CICS exit XEIIN It is my understanding that it
should get invoked whenever a CICS api is encountered
However this doesn't seem to be the case if anyone could shed some light on
this I would appreciate it
thsnks
Hi,
Would anyone know the best method to debug CICS Global User Exits For MVS I
usually used XDC
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Hi,
If I do 4 attaches to the same program then there will be only one copy of
the program
But each TCB will have its own set of RB's indicating where each task is to
resume processing
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2012 15:09:01 -0500 Micheal Butz michealb...@optonline.net
wrote:
:If I do 4 attaches to the same program then there will be only one copy of
:the program
If RENT.
:But each TCB will have its own set of RB's indicating where each task is
to
:resume processing
Yes.
In fact, ATTACH terminates
How about when the TCBs CPU time slice is up and control
Is given up to a different task
Thanks
Sent from my iPhone
On Dec 22, 2011, at 8:16 AM, Peter Relson rel...@us.ibm.com wrote:
Would anyone know what the differences at a point in time between the
values in TCBGRS and The Values of
FIRST dispatched but later on is the RB constantly updated
Sent from my iPhone
On Dec 22, 2011, at 3:59 PM, Shmuel Metz (Seymour J.)
shmuel+ibm-m...@patriot.net wrote:
In db25ced1-64e1-4611-ac68-b68776669...@optonline.net, on 12/22/2011
at 08:30 AM, Micheal Butz michealb...@optonline.net
Hi,
Would anyone know what the differences at a point in time between the
values in TCBGRS and The Values of the registers in XRBREGS of the RB
pointed to by TCBRB
I am assuming of course TCBRB is the currently executing RB
THANKS
Hi,
Would anyone know how to test the RTM routine of a SRB when I issue a
schedule even though SRB activity is asynchronous it takes off automatically
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From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Peter Relson
Sent: Sunday, October 23, 2011 10:06 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SRBEPA
There is not much of a real difference. SQA will even overflow into CSA.
It is a
Cann't a Authorized program do a ATTACH JSTCB=YES
anytime
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Of Wayne Driscoll
Sent: Saturday, October 22, 2011 8:29 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: z/OS Control block question
@bama.ua.edu
Subject: Re: SYSTEM ABEND CODE 0F8 REASON CODE 0014 under TESTAUTH
On Tue, 18 Oct 2011 00:26:08 -0400 Micheal Butz michealb...@optonline.net
wrote:
:I am trying to issue a branch entry form of a macro in a other address
:space since the specifications say PASN=HASN=SASN
Which macro
Does that mean subpool 227 as opposed to to 241
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From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Jim Mulder
Sent: Monday, October 17, 2011 4:03 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SRBEPA
IBM Mainframe Discussion List
Page fault that means it does't have to be fixed unless I just don't get it
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Of Shmuel Metz (Seymour J.)
Sent: Monday, October 17, 2011 6:32 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: SRBEPA
In
I am issuing a branch entry form of a macro, in the SRB
So for the SRB control block 241,
For the SRB code 227
Thank you for all your help
-Original Message-
From: IBM Mainframe Discussion List [mailto:IBM-MAIN@bama.ua.edu] On Behalf
Of Chris Craddock
Sent: Monday, October 17,
Hi,
I am trying to establish a FRR in a TSO command processor program that is
not re-entrant this is because
Later I schedule a SRB and I want to use the routine I established as a FRR,
as input to the SRBFRRA parameter
While tracing thru TESTAUTH
After establishing a breakpoint
I didn't issue any SVC
The code blew up under TESTAUTH at the fifth instruction after the
expansion of the SETFRR macro
I normally get 0F8 when I am in XMEM mode and issue a SVC I didn't abended
on a SVC I abended whitin STM of the SETFRR inst
-Original Message-
From: IBM
, 2011, at 10:07 PM, Micheal Butz michealb...@optonline.net
wrote:
I didn't issue any SVC
The code blew up under TESTAUTH at the fifth instruction after the
expansion of the SETFRR macro
I normally get 0F8 when I am in XMEM mode and issue a SVC I didn't abended
on a SVC I abended whitin
Does anyone know if the SRB rtn has to live common
Thanks in advance
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Sent: Sunday, October 16, 2011 06:04 AM
To: IBM-MAIN@bama.ua.edu IBM-MAIN@bama.ua.edu
Subject: SRBEPA
Does anyone know if the SRB rtn has to live common
Thanks in advance
Sent from my iPhone
Micheal Butz michealb...@optonline.net
wrote:
:Thats what I thought there was a
:Document XMEM for beginners which said both the SRB and SRB rtn EPA have to
be in common
The routine only has to be addressable in the target address space.
:On Oct 16, 2011, at 6:46 AM, Tom Harper
Hi,
Would anyone know if the SRB routine SRBEPA has to reside in common
thanks
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Hi,
Does anyone know if the SRB routine SRBEPA has to reside in common
thanks
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Hi,
Would anyone know when issuing the following console command
D A,JOBNAME and OWT is displayed under M/S column
What does OWT stand for ?
thanks
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, 16 Oct 2011 07:09:07 -0400 Micheal Butz michealb...@optonline.net
wrote:
:Thats what I thought there was a
:Document XMEM for beginners which said both the SRB and SRB rtn EPA have
to be in common
The routine only has to be addressable in the target address space.
:On Oct 16, 2011, at 6:46 AM
is certainly simpler.
Your questions are asking what is possible. Perhaps you might be asking
what is best practice, or, even better, tell us what you are trying to
accomplish.
Tom
- Original Message -
From: Micheal Butz [mailto:michealb...@optonline.net]
Sent: Sunday, October 16, 2011 03:30
Hi.
I know you can'nt issue SVC from a. SRB however PC rtn's are allowed
My question is can that PC rtn issue a
SVC
Thanks
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Hi,
I have piece of code that I am running in my program as a SRB the question I
have is the following the
The addressability to this piece of code is that by the base register
established at entry to this program or the code gets control at SRBEPA has
the entry point pointed to by
Hi,
The following is a description from SYSEVENT
ENTRY=SVC for the following SYSEVENTs:
DONTSWAP OKSWAP
TRANSWAP STGTEST
Hi
I have a program I am trying to debug that issues TPUTS so I have to use the CP
parm however it has input paramters and they are not passed when using the CP
parm
Any help appreciated
Thanks
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Sent: Thursday, October 06, 2011 3:18 PM
To: IBM-MAIN@bama.ua.edu
Subject: TSO TEST Debugging with TPUT and input paramters
Hi
I have a program I am trying to debug that issues TPUTS so I have to use the
CP parm however it has input paramters and they are not passed when using
Debugging with TPUT and input paramters
On 6 October 2011 17:29, Micheal Butz michealb...@optonline.net wrote:
When entering the command paramters are they surrounded by quotes
Generally, no. But you have to enter what the command is expecting,
and it's possible that it wants a quoted string.
Are you
Hi,
The OUCB control Block seems to contain information about Virtual storage
swapping.
Would anybody know if that's per page Of Virtual Storage, meaning
ASCBOUCB-OUCB-VITUALSTORAGE PAGE IN THAT AS
While if I were to issue a SYSEVENT DONTSWAP macro
All pages of Virtual Storage in
I am looking at a distributed header in memory well the first 2 bytes are
the length of the header meaning if there any long names in this header they
are encompossed in the length
At offset +4 I can see the Requester name for 16 bytes the offset for this
field at offset +1c I can see QWHDSVNM
I have a question regarding the product section The documentation says that
the product section can have may headers seems like there is always a
Standard header, but then the other header might also be present
(correlation, distributed, cpu) my question is if the other headers are
present were
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From:
Micheal Butz michealb...@optonline.net
To:
IBM-MAIN@bama.ua.edu
Date:
09/09/2011 00:55
But bascally they perform the same functions
Sent from my iPhone
On Aug 22, 2011, at 11:07 AM, Binyamin Dissen bdis...@dissensoftware.com
wrote:
On Mon, 22 Aug 2011 08:35:06 -0400 Micheal Butz michealb...@optonline.net
wrote:
:Would any one the difference between the the SYNCH LINK
Does that mean sync doesn't have to be associated with a CDE
Sent from my iPhone
On Aug 22, 2011, at 11:07 AM, Binyamin Dissen bdis...@dissensoftware.com
wrote:
On Mon, 22 Aug 2011 08:35:06 -0400 Micheal Butz michealb...@optonline.net
wrote:
:Would any one the difference between
by the LOAD or LINK SVC routine).
Mike Myers
Mentor Services Corporation
On 08/23/2011 07:03 AM, Micheal Butz wrote:
Does that mean sync doesn't have to be associated with a CDE
Sent from my iPhone
On Aug 22, 2011, at 11:07 AM, Binyamin Dissen bdis...@dissensoftware.com
wrote:
On Mon, 22
If I have a peice of code that was MVCL somewere it can'nt be the
object of synch/synch
Sent from my iPhone
On Aug 23, 2011, at 12:12 PM, john gilmore john_w_gilm...@msn.com
wrote:
Binyamin Dissen has already made the crucial point: LINK[X]
specifies a name (or alias); SYNCH[X]
In a earlier post John Gilmore wrote as long as the copy is
refershable reusable the Info is kept in the CDE
Sent from my iPhone
On Aug 23, 2011, at 2:47 PM, Gerhard Postpischil gerh...@valley.net
wrote:
On 8/23/2011 1:05 PM, Micheal Butz wrote:
If I have a peice of code that was MVCL
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