Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add an interface to dynamically change the cache level

2011-03-30 Thread Chris Wilson
The series looks really good, only one quibble below. On Tue, 29 Mar 2011 16:59:53 -0700, Eric Anholt e...@anholt.net wrote: +int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, + enum i915_cache_level cache_level) + if (cache_level ==

[Intel-gfx] [PATCH] drm/i915: Reset GMBUS controller after NAK

2011-03-30 Thread Chris Wilson
Once a NAK has been asserted by the slave, we need to reset the GMBUS controller in order to continue. This is done by asserting the Software Clear Interrupt bit and then clearing it again to restore operations. If we don't clear the NAK, then all future GMBUS xfers will fail, including DDC

Re: [Intel-gfx] [PATCH] drm/i915: Reset GMBUS controller after NAK

2011-03-30 Thread Chris Wilson
On Wed, 30 Mar 2011 09:48:25 -0700, Keith Packard kei...@keithp.com wrote: On Wed, 30 Mar 2011 17:07:11 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: +clear_err: + I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); + POSTING_READ(GMBUS1 + reg_offset); + I915_WRITE(GMBUS1 +

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add an interface to dynamically change the cache level

2011-03-30 Thread Eric Anholt
On Wed, 30 Mar 2011 08:09:47 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: The series looks really good, only one quibble below. On Tue, 29 Mar 2011 16:59:53 -0700, Eric Anholt e...@anholt.net wrote: +int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, +

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add an interface to dynamically change the cache level

2011-03-30 Thread Chris Wilson
On Wed, 30 Mar 2011 09:59:55 -0700, Eric Anholt e...@anholt.net wrote: On Wed, 30 Mar 2011 08:09:47 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: The series looks really good, only one quibble below. On Tue, 29 Mar 2011 16:59:53 -0700, Eric Anholt e...@anholt.net wrote: +int

Re: [Intel-gfx] [PATCH] drm/i915: Reset GMBUS controller after NAK

2011-03-30 Thread Keith Packard
On Wed, 30 Mar 2011 17:59:51 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: I'm not even sure we need the first posting read. Maybe it should be a wait_for(I915_READ(GMBUS1 + reg_offset) GMBUS_SW_CLR_INT, 100) to be clearer that we are simply giving the hardware the chance to assert

[Intel-gfx] vsync on ttys with KMS

2011-03-30 Thread Felix Miata
I run all my displays, LCD or not, at 60 vertical refresh. Flicker is a non-issue for these old eyes. Is there a way to force the kernel to use 60, or find out what is being used? On the p275 Trinitron I'm using right now, I doubt fc15's 2.6.38.2 is running 60, as the output is shifted so far

[Intel-gfx] [PATCH 3/9] drm/i915: Remove the PCH paths from the pre-Ironlake crtc_mode_set().

2011-03-30 Thread Eric Anholt
Signed-off-by: Eric Anholt e...@anholt.net --- drivers/gpu/drm/i915/intel_display.c | 284 +++--- 1 files changed, 24 insertions(+), 260 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7b2cd8a..d955646

[Intel-gfx] [PATCH 2/9] drm/i915: Move the vblank pre/post modeset to the common crtc_mode_set.

2011-03-30 Thread Eric Anholt
Signed-off-by: Eric Anholt e...@anholt.net --- drivers/gpu/drm/i915/intel_display.c | 16 ++-- 1 files changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 610363c..7b2cd8a 100644 ---

[Intel-gfx] [PATCH 4/9] drm/i915: Drop the eDP paths from the pre-Ironlake crtc_mode_set.

2011-03-30 Thread Eric Anholt
While g4x had DP, eDP came with Ironlake, so we don't need that code here. Signed-off-by: Eric Anholt e...@anholt.net --- drivers/gpu/drm/i915/intel_display.c | 57 ++--- 1 files changed, 24 insertions(+), 33 deletions(-) diff --git

[Intel-gfx] [PATCH 1/9] drm/i915: Split the crtc_mode_set function along HAS_PCH_SPLIT() lines.

2011-03-30 Thread Eric Anholt
This path, which shouldn't be *that* complicated, is now so littered with per-chipset tweaks that it's hard to trace the order of what happens. HAS_PCH_SPLIT() is the most radical change across chipsets, so it seems like a natural split to simplify the code. This first commit just copies the

[Intel-gfx] [PATCH 8/9] drm/i915: Clean up leftover DPLL and LVDS register choice from pch split.

2011-03-30 Thread Eric Anholt
We used to have these from the product of (pch, non-pch) * (pipe a, pipe b). Now we can just use the nice per-pipe reg macros in the split out crtc_mode_sets. Signed-off-by: Eric Anholt e...@anholt.net --- drivers/gpu/drm/i915/intel_display.c | 57 +- 1 files

[Intel-gfx] [PATCH 9/9] drm/i915: Fold the DPLL limit defines into the structs that use them.

2011-03-30 Thread Eric Anholt
They're used in one place, and not providing any descriptive value, with their names just being approximately the conjunction of the struct name and the struct field. This diff was produced with gcc -E, copying the new struct definitions out, moving a couple of the old comments into place in the

[Intel-gfx] [PATCH 6/9] drm/i915: Drop non-HAS_PCH_SPLIT() code from ironlake_crtc_mode_set().

2011-03-30 Thread Eric Anholt
Ironlake is where the PCH split started. Signed-off-by: Eric Anholt e...@anholt.net --- drivers/gpu/drm/i915/intel_display.c | 361 ++ 1 files changed, 150 insertions(+), 211 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH] drm/i915: use i915_enable_rc6 on SNB too

2011-03-30 Thread Jesse Barnes
For debug testing. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c |9 ++--- 1 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 32b41b4..1268c6a

Re: [Intel-gfx] [PATCH] drm/i915: use i915_enable_rc6 on SNB too

2011-03-30 Thread Ben Widawsky
On Wed, Mar 30, 2011 at 02:08:56PM -0700, Jesse Barnes wrote: For debug testing. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- I915_WRITE(GEN6_RC_CONTROL, -GEN6_RC_CTL_RC6p_ENABLE | -GEN6_RC_CTL_RC6_ENABLE | +rc6_mask |

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Add an interface to dynamically change the cache level

2011-03-30 Thread Eric Anholt
On Wed, 30 Mar 2011 18:16:11 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: On Wed, 30 Mar 2011 09:59:55 -0700, Eric Anholt e...@anholt.net wrote: On Wed, 30 Mar 2011 08:09:47 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: The series looks really good, only one quibble below.

Re: [Intel-gfx] [PATCH 3/9] drm/i915: Remove the PCH paths from the pre-Ironlake crtc_mode_set().

2011-03-30 Thread Jesse Barnes
On Wed, 30 Mar 2011 13:01:04 -0700 Eric Anholt e...@anholt.net wrote: Signed-off-by: Eric Anholt e...@anholt.net --- drivers/gpu/drm/i915/intel_display.c | 284 +++--- 1 files changed, 24 insertions(+), 260 deletions(-) Was going to suggest you also drop the

Re: [Intel-gfx] [PATCH] drm/i915: Reset GMBUS controller after NAK

2011-03-30 Thread Jesse Barnes
On Wed, 30 Mar 2011 17:07:11 +0100 Chris Wilson ch...@chris-wilson.co.uk wrote: Once a NAK has been asserted by the slave, we need to reset the GMBUS controller in order to continue. This is done by asserting the Software Clear Interrupt bit and then clearing it again to restore operations.

Re: [Intel-gfx] [PATCH] drm/i915: use i915_enable_rc6 on SNB too

2011-03-30 Thread Jesse Barnes
On Wed, 30 Mar 2011 14:32:51 -0700 Ben Widawsky b...@bwidawsk.net wrote: On Wed, Mar 30, 2011 at 02:08:56PM -0700, Jesse Barnes wrote: For debug testing. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- I915_WRITE(GEN6_RC_CONTROL, -

Re: [Intel-gfx] reduced LLC caching series

2011-03-30 Thread Michael Larabel
Eric Chris, For those interested, here's some of my test results of the LLC caching patch-set compared to a vanilla 2.6.38 and 2.6.39-rc1 on two SNBs. They just show some nice gains across the board and I haven't hit any issues with the patches. Core i3 2100: