Re: [Intel-gfx] [PATCH 21/21] drm/i915: Introduce vmap (mapping of user pages into video memory) ioctl

Thanks for excellent comments... Skipping to the end for a quick response: On Mon, 18 Apr 2011 16:58:17 +0200, Daniel Vetter dan...@ffwll.ch wrote: I have hopes that we might be able to subsume that use-case into the single-shot use-case by beefing up pwrite/read with a blt variant that does

[Intel-gfx] [PATCH 1/7] drm/i915: color range only works on pre-ILK

ILK+ provides this feature in the transcoder and pipe configuration instead. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_hdmi.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c

[Intel-gfx] [PATCH 3/7] drm/i915: set bpc for DP transcoder

This may not be the default value, so pull the bpc out of the pipe reg and write it to the DP transcoder so proper dithering and signaling occurs. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_display.c |3 ++- 1 files changed, 2 insertions(+), 1

[Intel-gfx] [PATCH 7/7] drm/i915: use pipe bpp when setting HDMI bpc

The Intel HDMI encoder can support 8bpc or 12bpc. Set the appropriate value based on the pipe bpp when configuring the output. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org --- drivers/gpu/drm/i915/intel_hdmi.c |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git

[Intel-gfx] [PATCH 1/5] drm/i915: downgrade non-lethal BUG_ONs

If it's a simple gem accounting error that won't lead to immediate harm (like a NULL-deref) or is a simple violation of a required invariant that the caller should always check/ensure, downgrade the BUG_ON to a WARN_ON and hope the system survives long enough to grab the dmesg. Signed-off-by:

[Intel-gfx] [PATCH 3/5] drm/i915: check gpu_write_list in move_to_flushing

The corresponding WARN_ON with opposite sign already exists in move_to_inactive, hence add it here for symmetry. I've actually hit this while hunting down bugs in various pipelined fencing patches. Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/i915_gem.c |1 +

[Intel-gfx] [ANCIENT PATCH] Enable 30-bit depth

Signed-off-by: Andy Lutomirski l...@mit.edu --- This patch is over a year old, caused problems, and probably doesn't even apply anymore. It worked at least a little bit, though. There's a lot more that needs doing, especially in relation to DirectColor mode. src/intel_driver.c |5 +++--

Re: [Intel-gfx] [ANCIENT PATCH] Enable 30-bit depth

On Tue, 19 Apr 2011 15:50:01 -0400 Andy Lutomirski l...@mit.edu wrote: Signed-off-by: Andy Lutomirski l...@mit.edu --- This patch is over a year old, caused problems, and probably doesn't even apply anymore. It worked at least a little bit, though. There's a lot more that needs doing,

[Intel-gfx] [PATCH 2/3] drm/i915: Attach a fb to the load-detect pipe

We need to ensure that we feed valid memory into the display plane attached to the pipe when switching the pipe on. Otherwise, the display engine may read through an invalid PTE and so throw an PGTBL_ER exception. For bonus amusement value, we perform the first load detect before even

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Check that the plane points to the pipe's framebuffer before enabling

On Tue, 19 Apr 2011 21:32:01 +0100 Chris Wilson ch...@chris-wilson.co.uk wrote: Knut Petersen reported a GPU hang when he left x11perf running overnight. The error state quite clearly indicates that plane A was enabled without being fully setup: PGTBL_ER: 0x0010 Display A: Invalid

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Attach a fb to the load-detect pipe

On Tue, 19 Apr 2011 21:32:02 +0100, Chris Wilson ch...@chris-wilson.co.uk wrote: We need to ensure that we feed valid memory into the display plane attached to the pipe when switching the pipe on. Otherwise, the display engine may read through an invalid PTE and so throw an PGTBL_ER