On Tue, Jul 08, 2014 at 03:26:36PM -0700, bradley.d.vol...@intel.com wrote:
+void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool)
+{
+ struct drm_i915_gem_object *obj, *next;
+
+ WARN_ON(!mutex_is_locked(pool-dev-struct_mutex));
+
On Tue, Jul 08, 2014 at 03:26:38PM -0700, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
It provides some useful information about the buffers in
the global command parser batch pool.
v2: rebase on global pool instead of per-ring pools
Include the counts in
On Tue, Jul 08, 2014 at 03:26:36PM -0700, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
This adds a small module for managing a pool of batch buffers.
The only current use case is for the command parser, as described
in the kerneldoc in the patch. The code is
From: Deepak S deepa...@linux.intel.com
This is useful for userspace utilities to verify and micromanaging the
increase/decrease frequncy.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_sysfs.c | 18 +++---
1 file changed, 15 insertions(+), 3
From: Deepak S deepa...@linux.intel.com
Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt for verifying the freq on
VLV and CHV
Deepak S (7):
drm/i915: Read guaranteed freq for valleyview
drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs
drm/i915: keep freq/opcode
From: Deepak S deepa...@linux.intel.com
We need mem_freq or cz clock for freq/opcode conversion
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 29
From: Deepak S deepa...@linux.intel.com
Since freq/encode conversion formula changes from platform to platform,
create a generic wrapper function and having platform check inside this
help to simpilfy adding newer platform freq/opcode conversion.
Signed-off-by: Deepak S deepa...@linux.intel.com
From: Deepak S deepa...@linux.intel.com
Enabled PM interrupt programming for CHV. Re-using gen8 code and extending same
for CHV.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5
From: Deepak S deepa...@linux.intel.com
Reading RP1 for valleyview to help us enable pm_rps i-g-t testcase
execution.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 16
1 file changed, 16 insertions(+)
diff --git
From: Deepak S deepa...@linux.intel.com
Adding chv specific fre/encode conversion.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 68 +++--
1 file changed, 59 insertions(+), 9 deletions(-)
diff --git
From: Deepak S deepa...@linux.intel.com
This is useful for userspace utilities to verify and micromanaging
the increase/decrease frequncy.
Signed-off-by: Deepak S deepa...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 15 +++
1 file changed, 15 insertions(+)
diff --git
Hi Dave,
Fixes for regressions and black screens, cc: stable where applicapable
(the last minute rebase was to sprinkle missing stable tags). A bit more
than what I'd wish for, but excluding vlv and that the first 3 patches are
just quirks for 1 regression it looks much better.
There's still a
On Tue, Jul 08, 2014 at 07:50:07AM -0700, Matt Roper wrote:
This should hopefully simplify the display code slightly and also
solves at least one mistake in intel_pipe_set_base() where
to_intel_framebuffer(fb)-obj is referenced during local variable
initialization, before 'if (!fb)' gets
On Mon, Jul 07, 2014 at 10:17:44AM -0600, reza wrote:
Hi,
We're working on Video Wall project on Linux, I need to know if it's
possible to grab Intel gpu output frames or not ?
Not without a video grabber or some other hardware device. Usually
people choose a software approach as below.
I
When changing the pipe we were using, test_grab_crc() wasn't correctly
setting the pipe constraint before waiting for the CRC on the pipe, and
so we ended up waiting for a CRC on a pipe that wasn't lit up.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
tests/kms_plane.c | 12
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_core.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 4dbcb1a..e66d096 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -575,6 +575,10 @@ void
The errno message was a bit in the middle here, it makes more sense to
group the messages about why the test requirement wasn't met together.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_core.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
We were leaking a bit.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 7ac7ebe..364cdd0 100644
--- a/lib/igt_core.c
+++ b/lib/igt_core.c
@@ -591,6 +591,8 @@ void
Just like the it was done for the requirement message, display the errno
message only if errno is set, and display it at the end of the assert
message.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_core.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
On Wed, Jul 09, 2014 at 10:29:09AM +0100, Chris Wilson wrote:
On Tue, Jul 08, 2014 at 07:50:07AM -0700, Matt Roper wrote:
This should hopefully simplify the display code slightly and also
solves at least one mistake in intel_pipe_set_base() where
to_intel_framebuffer(fb)-obj is referenced
The register to read cz count is different from vlv. Also
the counts returned from CCK_CTL1 for BSW are (ticks in 30ns - 1).
czcount_30ns of value 1 is a special case for 320Mhz.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80703
Suggested-by: Deepak S deepa...@linux.intel.com
Cc: Jesse
On Wed, Jul 09, 2014 at 11:45:18AM +0100, Damien Lespiau wrote:
We were leaking a bit.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 7ac7ebe..364cdd0 100644
---
On Wed, Jul 09, 2014 at 11:45:20AM +0100, Damien Lespiau wrote:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_core.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 4dbcb1a..e66d096 100644
---
On Wed, Jul 09, 2014 at 11:45:21AM +0100, Damien Lespiau wrote:
Just like the it was done for the requirement message, display the errno
message only if errno is set, and display it at the end of the assert
message.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Patches 24 are
On Thu, Jul 10, 2014 at 01:16:23PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Since freq/encode conversion formula changes from platform to platform,
create a generic wrapper function and having platform check inside this
help to simpilfy adding newer
On Wed, Jul 09, 2014 at 01:56:02PM +0200, Daniel Vetter wrote:
On Wed, Jul 09, 2014 at 11:45:18AM +0100, Damien Lespiau wrote:
We were leaking a bit.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
lib/igt_core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
CHV hard hangs on reading on 0x11100
References: https://bugs.freedesktop.org/show_bug.cgi?id=80893
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 24
1 file changed, 24 deletions(-)
diff --git
CHV hard hangs on reading on 0x112f4.
References: https://bugs.freedesktop.org/show_bug.cgi?id=80893
Suggested-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 -
1 file changed, 21
CHV hard hangs on reading these registers. As these have not
been used since cantiga ilk, remove the debugfs entry.
References: https://bugs.freedesktop.org/show_bug.cgi?id=80893
Suggested-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
These are accessing registers that the chv doesn't seem to
have. Read access on these regions cause a system hard hang.
If some of these are still on use just nack and I do
gen check patch instead.
Mika Kuoppala (4):
drm/i915: remove i915_delayedfreq_table debugfs entry
drm/i915: remove
On Wed, Jul 09, 2014 at 01:06:08PM +0100, Damien Lespiau wrote:
On Wed, Jul 09, 2014 at 01:56:02PM +0200, Daniel Vetter wrote:
On Wed, Jul 09, 2014 at 11:45:18AM +0100, Damien Lespiau wrote:
We were leaking a bit.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
On Wed, Jul 09, 2014 at 03:10:42PM +0300, Mika Kuoppala wrote:
These are accessing registers that the chv doesn't seem to
have. Read access on these regions cause a system hard hang.
If some of these are still on use just nack and I do
gen check patch instead.
For the first two we could
On 06/19/2014 12:13 PM, Damien Lespiau wrote:
On Wed, Feb 26, 2014 at 04:41:41PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Allow userptr objects to be created and used via libdrm_intel.
At the moment tiling and mapping to GTT aperture is not supported
due
On Wed, Jul 09, 2014 at 02:08:08PM +0100, Tvrtko Ursulin wrote:
On 06/19/2014 12:13 PM, Damien Lespiau wrote:
On Wed, Feb 26, 2014 at 04:41:41PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Allow userptr objects to be created and used via libdrm_intel.
At
Some comments on Daniels' comments inline
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Monday, July 07, 2014 5:10 PM
To: Gore, Tim
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2/2] intel-gpu-tools:
Some inline comments
Tim
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Monday, July 07, 2014 5:12 PM
To: Gore, Tim
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/2] intel-gpu-tools: pass argc/argv
On Mon, Jul 07, 2014 at 09:05:50PM +0200, Daniel Vetter wrote:
On Thu, Jun 26, 2014 at 06:24:01PM +0100, john.c.harri...@intel.com wrote:
From: John Harrison john.c.harri...@intel.com
A major point of the GPU scheduler is that it re-orders batch buffers after
they
have been submitted
On Wed, Jul 09, 2014 at 01:50:30PM +, Gore, Tim wrote:
Some inline comments
Tim
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Monday, July 07, 2014 5:12 PM
To: Gore, Tim
Cc: intel-gfx@lists.freedesktop.org
On Wed, Jul 09, 2014 at 01:23:46PM +, Gore, Tim wrote:
Some comments on Daniels' comments inline
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Not sure whether forcing the reuse of igt_subtest_init makes a lot of sense
since it
On Wed, Jul 09, 2014 at 02:16:59PM +0100, Damien Lespiau wrote:
On Wed, Jul 09, 2014 at 02:08:08PM +0100, Tvrtko Ursulin wrote:
On 06/19/2014 12:13 PM, Damien Lespiau wrote:
On Wed, Feb 26, 2014 at 04:41:41PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
On Wed, Jul 09, 2014 at 04:25:55PM +0200, Daniel Vetter wrote:
On Wed, Jul 09, 2014 at 02:16:59PM +0100, Damien Lespiau wrote:
On Wed, Jul 09, 2014 at 02:08:08PM +0100, Tvrtko Ursulin wrote:
On 06/19/2014 12:13 PM, Damien Lespiau wrote:
On Wed, Feb 26, 2014 at 04:41:41PM +, Tvrtko
On Wed, Jul 09, 2014 at 12:37:08AM -0700, Chris Wilson wrote:
On Tue, Jul 08, 2014 at 03:26:36PM -0700, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
This adds a small module for managing a pool of batch buffers.
The only current use case is for the
On Wed, 9 Jul 2014 15:10:43 +0300
Mika Kuoppala mika.kuopp...@linux.intel.com wrote:
CHV hard hangs on reading these registers. As these have not
been used since cantiga ilk, remove the debugfs entry.
References: https://bugs.freedesktop.org/show_bug.cgi?id=80893
Suggested-by: Jesse
On Wed, 9 Jul 2014 15:10:45 +0300
Mika Kuoppala mika.kuopp...@linux.intel.com wrote:
CHV hard hangs on reading on 0x112f4.
References: https://bugs.freedesktop.org/show_bug.cgi?id=80893
Suggested-by: Daniel Vetter daniel.vet...@ffwll.ch
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
On Wed, 9 Jul 2014 15:10:46 +0300
Mika Kuoppala mika.kuopp...@linux.intel.com wrote:
CHV hard hangs on reading on 0x11100
References: https://bugs.freedesktop.org/show_bug.cgi?id=80893
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 24
On Wed, Jul 09, 2014 at 08:10:47AM -0700, Volkin, Bradley D wrote:
On Wed, Jul 09, 2014 at 12:37:08AM -0700, Chris Wilson wrote:
On Tue, Jul 08, 2014 at 03:26:36PM -0700, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
This adds a small module for
On Wed, Jul 09, 2014 at 08:30:08AM -0700, Chris Wilson wrote:
On Wed, Jul 09, 2014 at 08:10:47AM -0700, Volkin, Bradley D wrote:
On Wed, Jul 09, 2014 at 12:37:08AM -0700, Chris Wilson wrote:
On Tue, Jul 08, 2014 at 03:26:36PM -0700, bradley.d.vol...@intel.com
wrote:
From: Brad Volkin
On Wed, Jul 09, 2014 at 12:36:38AM -0700, Chris Wilson wrote:
On Tue, Jul 08, 2014 at 03:26:38PM -0700, bradley.d.vol...@intel.com wrote:
From: Brad Volkin bradley.d.vol...@intel.com
It provides some useful information about the buffers in
the global command parser batch pool.
v2:
On Wed, Jul 09, 2014 at 08:59:29AM -0700, Volkin, Bradley D wrote:
On Wed, Jul 09, 2014 at 08:30:08AM -0700, Chris Wilson wrote:
You need to check that the shrinker hasn't truncated your backing
storage whilst it was marked DONTNEED. It just amounts to checking for
obj-madv ==
On Fri, Jul 04, 2014 at 11:59:57AM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
That function can be used to write anything on D_COMP, not just
disable it, so print a more appropriate message.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
Reviewed-by:
On Fri, Jul 04, 2014 at 11:59:58AM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
On HSW, the D_COMP register can be accessed through the mailbox (read
and write) or through MMIO on a MCHBAR offset (read only). On BDW, the
access should be done through MMIO on another
On Wed, Jul 09, 2014 at 04:23:50PM +0200, Daniel Vetter wrote:
For me the only trouble with this disdinction is that people consistently
place tests in the wrong Makefile target. Hence I'd like to see those two
Makefile targets being unified (which requires adjustements in piglit,
too) to
From: Paulo Zanoni paulo.r.zan...@intel.com
Otherwise we will print some WARNs when we read registers and the
machine is suspended.
Testcase: igt/pm_rpm/debugfs-read
Cc: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c |
From: Brad Volkin bradley.d.vol...@intel.com
This adds a small module for managing a pool of batch buffers.
The only current use case is for the command parser, as described
in the kerneldoc in the patch. The code is simple, but separating
it out makes it easier to change the underlying
From: Brad Volkin bradley.d.vol...@intel.com
To better account for the potentially large memory consumption
of the batch pool.
Signed-off-by: Brad Volkin bradley.d.vol...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 45 +
1 file changed, 36
... since it uses flink. Fixes a regression due to:
commit 6d6dfcfb883818b40b58bac61cc72cab428a7a03
Author: David Herrmann dh.herrm...@gmail.com
AuthorDate: Sun Mar 16 14:38:40 2014 +0100
drm: enable render-nodes by default
Cc: David Herrmann dh.herrm...@gmail.com
Signed-off-by: Daniel
This reverts commit 773875bfb6737982903c42d1ee88cf60af80089c.
It is very much needed and the lack of dithering has been reported by
a large list of people with various gen2/3 hardware.
Also, the original patch was complete non-sense since the WARNING
backtraces in the references bugzilla are
On Wed, Jul 09, 2014 at 02:31:57PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Otherwise we will print some WARNs when we read registers and the
machine is suspended.
Do all register reads really require this? If so, shouldn't it work
similarly to forcewake? I
On Mon, 7 Jul 2014 14:59:45 +0530
Vandana Kannan vandana.kan...@intel.com wrote:
For Gen 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the state. The register is set only if DRRS is
Daniel, looks like this series has some r-bs; iirc this fixed some Asus
HDMI monitors too (and who knows how many TVs).
Jesse
On Thu, 22 May 2014 16:50:48 +0530
Vandana Kannan vandana.kan...@intel.com wrote:
Added a property to enable user space to set aspect ratio.
This patch contains
On Wed 2014-07-09 22:35:53, Daniel Vetter wrote:
This reverts commit 773875bfb6737982903c42d1ee88cf60af80089c.
It is very much needed and the lack of dithering has been reported by
a large list of people with various gen2/3 hardware.
Also, the original patch was complete non-sense since
intel_primary_plane_{setplane,disable} were lacking struct_mutex locking
around their GEM operations.
Signed-off-by: Matt Roper matthew.d.ro...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
Add !mutex_is_locked() checks to intel_pin_and_fence_fb_obj() and
intel_unpin_fb_obj() to help catch failures to grab struct_mutex when
operating on fb objects.
Signed-off-by: Matt Roper matthew.d.ro...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 4
1 file changed, 4 insertions(+)
BDW supports GT C0 residency reporting in constant time unit. Driver calculates
GT utilization based on C0 residency and adjusts RP frequency up/down
accordingly.
Signed-off-by: Daisy Sun daisy@intel.com
[torourke: rebased on latest and resolved conflict]
Signed-off-by: Tom O'Rourke
On Wednesday 09 July 2014 05:33 PM, Daniel Vetter wrote:
On Thu, Jul 10, 2014 at 01:16:23PM +0530, deepa...@linux.intel.com wrote:
From: Deepak S deepa...@linux.intel.com
Since freq/encode conversion formula changes from platform to platform,
create a generic wrapper function and having
On Jul-10-2014 2:42 AM, Jesse Barnes wrote:
On Mon, 7 Jul 2014 14:59:45 +0530
Vandana Kannan vandana.kan...@intel.com wrote:
For Gen 8, set M2_N2 registers on every mode set. This is required to make
sure M2_N2 registers are set during boot, resume from sleep for cross-
checking the
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