Very appreciate. :) Thanks Thomas!
-Original Message-
From: Daniel, Thomas
Sent: Tuesday, February 10, 2015 10:56 PM
To: Wang, Zhi A; Intel-gfx@lists.freedesktop.org
Subject: RE: About CTX_CONTEXT_CONTROL initialization in populate_lr_context()
intel_lrc.c
-Original Message-
-Original Message-
From: Wang, Zhi A
Sent: Tuesday, February 10, 2015 2:44 PM
To: Daniel, Thomas; Intel-gfx@lists.freedesktop.org
Subject: RE: About CTX_CONTEXT_CONTROL initialization in
populate_lr_context() intel_lrc.c
Hi Thomas:
Thanks for the information! Learned a lot.
Hi Thomas:
Thanks for the information! Learned a lot. :)
I remember that semaphore is disabled on Gen8 for a long time ago. Recently I
found it has been enabled. just thought that if a workload which isn't being
protected by MI_ARB_ON_OFF may be switched out by failing to wait semaphore
Hello,
xserver-xorg-video-intel from git does not compile on ubuntu precise box
anymore... Here is error log:
https://launchpadlibrarian.net/197217861/buildlog_ubuntu-precise-amd64.xserver-xorg-video-intel_2:2.99.917-git201502091709.928ff25~ubuntu12.04.1_FAILEDTOBUILD.txt.gz
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5750
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV +5-4 275/283
On Mon, Feb 09, 2015 at 07:03:26PM +0100, Daniel Vetter wrote:
Just a little demo really. We probably need to introduce skl specific
functions for a lot of the format validation stuff, or at least
helpers. Specifically I think intel_framebuffer_init and
intel_fb_align_height must be adjusted
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Let the DRM core know we can handle it.
v2: Change to boolean true. (Daniel Vetter)
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file
From: Daniel Vetter daniel.vet...@ffwll.ch
With this we can treat the fb format modifier completely independently
from the fencing mode in obj-tiling_mode in the initial plane code.
Which means new tiling modes without any gtt fence are now fully
support in the core i915 driver code.
v2: Also
On 09/02/15 15:05, Wang, Zhi A wrote:
Hi Gurus:
Forgive my junior HW knowledge, I just found that in execlist
context initialization function populate_lr_context(), this line:
reg_state[CTX_CONTEXT_CONTROL+1] =
_MASKED_BIT_ENABLE((13) |
Boring ioctl validation. Luckily no gaps found while doing it.
v2: git add ftw!
v3: Fixes:
- args-size is an outparam for get, adjust test.
- Pick an invalid param, not an invalid ioctl number ... tsk.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
tests/.gitignore| 1
Align with common igt library style:
- Push the igt_require into the function.
- Push the intel_gen into the function.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
lib/igt_gt.c | 12
lib/igt_gt.h | 2 +-
tests/gem_concurrent_blit.c | 2
Just push the igt_require down to align with the usual style.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
lib/igt_gt.c | 2 +-
lib/ioctl_wrappers.c | 4 ++--
lib/ioctl_wrappers.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/lib/igt_gt.c
We also need a raw version for some tests.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
lib/ioctl_wrappers.c | 32
lib/ioctl_wrappers.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index
Just spotted while driving around. gtkdoc needs the full parameter
list otherwise it doesn't recognize it as a function. So add them.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
lib/ioctl_wrappers.h | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git
We stick to the overall prefix even for magic require functions.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
lib/ioctl_wrappers.h| 11 ++-
tests/gem_concurrent_blit.c | 4 ++--
tests/gem_fence_upload.c| 2 +-
tests/gem_mmap_wc.c | 16
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
tests/gem_ctx_bad_destroy.c | 25 +
tests/gem_ctx_create.c | 11 ++-
tests/gem_ctx_exec.c| 23 ---
3 files changed, 11 insertions(+), 48 deletions(-)
diff --git
We have separate require checks already, so these failing is a bug in
the test logic.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
lib/igt_gt.c | 2 +-
lib/ioctl_wrappers.c | 18 +-
lib/ioctl_wrappers.h | 4 ++--
3 files changed, 8 insertions(+), 16
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5743
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV +4 275/283
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Just a few basic tests to make sure fb modifiers can be used and
behave sanely when mixed with the old set_tiling API.
v2:
* Review feedback from Daniel Vetter:
1. Move cap detection into the subtest so skipping works.
2. Added some
From: Daniel Vetter daniel.vet...@ffwll.ch
Just the usual paranoia ...
v2: Fixed format strings. (Tvrtko Ursulin)
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
Reviewed-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/drm_crtc.c | 17 +
1 file changed, 17
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Also drop the mutex since with universal planes object tiling mode is
locked down while assigned to a framebuffer.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 5 ++---
1 file changed, 2
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Aggregated patch series containing Daniel's take on fb modifiers plus
some missing bits, fixes and cleanups.
Also including Rob Clark's RFC so PRTS can attempt to test this.
Needs updated kms_addfb i-g-t which will follow.
Daniel Vetter (5):
From: Daniel Vetter daniel.vet...@ffwll.ch
Just a little demo really. We probably need to introduce skl specific
functions for a lot of the format validation stuff, or at least
helpers. Specifically I think intel_framebuffer_init and
intel_fb_align_height must be adjusted to have an i915_ and a
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Therefore remove dead code.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 72 ++--
1 file changed, 4 insertions(+), 68 deletions(-)
diff --git
From: Rob Clark robdcl...@gmail.com
In DRM/KMS we are lacking a good way to deal with tiled/compressed
formats. Especially in the case of dmabuf/prime buffer sharing, where
we cannot always rely on under-the-hood flags passed to driver specific
gem-create ioctl to pass around these extra flags.
From: Daniel Vetter daniel.vet...@ffwll.ch
Currently we don't support anything but X tiled. And for an easier
transition it makes a lot of sense to just keep requiring that X tiled
is properly fenced.
Which means we need to do absolutely nothing in old code to support fb
modifiers, yay!
v2: Fix
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/intel_sprite.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
To be used from the new addfb2 extension.
v2:
- Drop Intel-specific untiled modfier.
- Move to drm_fourcc.h.
- Document layouts a bit and denote them as platform-specific and not
useable for cross-driver sharing.
- Add Y-tiling for completeness.
-
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index
From: Daniel Vetter daniel.vet...@ffwll.ch
No functional changes yet since intel_framebuffer_init would have
fixed this up for us. But this is prep work to be able to handle new
tiling layouts in the initial plane config code.
Follow-up patches will start to make use of this and switch over to
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
And at the same time replace BUG() with a warning and handle it gracefuly.
Signed-off-by: Tvrtko Ursulin tvrtko.ursu...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git
Also move forcewake and stop_rings code from igt_debugfs to igt_gt
since it fits better. And move the hang injection fork helpers from
igt_aux to igt_gt, too.
Also push the intel_gen call into igt_hang_ring while at it.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
It collides with the subtest naming convention glossary entry for swap.
Which makes the docbook xml stuff unhappy.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
lib/igt.cocci | 4 ++--
lib/igt_aux.h | 2 +-
tests/eviction_common.c | 2 +-
tests/gem_ctx_thrash.c | 4
This way the igt_require for the ctx support is hit before we've
launched a bazillion threads and need to wait until they're all done.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
tests/gem_ppgtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/gem_ppgtt.c
I've forgotten to do this in
commit e4753d2d96fbb88077e70820793137f45f02c9ba
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Mon Sep 29 14:42:33 2014 +0200
tests/gem_wait_render_timeout: Convert to subtests
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
tests/Makefile.am | 2
We've missed them, and the kernel isn't nasty enough and forgot to
check them. To add these tests convert the existing create/destroy
tests over to subtests.
v2: Do the basic create/destroy in ctx_bad_destroy in a fixture
so that all the tests skip properly.
Signed-off-by: Daniel Vetter
A bit more invasive since getting rid off all the places meant
to flatten some of the control flow with implicit igt_require.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
tests/gem_reset_stats.c | 117 +++-
1 file changed, 27 insertions(+),
And move them so that they're grouped with the other context wrappers.
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
lib/ioctl_wrappers.c | 79 +++-
lib/ioctl_wrappers.h | 22 +++
2 files changed, 63 insertions(+), 38
Duplication just means it gets out of sync.
Also update they keyword list in the Makefile, not everything was listed.
And add a new invalid keyword.
While at it update NEWS.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
CONTRIBUTING | 2 +-
NEWS
Yeah, historically grown but we should try to be somewhat consistent.
It helps with filtering testcases.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
tests/gem_concurrent_blit.c | 4 ++--
tests/gem_ppgtt.c | 4 ++--
tests/kms_flip.c| 16
3
On Mon, Feb 09, 2015 at 01:54:16PM -0800, Ben Widawsky wrote:
If we're moving a bunch of buffers from the CPU domain to the GPU domain, and
we've already blown out the entire cache via a wbinvd, there is nothing more
to
do.
With this and the previous patches, I am seeing a 3x FPS increase
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5733
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Mon, Feb 09, 2015 at 01:54:14PM -0800, Ben Widawsky wrote:
flush_chipset makes no sense with execlists because the former is for strictly
prior to gen6, while the latter is for gen = 8
The whole split is insane. I'd rather keep the code as is and merge it
back together which was the idea
On Mon, Feb 09, 2015 at 01:54:15PM -0800, Ben Widawsky wrote:
The role of eb_vmas continues to grow here as it becomes the proper
encapsulation for the data passed to the various execution function.
Next patch makes use of it... This patch was initially part of the next patch,
but got split
On Mon, Feb 09, 2015 at 01:54:19PM -0800, Ben Widawsky wrote:
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/i915_gem.c | 32
drivers/gpu/drm/i915/i915_gem_gtt.c | 13 ++---
3
On Mon, Feb 09, 2015 at 09:14:26PM +, Chris Wilson wrote:
On Mon, Feb 09, 2015 at 07:25:56PM +, Damien Lespiau wrote:
v2: Reorder defines (Ben)
Bikeshed time?
Oh no, why did I give in the first time? now I'm being bullied!
/* WaCatErrorRejectionIssue */
#define
v2: Reorder defines (Ben)
v3: More bikesheds, this time re-ordering comments! (Chris)
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
On Mon, Feb 09, 2015 at 07:33:05PM +, Damien Lespiau wrote:
When enabling new platforms, we may not have any W/A to apply,
especially that, now, a bunch of them have to be done from the ring.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Queued for -next, thanks for the patch.
No functional changes yet since intel_framebuffer_init would have
fixed this up for us. But this is prep work to be able to handle new
tiling layouts in the initial plane config code.
Follow-up patches will start to make use of this and switch over to fb
modifiers where needed.
Signed-off-by:
With this we can treat the fb format modifier completely independently
from the fencing mode in obj-tiling_mode in the initial plane code.
Which means new tiling modes without any gtt fence are now fully
support in the core i915 driver code.
v2: Also add pixel_format while at it, we need this to
On Mon, Feb 09, 2015 at 07:03:28PM +0100, Daniel Vetter wrote:
Just the usual paranoia ...
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/drm_crtc.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/drm_crtc.c
With Intel GVT-g, GPU power management is controlled by
host driver, so there is no need to provide virtualized
GPU PM support. In the future it might be useful to gather
VM input for freq boost, but now let's disable it simply.
v2:
take Chris' comments:
- do not special case this to
With Intel GVT-g, the global graphic memory space is partitioned by
multiple vGPU instances in different VMs. The ballooning code is called
in i915_gem_setup_global_gtt(), utilizing the drm mm allocator APIs to
mark the graphic address space which are partitioned out to other vGPUs
as reserved.
With Intel GVT-g, the fence registers are partitioned by multiple
vGPU instances in different VMs. Routine i915_gem_load() is modified
to reset the num_fence_regs, when the driver detects it's running in
a VM. Accesses to the fence registers from vGPU will be trapped and
remapped by the host side.
Display switch logic is added to notify the host side that
current vGPU have a valid surface to show. It does so by
writing the display_ready field in PV INFO page, and then
will be handled in the host side. This is useful to avoid
trickiness when the VM's framebuffer is being accessed in
the
In the virtualized environment, forcewake operations are not
necessary for the driver, because mmio accesses will be trapped
and emulated by the host side, and real forcewake operations are
also done in the host. New mmio access handlers are added to directly
call the __raw_i915_read/write,
Framebuffer compression is disabled when driver detects it's
running in a Intel GVT-g enlightened VM, because FBC is not
emulated and there is no stolen memory for a vGPU.
v2:
take Chris' comments:
- move the code into intel_update_fbc()
v4:
take Tvrtko's comments:
- rebase the
On Tue, Feb 10, 2015 at 12:36:51PM +0100, Daniel Vetter wrote:
On Tue, Feb 10, 2015 at 11:01:56AM +, Chris Wilson wrote:
On Mon, Feb 09, 2015 at 07:03:28PM +0100, Daniel Vetter wrote:
Just the usual paranoia ...
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
On 02/10/2015 11:05 AM, Yu Zhang wrote:
This patch set includes necessary code changes when i915 driver
runs inside a VM. Though ideally we can run an unmodified i915
driver in VM, adding such enlightenments can greatly reduce the
virtualization complexity in orders of magnitude. Code changes
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
To be used from the new addfb2 extension.
v2:
- Drop Intel-specific untiled modfier.
- Move to drm_fourcc.h.
- Document layouts a bit and denote them as platform-specific and not
useable for cross-driver sharing.
- Add Y-tiling for completeness.
-
On Tue, Feb 10, 2015 at 11:01:56AM +, Chris Wilson wrote:
On Mon, Feb 09, 2015 at 07:03:28PM +0100, Daniel Vetter wrote:
Just the usual paranoia ...
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
drivers/gpu/drm/drm_crtc.c | 17 +
1 file changed, 17
This patch set includes necessary code changes when i915 driver
runs inside a VM. Though ideally we can run an unmodified i915
driver in VM, adding such enlightenments can greatly reduce the
virtualization complexity in orders of magnitude. Code changes
for the host side, which includes the actual
Introduce a PV INFO structure, to facilitate the Intel GVT-g
technology, which is a GPU virtualization solution with mediated
pass-through. This page contains the shared information between
i915 driver and the host emulator. For now, this structure utilizes
an area of 4K bytes on HSW GPU's unused
The current Intel GVT-g only supports alias ppgtt. And the
emulation is done in the host by first trapping PP_DIR_BASE
mmio accesses. Updating PP_DIR_BASE by using instructions such
as MI_LOAD_REGISTER_IMM are hard to detect and are not supported
in current code. Therefore this patch also adds a
From: Ville Syrjälä ville.syrj...@linux.intel.com
Return IRQ_HANDLED from intel_dp_hpd_pulse() to properly
ignore the long HPD pulse on eDP to avoid the never ending
VDD off-HPD-VDD on-VDD off-HPD... cycle.
This fixes a regression intoduced by
commit b2c5c181ed18490648a02f8c7d562a3b9e8b96de
On 02/09/2015 06:03 PM, Daniel Vetter wrote:
From: Tvrtko Ursulin tvrtko.ursu...@intel.com
To be used from the new addfb2 extension.
v2:
- Drop Intel-specific untiled modfier.
- Move to drm_fourcc.h.
- Document layouts a bit and denote them as platform-specific and not
useable for
On 02/09/2015 06:03 PM, Daniel Vetter wrote:
Currently we don't support anything but X tiled. And for an easier
transition it makes a lot of sense to just keep requiring that X tiled
is properly fenced.
Which means we need to do absolutely nothing in old code to support fb
modifiers, yay!
Cc:
skylake_update_primary_plane() did not handle all pixel formats returned
by skl_format_to_fourcc(). Handle alpha similar to skl_update_plane().
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89052
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
This is purely cargo culting to avoid
Currently we don't support anything but X tiled. And for an easier
transition it makes a lot of sense to just keep requiring that X tiled
is properly fenced.
Which means we need to do absolutely nothing in old code to support fb
modifiers, yay!
v2: Fix the Y tiling check, noticed by Tvrtko.
Cc:
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5734
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Mon, 09 Feb 2015, Daniel Vetter daniel.vet...@ffwll.ch wrote:
From: Chris Wilson ch...@chris-wilson.co.uk
This (partially) reverts
commit 5537252b6b6d71fb1a8ed7395a8e5babf91953fd
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Tue Mar 25 13:23:06 2014 +
drm/i915:
On Tue, Feb 10, 2015 at 01:15:49PM +0200, Jani Nikula wrote:
skylake_update_primary_plane() did not handle all pixel formats returned
by skl_format_to_fourcc(). Handle alpha similar to skl_update_plane().
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89052
Signed-off-by: Jani Nikula
Currently we don't support anything but X tiled. And for an easier
transition it makes a lot of sense to just keep requiring that X tiled
is properly fenced.
Which means we need to do absolutely nothing in old code to support fb
modifiers, yay!
v2: Fix the Y tiling check, noticed by Tvrtko.
v3:
On Tue, Feb 10, 2015 at 10:31:00AM +, Damien Lespiau wrote:
v2: Reorder defines (Ben)
v3: More bikesheds, this time re-ordering comments! (Chris)
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com
Signed-off-by: Damien Lespiau
From: Ville Syrjälä ville.syrj...@linux.intel.com
Apparently we must yet halve the DDL drain latency from what we're
using currently. This little nugget is not in any spec, but came
down through the grapevine.
This makes the displays a bit more stable. Not quite fully stable but at
least they
From: Ville Syrjälä ville.syrj...@linux.intel.com
The main motivation behind this series is to get the display to be stable
on CHV. Some new memory power savings features got enabled on later
steppings/BIOS versions which caused all kinds of display troubles
with our current code.
There are
From: Ville Syrjälä ville.syrj...@linux.intel.com
Move the DDL precision handling into vlv_compute_drain_latency() so the
callers don't have to duplicate the same code to deal with it.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++---
From: Ville Syrjälä ville.syrj...@linux.intel.com
The current drain lantency computation relies on hardcoded limits to
determine when the to use the low vs. high precision multiplier.
Rewrite the code to use a more straightforward approach.
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä ville.syrj...@linux.intel.com
VLV/CHV have similar DSPARB registers as older platforms, just more of
them due to more planes. Add a bit of code to read out the current FIFO
split from the registers. Will be useful later when we improve the WM
calculations.
Signed-off-by:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Poke at the CBR1_VLV register during init_clock_gating to make sure the
PND deadline scheme is used.
The hardware has two modes of operation wrt. watermarks:
1) PND deadline mode:
- memory request deadline is calculated from actual FIFO level *
From: Ville Syrjälä ville.syrj...@linux.intel.com
Now that we have drm_planes for the cursor and primary we can move the
pixel_size handling into vlv_compute_drain_latency() and just pass the
appropriate plane to it.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV has a new knob in Punit to select between some memory power savings
modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
enabled, so let's do so in the hopes for moar power savings.
Signed-off-by: Ville Syrjälä
From: Ville Syrjälä ville.syrj...@linux.intel.com
Assuming the PND deadline mechanism works reasonably we should do
memory requests as early as possible so that PND has schedule the
requests more intelligently. Currently we're still calculating
the watermarks as if VLV/CHV are identical to g4x,
From: Ville Syrjälä ville.syrj...@linux.intel.com
CHV supposedly does maxfifo mode even with two enabled
(primary/sprite) planes. Lets try to support that by halving the FIFO
size for the calculations and picking the smallest calculcated
watermark from the enabled planes.
Signed-off-by: Ville
From: Ville Syrjälä ville.syrj...@linux.intel.com
Introduce struct vlv_wm_values to house VLV watermark/drain latency
values. We start by using it when computing the drain latency values.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 9
From: Vidya Srinivas vidya.srini...@intel.com
PFI credit programming is required when CD clock (related to data flow from
display pipeline to end display) is greater than CZ clock (related to data
flow from memory to display plane). This programming should be done when all
planes are OFF to avoid
From: Ville Syrjälä ville.syrj...@linux.intel.com
Kill the silly DRAIN_LATENCY_PRECISION_* defines and just use the raw
number instead.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_pm.c | 12
2
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5737
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Fri, Nov 14, 2014 at 08:52:30AM -0800, Rodrigo Vivi wrote:
+struct psr_table {
+ /* Feature bits */
+ u8 full_link:1;
+ u8 require_aux_to_wakeup:1;
+ u8 feature_bits_rsvd:6;
+
+ /* Wait times */
+ u8 idle_frames:4;
+ u8 lines_to_wait:3;
+ u8
This function is only used in intel_lrc.c, so restrict it to that file. The
function was moved around to avoid a forward declaration and group it with its
user.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 9 +
The last (only?) user of this was removed in:
commit 2208d655a91f9879bd9a39ff9df05dd668b3512c
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Fri Nov 14 09:25:29 2014 +0100
drm/i915: drop WaSetupGtModeTdRowDispatch:snb
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
This header has been unusued since:
commit 063c86f60ad4064b2cf62041bee8c6389e180b76
Author: Jani Nikula jani.nik...@intel.com
Date: Fri Jan 16 14:27:27 2015 +0200
drm/i915/dsi: remove intel_dsi_cmd.c and the unused functions therein
Signed-off-by: Damien Lespiau
This function is only used in intel_lrc.c, so restrict it to that file.
One user of intel_logical_ring_begin() that was defined before the
function was moved after it (it's less code movement than moving
intel_logical_ring_begin() and its dependencies.
intel_logical_ring_begin() was also removed
This function is only used in intel_ringbuffer.c, so restrict it to that
file. The function was moved around to avoid a forward declaration and
group it with its user.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 124
This function is only used in intel_lrc.c, so restrict it to that file. The
function was moved around to avoid a forward declaration and group it with its
user.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c | 66
This function is only used in intel_dp.c since:
commit 0e32b39ceed665bfa4a77a4bc307b6652b991632
Author: Dave Airlie airl...@redhat.com
Date: Fri May 2 14:02:48 2014 +1000
drm/i915: add DP 1.2 MST support (v0.7)
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
These error states are great to know gpu state when it hangs.
But since we don't have automated tools to do analysis we are
facing much noise on bugzilla with end users reporting just
because log asked to, while gpu reset worked and users probably
never notice any screen issue. Most of these
There have been quite a bit of development lately, leaving behing lonely
protypes. Time to bid them farewell.
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/intel_drv.h | 9 -
2 files changed, 13 deletions(-)
This function is not used outside of intel_display.c since;
commit cf4c7c12258ed9367f4fc45238f5f50d2db892c1
Author: Matt Roper matthew.d.ro...@intel.com
Date: Thu Dec 4 10:27:42 2014 -0800
drm/i915: Make all plane disables use 'update_plane' (v5)
Signed-off-by: Damien Lespiau
Ran my cleanup script again and caught a few tiny oversights.
--
Damien
Damien Lespiau (10):
drm/i915: Garbage collect orphaned prototypes
drm/i915: Make intel_ring_setup_status_page() static
drm/i915: Remove intel_dsi_cmd.h
drm/i915: Make intel_lr_context_render_state_init() static
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