== Series Details ==
Series: drm/i915/pps: Add PPS power domain
URL : https://patchwork.freedesktop.org/series/85470/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9544 -> Patchwork_19256
Summary
---
**FAILURE**
On Tue, Dec 29, 2020 at 04:41:31PM +0200, Imre Deak wrote:
> Hi,
>
> On Mon, Dec 21, 2020 at 04:07:58AM +, Matthew Wilcox wrote:
> >
> > At boot,
> >
> > [2.787995] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon
> > [2.788001] i915 :00:02.0: [drm] *ERROR* LSPCON init
It abstracts getting the AUX power domain in pps_lock under
PPS power domain. This makes sure that the platforms which really
requires AUX power in order to access PPS registers will get the
reference to necessary power wells.
PPS power domain requires only to track the AUX_A associated
power
> -Original Message-
> From: S, Saichandana
> Sent: Monday, January 4, 2021 4:01 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: S, Saichandana ; Nikula, Jani
> ; Gupta, Anshuman
> Subject: [PATCH v2] drm/i915/debugfs : PM_REQ and PM_RES registers
>
> From: Saichandana
>
> PM_REQ
Hi Chris,
> Before we mark the virtual engine as no longer inflight, flush any
> ongoing signaling that may be using the ce->signal_link along the
> previous breadcrumbs. On switch to a new physical engine, that link will
> be inserted into the new set of breadcrumbs, causing confusion to an
>
Hi Chris,
On Mon, Jan 04, 2021 at 11:51:43AM +, Chris Wilson wrote:
> If another sibling is able to claim the virtual request, by the time we
> inspect the request under the lock if may no longer match the local
> engine.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2877
>
Hi Chris,
On Mon, Jan 04, 2021 at 11:51:42AM +, Chris Wilson wrote:
> If the engine reset fails, we will attempt to resume with the current
> inflight submissions. When that happens, we cannot assert that the
> engine reset cleared the pending submission, so do not.
>
> Closes:
== Series Details ==
Series: series starting with [1/8] drm/i915/gt: Rearrange vlv workarounds
URL : https://patchwork.freedesktop.org/series/85467/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9544 -> Patchwork_19255
Hi Chris,
On Mon, Jan 04, 2021 at 11:51:41AM +, Chris Wilson wrote:
> Fixes: f170523a7b8e ("drm/i915/gt: Consolidate the CS timestamp clocks")
> Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
Thanks,
Andi
___
Intel-gfx mailing list
Hi Chris,
On Mon, Jan 04, 2021 at 11:51:40AM +, Chris Wilson wrote:
> A few missed PTR_ERR() upon create_gang() errors.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Andi Shyti
Thanks,
Andi
___
Intel-gfx mailing list
== Series Details ==
Series: series starting with [1/8] drm/i915/gt: Rearrange vlv workarounds
URL : https://patchwork.freedesktop.org/series/85467/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: series starting with [CI,1/4] drm: Add function to convert rect in
16.16 fixed format to regular format
URL : https://patchwork.freedesktop.org/series/85458/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9544_full -> Patchwork_19254_full
Push the sleeping stop_ring() out of the reset resume function to reset
prepare; we are not allowed to sleep in the former.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 97 +++
1 file changed, 36 insertions(+), 61 deletions(-)
diff --git
The GFX_MODE is reset along with the engine, turning off ppGTT. We need
to re-enable it upon resume.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen6_ppgtt.c| 9 -
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 13 ++---
2 files changed, 10
Take advantage of calling xcs_resume under a forcewake by using direct
mmio access. In particular, we can avoid the sleeping variants to allow
resume to be called from softirq context, required for engine resets.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 98
The benefit of only resetting a single engine is that we leave other
streams of userspace work intact across a hang; vital for process
isolation. We had wired up individual engine resets for gen6, but only
enabled it from gen8; now let's turn it on for the forgotten gen7. gen6
is still a mystery
The engine resets selftests kick the tasklets, safe up until now as only
execlists supported engine resets.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 18 ++
drivers/gpu/drm/i915/gt/selftest_reset.c | 11 ---
2 files changed, 22
In the legacy ringbuffer submission, we still had an open-coded version
of intel_engine_stop_cs() with one addition verification step. Transfer
that verification to intel_engine_stop_cs() itself, and call it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 15
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 118
1 file changed, 47 insertions(+), 71 deletions(-)
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 +++--
1 file changed, 51 insertions(+), 44 deletions(-)
== Series Details ==
Series: drm/i915: Disable RPM wakeref assertions during driver shutdown
URL : https://patchwork.freedesktop.org/series/85456/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9544_full -> Patchwork_19253_full
== Series Details ==
Series: series starting with [CI,1/4] drm: Add function to convert rect in
16.16 fixed format to regular format
URL : https://patchwork.freedesktop.org/series/85458/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9544 -> Patchwork_19254
== Series Details ==
Series: series starting with [CI,1/4] drm: Add function to convert rect in
16.16 fixed format to regular format
URL : https://patchwork.freedesktop.org/series/85458/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used,
== Series Details ==
Series: drm/i915: Disable RPM wakeref assertions during driver shutdown
URL : https://patchwork.freedesktop.org/series/85456/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9544 -> Patchwork_19253
On Mon, 2021-01-04 at 15:07 +0200, Gwan-gyeong Mun wrote:
> It is a preliminary work for supporting multiple EDP PSR and
> DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> supportable PSR.
> And this moves and renames the i915_psr structure of drm_i915_private's to
> intel_dp's
== Series Details ==
Series: drm/i915: Use kzalloc for allocating only one thing
URL : https://patchwork.freedesktop.org/series/85447/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9542_full -> Patchwork_19250_full
Summary
Hi Dave and Daniel,
Happy New Year.
Here goes the first pull request targeting 5.12.
drm-intel-next-2021-01-04:
- Display hotplug fix for gen2/gen3 (Chris)
- Remove trailing semicolon (Tom)
- Suppress display warnings for old ifwi presend on our CI (Chris)
- OA/Perf related workaround (Lionel)
It programs Plane's calculated x, y, offset to Plane SF register.
It does the calculation of x and y offsets using
skl_calc_main_surface_offset().
v3: Update commit message
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by:
Now using plane damage clips property to calcualte the damaged area.
Selective fetch only supports one region to be fetched so software
needs to calculate a bounding box around all damage clips.
Now that we are not complete fetching each plane, there is another
loop needed as all the plane areas
The calculation the offsets of the main surface will be needed by PSR2
selective fetch code so here splitting and exporting it.
No functional changes were done here.
v3: Rebased
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by: Gwan-gyeong Mun
Tested-by:
Much more clear to read one function call than four lines doing this
conversion.
v7:
- function renamed
- calculating width and height before truncate
- inlined
v10:
- renamed parameters from source and destination to src and dst
to match sister functions
Cc: Ville Syrjälä
Cc:
As with the regular suspend paths, also disable the wakeref assertions
as we disable the driver during shutdown.
Reported-by: Hans de Goede
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2899
Fixes: fe0f1e3bfdfe ("drm/i915: Shut down displays gracefully on reboot")
Signed-off-by:
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.11-rc2 next-20210104]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use
Quoting Souza, Jose (2021-01-04 19:59:42)
> On Mon, 2021-01-04 at 17:13 +, Chris Wilson wrote:
> > In the near future, upstream will introduce a SZ_8G macro that is
> > slightly different to our own. Employ a temporary ifndef to avoid
> > compilation failure until we have backmerged.
>
>
== Series Details ==
Series: series starting with [1/2] drm/i915/gem: Almagamate clflushes on suspend
URL : https://patchwork.freedesktop.org/series/85445/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9542_full -> Patchwork_19249_full
On Mon, 2021-01-04 at 17:13 +, Chris Wilson wrote:
> In the near future, upstream will introduce a SZ_8G macro that is
> slightly different to our own. Employ a temporary ifndef to avoid
> compilation failure until we have backmerged.
Already here!
Reviewed-by: José Roberto de Souza
Will
Hi Chris,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.11-rc2 next-20210104]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use
== Series Details ==
Series: series starting with [v10,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/85444/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9542_full -> Patchwork_19248_full
== Series Details ==
Series: drm/i915/selftests: Guard against redifinition of SZ_8G (rev2)
URL : https://patchwork.freedesktop.org/series/85451/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9542 -> Patchwork_19252
== Series Details ==
Series: drm/i915/selftests: Guard against redifinition of SZ_8G (rev2)
URL : https://patchwork.freedesktop.org/series/85451/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a1bfe2c002d1 drm/i915/selftests: Guard against redifinition of SZ_8G
-:10:
== Series Details ==
Series: drm/i915: Use kzalloc for allocating only one thing
URL : https://patchwork.freedesktop.org/series/85447/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9542 -> Patchwork_19250
Summary
---
== Series Details ==
Series: i915: fix shift warning (rev2)
URL : https://patchwork.freedesktop.org/series/85448/
State : failure
== Summary ==
Applying: i915: fix shift warning
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
Falling back
In the near future, upstream will introduce a SZ_8G macro that is
slightly different to our own. Employ a temporary ifndef to avoid
compilation failure until we have backmerged.
References: 8b0fac44bd1f ("sizes.h: add SZ_8G/SZ_16G/SZ_32G macros")
Signed-off-by: Chris Wilson
---
In the near future, upstream will introduce a SZ_8G macro that is
slightly different to our own. Employ a temporary ifndef to avoid
compilation failure until we have backmerged.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_memory_region.c | 2 ++
1 file changed, 2
== Series Details ==
Series: series starting with [1/2] drm/i915/gem: Almagamate clflushes on suspend
URL : https://patchwork.freedesktop.org/series/85445/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9542 -> Patchwork_19249
== Series Details ==
Series: drm/i915/gt: Replace open-coded intel_engine_stop_cs() (rev2)
URL : https://patchwork.freedesktop.org/series/84726/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9542_full -> Patchwork_19247_full
== Series Details ==
Series: series starting with [v10,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/85444/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9542 -> Patchwork_19248
== Series Details ==
Series: series starting with [v10,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/85444/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: series starting with [v10,1/2] drm/i915/display: Support PSR Multiple
Instances
URL : https://patchwork.freedesktop.org/series/85444/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5338f9b30dac drm/i915/display: Support PSR Multiple Instances
From: Arnd Bergmann
Randconfig builds on 32-bit machines show lots of warnings for
the i915 driver for passing a 32-bit value into __const_hweight64():
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2584:9: error: shift count >=
width of type [-Werror,-Wshift-count-overflow]
return
Use kzalloc rather than kcalloc(1,...)
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
//
@@
@@
- kcalloc(1,
+ kzalloc(
...)
//
Signed-off-by: Zheng Yongjun
---
drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 +-
1 file changed, 1
From: Arnd Bergmann
Randconfig builds on 32-bit machines show lots of warnings for
the i915 driver for incorrect bit masks like:
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:2584:9: error: shift count >=
width of type [-Werror,-Wshift-count-overflow]
return
On Wed, Dec 30, 2020 at 4:56 PM Chris Wilson wrote:
>
> Quoting Arnd Bergmann (2020-12-30 15:39:14)
> > From: Arnd Bergmann
> >
> > Randconfig builds on 32-bit machines show lots of warnings for
> > the i915 driver for incorrect bit masks like:
>
> mask is a u8.
>
> VCS0 is 2, I915_MAX_VCS 4
>
>
== Series Details ==
Series: series starting with [1/6] drm/i915/selftests: Set error returns
URL : https://patchwork.freedesktop.org/series/85440/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9541_full -> Patchwork_19245_full
Quoting Souza, Jose (2021-01-04 14:50:59)
> On Thu, 2020-12-31 at 09:17 +, Chris Wilson wrote:
> > Quoting Almahallawy, Khaled (2020-12-31 01:24:34)
> > > On Wed, 2020-12-30 at 16:02 -0800, Matt Roper wrote:
> > > > On Wed, Dec 30, 2020 at 10:37:42AM +, Chris Wilson wrote:
> > > > > The
== Series Details ==
Series: drm/i915/gt: Replace open-coded intel_engine_stop_cs() (rev2)
URL : https://patchwork.freedesktop.org/series/84726/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9542 -> Patchwork_19247
Summary
On Thu, 2020-12-31 at 09:17 +, Chris Wilson wrote:
> Quoting Almahallawy, Khaled (2020-12-31 01:24:34)
> > On Wed, 2020-12-30 at 16:02 -0800, Matt Roper wrote:
> > > On Wed, Dec 30, 2020 at 10:37:42AM +, Chris Wilson wrote:
> > > > The timeouts are frequent and expected. We will complain
On Mon, 28 Dec 2020, "Gupta, Anshuman" wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Jani
>> Nikula
>> Sent: Tuesday, December 22, 2020 8:20 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani
>> Subject: [Intel-gfx] [PATCH 01/13] drm/i915/pps: abstract panel
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Rearrange snb workarounds
URL : https://patchwork.freedesktop.org/series/85439/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9541_full -> Patchwork_19244_full
== Series Details ==
Series: drm/i915/gt: Replace open-coded intel_engine_stop_cs() (rev2)
URL : https://patchwork.freedesktop.org/series/84726/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7254e1abeb33 drm/i915/gt: Replace open-coded intel_engine_stop_cs()
-:32:
== Series Details ==
Series: series starting with [v10,1/5] drm: Add function to convert rect in
16.16 fixed format to regular format
URL : https://patchwork.freedesktop.org/series/85441/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9542 -> Patchwork_19246
When flushing objects larger than the CPU cache it is preferrable to use
a single wbinvd() rather than overlapping clflush(). At runtime, we
avoid wbinvd() due to its system-wide latencies, but during
singlethreaded suspend, no one will observe the imposed latency and we
can opt for the faster
When flushing objects larger than the CPU cache it is preferrable to use
a single wbinvd() rather than overlapping clflush(). At runtime, we
avoid wbinvd() due to its system-wide latencies, but during
singlethreaded suspend, no one will observe the imposed latency and we
can opt for the faster
== Series Details ==
Series: series starting with [v10,1/5] drm: Add function to convert rect in
16.16 fixed format to regular format
URL : https://patchwork.freedesktop.org/series/85441/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used,
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
v5: Addressed JJani Nikula's review comments
- Remove checking of Gen12 for
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt
== Series Details ==
Series: series starting with [1/6] drm/i915/selftests: Set error returns
URL : https://patchwork.freedesktop.org/series/85440/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9541 -> Patchwork_19245
== Series Details ==
Series: series starting with [1/6] drm/i915/selftests: Set error returns
URL : https://patchwork.freedesktop.org/series/85440/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a79946cc2df2 drm/i915/selftests: Set error returns
ad716358ae5b drm/i915: Set
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Rearrange snb workarounds
URL : https://patchwork.freedesktop.org/series/85439/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9541 -> Patchwork_19244
In the legacy ringbuffer submission, we still had an open-coded version
of intel_engine_stop_cs() with one addition verification step. Transfer
that verification to intel_engine_stop_cs() itself, and call it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 15
From: José Roberto de Souza
Now using plane damage clips property to calcualte the damaged area.
Selective fetch only supports one region to be fetched so software
needs to calculate a bounding box around all damage clips.
Now that we are not complete fetching each plane, there is another
loop
From: José Roberto de Souza
It programs Plane's calculated x, y, offset to Plane SF register.
It does the calculation of x and y offsets using
skl_calc_main_surface_offset().
v3: Update commit message
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Reviewed-by:
From: José Roberto de Souza
Enabling it to check if it causes regressions in CI but the feature is
still not ready to be enabled by default.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: José Roberto de Souza
The calculation the offsets of the main surface will be needed by PSR2
selective fetch code so here splitting and exporting it.
No functional changes were done here.
v3: Rebased
v10: Rebased
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Signed-off-by: José Roberto de
From: José Roberto de Souza
Much more clear to read one function call than four lines doing this
conversion.
v7:
- function renamed
- calculating width and height before truncate
- inlined
Cc: Ville Syrjälä
Cc: dri-de...@lists.freedesktop.org
Cc: Gwan-gyeong Mun
Signed-off-by: José Roberto
== Series Details ==
Series: drm/i915/debugfs : PM_REQ and PM_RES registers
URL : https://patchwork.freedesktop.org/series/85437/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
Before we mark the virtual engine as no longer inflight, flush any
ongoing signaling that may be using the ce->signal_link along the
previous breadcrumbs. On switch to a new physical engine, that link will
be inserted into the new set of breadcrumbs, causing confusion to an
ongoing iterator.
This
In the next patch, we remove the strict priority system and continuously
re-evaluate the relative priority of tasks. As such we need to enable
the timeslice whenever there is more than one context in the pipeline.
This simplifies the decision and removes some of the tweaks to suppress
timeslicing,
If the engine reset fails, we will attempt to resume with the current
inflight submissions. When that happens, we cannot assert that the
engine reset cleared the pending submission, so do not.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2878
Fixes: 16f2941ad307 ("drm/i915/gt:
A few missed PTR_ERR() upon create_gang() errors.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_execlists.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c
b/drivers/gpu/drm/i915/gt/selftest_execlists.c
If another sibling is able to claim the virtual request, by the time we
inspect the request under the lock if may no longer match the local
engine.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2877
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
Fixes: f170523a7b8e ("drm/i915/gt: Consolidate the CS timestamp clocks")
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 54 +++--
1 file changed, 29
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 67 ++---
1 file changed, 33
Only run the tests on the available engines using igt_dynamic. This
prevents flip-flops with SKIP on shards that have a mixture of machine
types (e.g. shard-icl that has some machines with vcs1 and some
without).
Signed-off-by: Chris Wilson
---
tests/i915/gem_spin_batch.c | 82
From: Saichandana
PM_REQ register provides the value of the last PM request from PCU to
Display Engine.PM_RES register provides the value of the last PM
response from Display Engine to PCU.This debugfs will be used by
DC9 IGT test to know about "DC9 Ready" status.
B.Spec : 49501, 49502
Hi,
it looks like this PR has not been merged yet.
Best regard
Thomas
Am 22.12.20 um 20:13 schrieb Thomas Zimmermann:
Hi Dave and Daniel,
here's this week's PR for drm-misc-next-fixes.
Best regards
Thomas
drm-misc-next-fixes-2020-12-22:
Short summary of fixes pull:
* dma-buf: Include
87 matches
Mail list logo
