== Series Details ==
Series: drm/i915/gem: missing boundary check in vm_access leads to OOB
read/write
URL : https://patchwork.freedesktop.org/series/100932/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11308 -> Patchwork_22460
On Tue, 2022-03-01 at 19:13 -0800, Niranjana Vishwanathapura wrote:
> On Tue, Feb 22, 2022 at 06:10:29PM +0100, Thomas Hellström wrote:
> > It's unclear what reference the initial vma kref reference refers
> > to.
> > A vma can have multiple weak references, the object vma list,
> > the vm's bound
== Series Details ==
Series: drm/i915/gem: missing boundary check in vm_access leads to OOB
read/write
URL : https://patchwork.freedesktop.org/series/100932/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e4e38dbb19da drm/i915/gem: missing boundary check in vm_access leads to
== Series Details ==
Series: i915: Prepare for Xe_HP compute engines (rev4)
URL : https://patchwork.freedesktop.org/series/100833/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11308 -> Patchwork_22459
Summary
---
== Series Details ==
Series: i915: Prepare for Xe_HP compute engines (rev4)
URL : https://patchwork.freedesktop.org/series/100833/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: i915: Prepare for Xe_HP compute engines (rev4)
URL : https://patchwork.freedesktop.org/series/100833/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ba39c8793670 drm/i915/xehp: Define compute class and engine
290898d45efe drm/i915/xehp: CCS shares
Intel ID: PSIRT-PTK0002429
A missing bounds check in vm_access() in
drivers/gpu/drm/i915/gem/i915_gem_mman.c
can lead to an out-of-bounds read or write in the adjacent memory area.
The len attribute is not validated before the memcpy at [1]or [2] occurs.
[ 183.637831] BUG: unable to handle
== Series Details ==
Series: iommu/vt-d: Add RPLS to quirk list to skip TE disabling (rev3)
URL : https://patchwork.freedesktop.org/series/100165/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11308 -> Patchwork_22458
From: Daniele Ceraolo Spurio
HW resources are divided across the active CCS engines at the compute
slice level, with each CCS having priority on one of the cslices.
If a compute slice has no enabled DSS, its paired compute engine is not
usable in full parallel execution because the other ones
== Series Details ==
Series: drm/i915/gt: Clear compress metadata for Xe_HP platforms (rev2)
URL : https://patchwork.freedesktop.org/series/100856/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11306_full -> Patchwork_22454_full
The VT-d spec requires (10.4.4 Global Command Register, TE
field) that:
Hardware implementations supporting DMA draining must drain
any in-flight DMA read/write requests queued within the
Root-Complex before completing the translation enable
command and reflecting the status of the command
== Series Details ==
Series: drm/amdgpu: add drm buddy support to amdgpu
URL : https://patchwork.freedesktop.org/series/100908/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11306_full -> Patchwork_22453_full
Summary
On Tue, Feb 22, 2022 at 06:10:30PM +0100, Thomas Hellström wrote:
vms are not getting properly closed. Rather than fixing that,
Remove the vm open count and instead rely on the vm refcount.
The vm open count existed solely to break the strong references the
vmas had on the vms. Now instead make
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev2)
URL : https://patchwork.freedesktop.org/series/100899/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11306_full -> Patchwork_22450_full
Summary
---
== Series Details ==
Series: Prep work for next GuC release (rev4)
URL : https://patchwork.freedesktop.org/series/99805/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11308 -> Patchwork_22457
Summary
---
**SUCCESS**
On Tue, Feb 22, 2022 at 06:10:29PM +0100, Thomas Hellström wrote:
It's unclear what reference the initial vma kref reference refers to.
A vma can have multiple weak references, the object vma list,
the vm's bound list and the GT's closed_list, and the initial vma
reference can be put from
== Series Details ==
Series: i915: Prepare for Xe_HP compute engines (rev3)
URL : https://patchwork.freedesktop.org/series/100833/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11308 -> Patchwork_22456
Summary
---
== Series Details ==
Series: Prep work for next GuC release (rev4)
URL : https://patchwork.freedesktop.org/series/99805/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Hi Arunpravin,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next v5.17-rc6 next-20220301]
[If your patch is applied to the wrong git tree, kindly drop us a note
== Series Details ==
Series: i915: Prepare for Xe_HP compute engines (rev3)
URL : https://patchwork.freedesktop.org/series/100833/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: i915: Prepare for Xe_HP compute engines (rev3)
URL : https://patchwork.freedesktop.org/series/100833/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d5cf9daabfdf drm/i915/xehp: Define compute class and engine
01194092d81e drm/i915/xehp: CCS shares
== Series Details ==
Series: drm/i915/ttm: Evict and store of compressed object (rev2)
URL : https://patchwork.freedesktop.org/series/99759/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11308 -> Patchwork_22455
Summary
== Series Details ==
Series: drm/i915/ttm: Evict and store of compressed object (rev2)
URL : https://patchwork.freedesktop.org/series/99759/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/ttm: Evict and store of compressed object (rev2)
URL : https://patchwork.freedesktop.org/series/99759/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9108a19bd675 drm/i915/gt: Clear compress metadata for Xe_HP platforms
03b09cc7472c
Hi all,
On Thu, 20 Jan 2022 14:26:39 +1100 Stephen Rothwell
wrote:
>
> On Wed, 17 Nov 2021 13:49:26 +1100 Stephen Rothwell
> wrote:
> >
> > After merging the drm-misc tree, today's linux-next build (htmldocs)
> > produced this warning:
> >
> > include/drm/gpu_scheduler.h:316: warning:
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check for
context registration, use the GuC id instead (being the thing that
actually gets registered with the GuC).
Also, rename the set/clear/query helper functions for context id
mappings to better reflect
From: John Harrison
The LRC descriptor pool is going away. So, stop naming context ids as
descriptor pool indecies.
While at it, add a bunch of missing line feeds to some error messages.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
From: John Harrison
The LRC descriptor was being initialised early on in the context
registration sequence. It could then be determined that the actual
registration needs to be delayed and the descriptor would be wiped
out. This is inefficient, so move the setup to later in the process
after the
From: John Harrison
The CTB registration process changed significantly a while back using
a single KLV based H2G. So drop the original and now obsolete H2G
definitions.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2
From: John Harrison
Some G2H handlers were reading the context id field from the payload
before checking the payload met the minimum length required.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 --
1 file
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check
for whether submission has been initialised or not.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
From: John Harrison
The next GuC firmware release includes some significant backwards
breaking API changes. One such is that there is no longer an LRC
descriptor pool. A bunch of prep work for that change can be done in
advance - the descriptor pool was being used for things it shouldn't
really
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as the limit
for how many context ids are available. Instead, size the pool
according to the number of contexts allowed. Note that this is just a
naming change, the actual limit is identical in value.
While at it, also
From: John Harrison
The LRC descriptor pool is going away. Further, the function that was
populating it was also doing a bunch of logic about the context
registration sequence. So, split that code apart into separate state
setup and try to register functions. Note that some of those 'try to
On Tue, Mar 01, 2022 at 03:15:45PM -0800, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> Tell GuC that CCS is enabled by setting a bit in its ADS.
>
> Cc: Vinay Belgaumkar
> Original-author: Michel Thierry
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Matt Roper
We have to specify in the Render Control Unit Mode register
when CCS is enabled.
v2:
- Move RCU_MODE programming to a helper function. (Tvrtko)
- Clean up and clarify comments. (Tvrtko)
- Add RCU_MODE to the GuC save/restore list. (Daniele)
v3:
- Move this patch before the GuC ADS update
== Series Details ==
Series: drm/i915/gt: Clear compress metadata for Xe_HP platforms (rev2)
URL : https://patchwork.freedesktop.org/series/100856/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11306 -> Patchwork_22454
On Tue, Mar 01, 2022 at 03:15:49PM -0800, Matt Roper wrote:
> From: Srinivasan Shanmugam
>
> Registers that exist in the shared render/compute reset domain need to
> be placed on an engine workaround list to ensure that they are properly
> re-applied whenever an RCS or CCS engine is reset. We
On Tue, Mar 01, 2022 at 03:51:21PM -0800, Umesh Nerlige Ramappa wrote:
> On Tue, Mar 01, 2022 at 03:15:44PM -0800, Matt Roper wrote:
> > We have to specify in the Render Control Unit Mode register
> > when CCS is enabled.
> >
> > v2:
> > - Move RCU_MODE programming to a helper function. (Tvrtko)
On Tue, Mar 1, 2022 at 3:19 PM David Laight wrote:
>
> Having said that there are so few users of list_entry_is_head()
> it is reasonable to generate two new names.
Well, the problem is that the users of list_entry_is_head() may be few
- but there are a number of _other_ ways to check "was that
On Tue, Mar 01, 2022 at 03:15:44PM -0800, Matt Roper wrote:
We have to specify in the Render Control Unit Mode register
when CCS is enabled.
v2:
- Move RCU_MODE programming to a helper function. (Tvrtko)
- Clean up and clarify comments. (Tvrtko)
- Add RCU_MODE to the GuC save/restore list.
On Tue, Mar 01, 2022 at 03:15:47PM -0800, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> HW resources are divided across the active CCS engines at the compute
> slice level, with each CCS having priority on one of the cslices.
> If a compute slice has no enabled DSS, its paired compute
== Series Details ==
Series: drm/amdgpu: add drm buddy support to amdgpu
URL : https://patchwork.freedesktop.org/series/100908/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11306 -> Patchwork_22453
Summary
---
On 3/1/2022 3:15 PM, Matt Roper wrote:
From: Daniele Ceraolo Spurio
Tell GuC that CCS is enabled by setting a bit in its ADS.
It's a mask, not a bit.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Cc: Vinay Belgaumkar
Original-author: Michel Thierry
Signed-off-by: Daniele Ceraolo
On Tue, Mar 1, 2022 at 2:00 PM Patchwork
wrote:
>
> == Series Details ==
>
> Series: use dynamic-debug under drm.debug api (rev2)
> URL : https://patchwork.freedesktop.org/series/100289/
> State : warning
>
> == Summary ==
>
> $ dim sparse --fast origin/drm-tip
> Sparse version: v0.6.2
> Fast
On Tue, Mar 01, 2022 at 09:34:54PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 01, 2022 at 11:30:52AM -0800, Navare, Manasi wrote:
> > Hi Ville,
> >
> > Does it make sense to add the set prop in intel_dp_Set_edid but keep the
> > reset to false
> > in intel_dp_detect where we clear other
From: Linus Torvalds
> Sent: 01 March 2022 23:03
>
> On Tue, Mar 1, 2022 at 2:58 PM David Laight wrote:
> >
> > Can it be resolved by making:
> > #define list_entry_is_head(pos, head, member) ((pos) == NULL)
> > and double-checking that it isn't used anywhere else (except in
> > the list macros
On Tue, Mar 1, 2022 at 2:32 PM Patchwork
wrote:
>
> Patch Details
> Series:use dynamic-debug under drm.debug api (rev2)
> URL:https://patchwork.freedesktop.org/series/100289/
> State:failure
> Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22448/index.html
>
> CI Bug Log - changes
From: Daniele Ceraolo Spurio
HW resources are divided across the active CCS engines at the compute
slice level, with each CCS having priority on one of the cslices.
If a compute slice has no enabled DSS, its paired compute engine is not
usable in full parallel execution because the other ones
From: Daniele Ceraolo Spurio
Tell GuC that CCS is enabled by setting a bit in its ADS.
Cc: Vinay Belgaumkar
Original-author: Michel Thierry
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
1 file changed, 1 insertion(+)
In Dual Context mode the EUs are shared between render and compute
command streamers. The hardware provides a field in the lrc descriptor
to indicate the prioritization of the thread dispatch associated to the
corresponding context.
The context priority is set to 'low' at creation time and relies
From: Srinivasan Shanmugam
Registers that exist in the shared render/compute reset domain need to
be placed on an engine workaround list to ensure that they are properly
re-applied whenever an RCS or CCS engine is reset. We have a number of
workarounds (updating registers MLTICTXCTL,
From: Matthew Brost
A different emit breadcrumbs ring programming is required for compute /
render and we don't have UMD user so just reject parallel submission for
these engine classes.
Signed-off-by: Matthew Brost
Signed-off-by: Matt Roper
Reviewed-by: Daniele Ceraolo Spurio
---
Additional workarounds are required once we start exposing CCS engines.
Note that we have a number of workarounds that update registers in the
shared render/compute reset domain. Historically we've just added such
registers to the RCS engine's workaround list. But going forward we
should be
From: Daniele Ceraolo Spurio
CCS will reuse the RCS functions for breadcrumb and flush emission.
However, CCS pipe_control has additional programming restrictions:
- Command Streamer Stall Enable must be always set
- Post Sync Operations must not be set to Write PS Depth Count
- 3D-related
The compute engine handles the same commands the render engine can
(except 3D pipeline), so it makes sense that CCS is more similar to RCS
than non-render engines.
The CCS context state (lrc) is also similar to the render one, so reuse
it. Note that the compute engine has its own
We have to specify in the Render Control Unit Mode register
when CCS is enabled.
v2:
- Move RCU_MODE programming to a helper function. (Tvrtko)
- Clean up and clarify comments. (Tvrtko)
- Add RCU_MODE to the GuC save/restore list. (Daniele)
v3:
- Move this patch before the GuC ADS update
This is a more appropriate header for these definitions.
v2:
- Cleanup whitespace. (Lucas)
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 34 ---
The reset domain is shared between render and all compute engines,
so resetting one will affect the others.
Note: Before performing a reset on an RCS or CCS engine, the GuC will
attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
impacting other clients (since some shared
Add execlists and GuC interrupts for compute CS into existing IRQ handlers.
All compute command streamers belong to the same compute class, so the
only change needed to enable their interrupts is to program their GT engine
interrupt mask registers.
CCS0 shares the register with CCS1, while CCS2
The Xe_HP architecture introduces compute engines as a new engine class.
These compute command streamers (CCS) are similar to the render engine,
except that they're intended for GPGPU usage and lack support for the 3D
pipeline.
For now we're just sending some initial "under the hood" preparation
Introduce a Compute Command Streamer (CCS), which has access to
the media and GPGPU pipelines (but not the 3D pipeline).
To begin with, define the compute class/engine common functions, based
on the existing render ones.
v2:
- Add kerneldoc for drm_i915_gem_engine_class since we're adding a new
== Series Details ==
Series: drm/amdgpu: add drm buddy support to amdgpu
URL : https://patchwork.freedesktop.org/series/100908/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8e830a55eacb drm/amdgpu: add drm buddy support to amdgpu
-:76: CHECK:PREFER_KERNEL_TYPES: Prefer kernel
On Tue, Mar 1, 2022 at 2:58 PM David Laight wrote:
>
> Can it be resolved by making:
> #define list_entry_is_head(pos, head, member) ((pos) == NULL)
> and double-checking that it isn't used anywhere else (except in
> the list macros themselves).
Well, yes, except for the fact that then the name
== Series Details ==
Series: drm/i915: Clean up some dpll stuff (rev2)
URL : https://patchwork.freedesktop.org/series/100899/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11306 -> Patchwork_22450
Summary
---
From: Linus Torvalds
> Sent: 01 March 2022 19:07
> On Mon, Feb 28, 2022 at 2:29 PM James Bottomley
> wrote:
> >
> > However, if the desire is really to poison the loop variable then we
> > can do
> >
> > #define list_for_each_entry(pos, head, member) \
> > for
== Series Details ==
Series: Remove usage of list iterator past the loop body (rev4)
URL : https://patchwork.freedesktop.org/series/100822/
State : failure
== Summary ==
Applying: drivers: usb: remove usage of list iterator past the loop body
Patch is empty.
When you have resolved this
== Series Details ==
Series: RFC: nested AVIC
URL : https://patchwork.freedesktop.org/series/100904/
State : failure
== Summary ==
Applying: KVM: x86: SVM: move nested_npt_enabled to svm.h
Applying: KVM: x86: SVM: allow AVIC to co-exist with a nested guest running
error: sha1 information is
On Mon, Feb 28, 2022 at 09:42:43AM -0800, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> HW resources are divided across the active CCS engines at the compute
> slice level, with each CCS having priority on one of the cslices.
> If a compute slice has no enabled DSS, its paired compute
On Tue, 01 Mar 2022 03:03:59 -0800, Matthew Auld wrote:
>
> The shmem mmap and pwrite interfaces conveniently let us probe just a
> few pages, without needing to populate the entire object. On discrete
> and newer platforms the kernel has dropped support for both, leaving us
> with MMAP_OFFSET,
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gtt: reduce overzealous
alignment constraints for GGTT
URL : https://patchwork.freedesktop.org/series/100898/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11306 -> Patchwork_22449
On 2/24/2022 5:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
It is possible for reset notifications to arrive for a context that is
in the process of being banned. So don't flag these as an error, just
report it as informational (because it is still useful to know that
resets
When we are swapping out the local memory obj on flat-ccs capable platform,
we need to capture the ccs data too along with main meory and we need to
restore it when we are swapping in the content.
When lmem object is swapped into a smem obj, smem obj will
have the extra pages required to hold the
On Xe-HP and later devices, we use dedicated compression control
state (CCS) stored in local memory for each surface, to support the
3D and media compression formats.
The memory required for the CCS of the entire local memory is 1/256 of
the local memory size. So before the kernel boot, the
From: Ayaz A Siddiqui
Xe-HP and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated
CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
When a driver needs extra pages in ttm_tt, to facilidate such
requirement, parameter called "extra_pages" is added for
ttm_tt_init
Signed-off-by: Ramalingam C
cc: Christian Koenig
cc: Hellstrom Thomas
---
drivers/gpu/drm/drm_gem_vram_helper.c | 2 +-
On Xe-HP and later devices, we use dedicated compression control
state (CCS) stored in local memory for each surface, to support
the 3D and media compression formats.
The memory required for the CCS of the entire local memory is
1/256 of the local memory size. So before the kernel
boot, the
From: Ayaz A Siddiqui
Xe-HP and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated
CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
On 2/25/2022 22:27, Alan Previn wrote:
Fix our pointer offset usage in error_state_read
when there is no i915_gpu_coredump but buf offset
is non-zero.
This fixes a kernel page fault can happen when
multiple tests are running concurrently in a loop
and one is producing engine resets and
== Series Details ==
Series: use dynamic-debug under drm.debug api (rev2)
URL : https://patchwork.freedesktop.org/series/100289/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11306 -> Patchwork_22448
Summary
---
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gtt: reduce overzealous
alignment constraints for GGTT
URL : https://patchwork.freedesktop.org/series/100898/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
61b713195d33 drm/i915/gtt: reduce overzealous
== Series Details ==
Series: use dynamic-debug under drm.debug api (rev2)
URL : https://patchwork.freedesktop.org/series/100289/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On 3/1/2022 04:09, Tvrtko Ursulin wrote:
I'll trim it a bit again..
On 28/02/2022 18:55, John Harrison wrote:
On 2/28/2022 09:12, Tvrtko Ursulin wrote:
On 25/02/2022 18:48, John Harrison wrote:
On 2/25/2022 10:14, Tvrtko Ursulin wrote:
[snip]
Your only objection is that ends up with too
== Series Details ==
Series: use dynamic-debug under drm.debug api (rev2)
URL : https://patchwork.freedesktop.org/series/100289/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c2ed9cc02d9c dyndbg: fix static_branch manipulation
a8f6c71f283e dyndbg: add class_id field and query
So looking at this patch, I really reacted to the fact that quite
often the "use outside the loop" case is all kinds of just plain
unnecessary, but _used_ to be a convenience feature.
I'll just quote the first chunk in it's entirely as an example - not
because I think this chunk is particularly
> On 1. Mar 2022, at 18:36, Greg KH wrote:
>
> On Tue, Mar 01, 2022 at 12:28:15PM +0100, Jakob Koschel wrote:
>>
>>
>>> On 1. Mar 2022, at 01:41, Linus Torvalds
>>> wrote:
>>>
>>> On Mon, Feb 28, 2022 at 1:47 PM Jakob Koschel
>>> wrote:
The goal of this is to get compiler
On Mon, Feb 28, 2022 at 11:32 AM Arnd Bergmann wrote:
>
> -under ``-std=gnu89`` [gcc-c-dialect-options]_: the GNU dialect of ISO C90
> -(including some C99 features). ``clang`` [clang]_ is also supported, see
> +under ``-std=gnu11`` [gcc-c-dialect-options]_: the GNU dialect of ISO C11
>
On Mon, Feb 28, 2022 at 10:41 PM Fangrui Song wrote:
> >
> >More precisely, the semantics of "extern inline" functions changed
> >between ISO C90 and ISO C99.
>
> Perhaps a clearer explanation to readers is: "extern inline" and "inline" swap
> semantics with gnu_inline (-fgnu89-inline or
> On 1. Mar 2022, at 01:41, Linus Torvalds
> wrote:
>
> On Mon, Feb 28, 2022 at 1:47 PM Jakob Koschel wrote:
>>
>> The goal of this is to get compiler warnings right? This would indeed be
>> great.
>
> Yes, so I don't mind having a one-time patch that has been gathered
> using some
On Tue, Mar 1, 2022 at 11:43 AM Miguel Ojeda
wrote:
>
> On Mon, Feb 28, 2022 at 11:32 AM Arnd Bergmann wrote:
> >
> > -under ``-std=gnu89`` [gcc-c-dialect-options]_: the GNU dialect of ISO C90
> > -(including some C99 features). ``clang`` [clang]_ is also supported, see
> > +under ``-std=gnu11``
On 3/1/2022 02:50, Tvrtko Ursulin wrote:
On 28/02/2022 18:32, John Harrison wrote:
On 2/28/2022 08:11, Tvrtko Ursulin wrote:
On 25/02/2022 17:39, John Harrison wrote:
On 2/25/2022 09:06, Tvrtko Ursulin wrote:
On 24/02/2022 19:19, John Harrison wrote:
[snip]
./gt/uc/intel_guc_fwif.h: u32
On Tue, Mar 1, 2022 at 11:06 AM Linus Torvalds
wrote:
>
> So instead of that simple "if (!entry)", we'd effectively have to
> continue to use something that still works with the old world order
> (ie that "if (list_entry_is_head())" model).
Just to prove my point about how this is painful, that
On Tue, Mar 01, 2022 at 11:30:52AM -0800, Navare, Manasi wrote:
> Hi Ville,
>
> Does it make sense to add the set prop in intel_dp_Set_edid but keep the
> reset to false
> in intel_dp_detect where we clear other parameters?
We don't clear stuff in .detect(), or at least shouldn't. .detect()
On Tue, Feb 22, 2022 at 02:04:21PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
This will be useful to have at hand in a following patch.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 11 ++-
drivers/gpu/drm/i915/i915_drv.h | 1 +
2
On 2/28/2022 9:42 AM, Matt Roper wrote:
Additional workarounds are required once we start exposing CCS engines.
Note that we have a number of workarounds that update registers in the
shared render/compute reset domain. Historically we've just added such
registers to the RCS engine's
Hi Ville,
Does it make sense to add the set prop in intel_dp_Set_edid but keep the reset
to false
in intel_dp_detect where we clear other parameters?
Manasi
On Fri, Feb 25, 2022 at 05:11:02PM -0800, Navare, Manasi wrote:
> On Fri, Feb 25, 2022 at 11:13:35AM +0200, Ville Syrjälä wrote:
> > On
== Series Details ==
Series: drm/mm: Add an iterator to optimally walk over holes suitable for an
allocation (rev2)
URL : https://patchwork.freedesktop.org/series/100847/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11302_full -> Patchwork_22447_full
On Mon, Feb 28, 2022 at 2:29 PM James Bottomley
wrote:
>
> However, if the desire is really to poison the loop variable then we
> can do
>
> #define list_for_each_entry(pos, head, member) \
> for (pos = list_first_entry(head, typeof(*pos), member);\
>
On 2/28/2022 9:42 AM, Matt Roper wrote:
From: Matthew Brost
A different emit breadcrumbs ring programming is required for compute /
render and we don't have UMD user so just reject parallel submission for
these engine classes.
Signed-off-by: Matthew Brost
Signed-off-by: Matt Roper
On Tue, Mar 01, 2022 at 10:14:07AM -0800, Kees Cook wrote:
> On Mon, Feb 28, 2022 at 04:45:11PM -0800, Linus Torvalds wrote:
> > Really. The "-Wshadow doesn't work on the kernel" is not some new
> > issue, because you have to do completely insane things to the source
> > code to enable it.
>
>
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