Hi All,
Gentle Reminder
Regards,
Suraj Kandpal
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_acpi.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 89 +-
> drivers/gpu/drm/i915/display/intel_display.h | 9 +
>
== Series Details ==
Series: drm/i915/dg1: remove redundant uc_index assignment
URL : https://patchwork.freedesktop.org/series/101765/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11403_full -> Patchwork_22676_full
== Series Details ==
Series: drm/i915/dg1: remove redundant uc_index assignment
URL : https://patchwork.freedesktop.org/series/101765/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22676
Summary
---
== Series Details ==
Series: drm/i915/dg1: remove redundant uc_index assignment
URL : https://patchwork.freedesktop.org/series/101765/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
== Series Details ==
Series: drm/i915/hwconfig: Add DG2 support
URL : https://patchwork.freedesktop.org/series/101760/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11403_full -> Patchwork_22674_full
Summary
---
Just clean up the redundant uc_index assignment for DG1.
Signed-off-by: Chuansheng Liu
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c4c37585ae8c..0c300727a5c2 100644
== Series Details ==
Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev4)
URL : https://patchwork.freedesktop.org/series/100532/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22675
Summary
== Series Details ==
Series: drm/i915: fix one mem leak in mmap_offset_attach() (rev4)
URL : https://patchwork.freedesktop.org/series/100532/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable'
== Series Details ==
Series: drm/i915/hwconfig: Add DG2 support
URL : https://patchwork.freedesktop.org/series/101760/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11403 -> Patchwork_22674
Summary
---
**SUCCESS**
The below memory leak information is caught:
unreferenced object 0x997dd4e3b240 (size 64):
comm "gem_tiled_fence", pid 10332, jiffies 4294959326 (age
220778.420s)
hex dump (first 32 bytes):
01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
== Series Details ==
Series: drm/i915/hwconfig: Add DG2 support
URL : https://patchwork.freedesktop.org/series/101760/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
found
From: Rodrigo Vivi
DG2 support for hwconfig tables varies by both SKU and stepping.
Signed-off-by: Rodrigo Vivi
Signed-off-by: John Harrison
Signed-off-by: Ramalingam C
Tested-by: Jordan Justen
---
drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c | 2 ++
1 file changed, 2 insertions(+)
On Thu, 2022-03-24 at 08:39 +, Murthy, Arun R wrote:
> > }
> >
> > +static unsigned int dg2_max_bw(struct drm_i915_private *i915) {
> > + struct intel_bw_info *bi = >max_bw[0];
> > +
> > + return bi->deratedbw[0];
> > +}
>
> Would it look better to have this as a macro rather than a
== Series Details ==
Series: series starting with [1/2] drm/i915/display/psr: Set partial frame
enable when forcing full frame fetch
URL : https://patchwork.freedesktop.org/series/101752/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11402_full -> Patchwork_22673_full
== Series Details ==
Series: lmem_size modparam
URL : https://patchwork.freedesktop.org/series/101744/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11402_full -> Patchwork_22671_full
Summary
---
**FAILURE**
== Series Details ==
Series: series starting with [1/2] drm/i915/display/psr: Set partial frame
enable when forcing full frame fetch
URL : https://patchwork.freedesktop.org/series/101752/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11402 -> Patchwork_22673
== Series Details ==
Series: series starting with [1/2] drm/i915/display/psr: Set partial frame
enable when forcing full frame fetch
URL : https://patchwork.freedesktop.org/series/101752/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
On Thu, 24 Mar 2022, Tvrtko Ursulin wrote:
> On 24/03/2022 11:57, Jani Nikula wrote:
>> On Thu, 24 Mar 2022, Tvrtko Ursulin wrote:
>>> On 24/03/2022 09:31, Jani Nikula wrote:
On Tue, 22 Mar 2022, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> ...
>
> Signed-off-by:
Instead of exit PSR when a frontbuffer invalidation happens, we can
enable the PSR2 selective fetch continuous full frame, that will keep
the panel updated like PSR was disabled but without keeping PSR active.
So as soon as the frontbuffer flush happens we can disable the
continuous full frame
Following up what was done in commit 804f46885317 ("drm/i915/psr: Set
"SF Partial Frame Enable" also on full update") and also setting
partial frame enable when psr_force_hw_tracking_exit() is called.
Cc: Jouni Högander
Cc: Mika Kahola
Signed-off-by: José Roberto de Souza
---
== Series Details ==
Series: series starting with [1/2] drm/i915/ttm: limit where we apply
TTM_PL_FLAG_CONTIGUOUS
URL : https://patchwork.freedesktop.org/series/101749/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11402 -> Patchwork_22672
On Thu, 24 Mar 2022 07:26:20 -0700, Matthew Auld wrote:
>
> @@ -554,6 +560,7 @@ igt_main_args("", long_options, help_str, opt_handler,
> NULL)
> igt_fixture {
> free(regions);
> close(i915);
> + igt_i915_driver_unload();
I thought we'd reload the
On Thu, 24 Mar 2022 07:26:19 -0700, Matthew Auld wrote:
>
> @@ -353,14 +356,17 @@ static void test_evict(int i915,
> if (flags & TEST_PARALLEL) {
> int fd = gem_reopen_driver(i915);
>
> + ctx = intel_ctx_create_all_physical(fd);
> +
== Series Details ==
Series: series starting with [1/2] drm/i915/ttm: limit where we apply
TTM_PL_FLAG_CONTIGUOUS
URL : https://patchwork.freedesktop.org/series/101749/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1:
On Thu, 24 Mar 2022 07:26:18 -0700, Matthew Auld wrote:
>
> On DG2 the object size might be rounded when allocating lmem. Make sure
> we account for any rounding up.
Reviewed-by: Ashutosh Dixit
Move the sanity check that both src and dst are never both system
memory, which should never happen on discrete, and likely means we have
a bug. The only exception is on integrated where we trigger this path in
the selftests.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
We only need this when allocating device local-memory, where this
influences the drm_buddy. Currently there is some funny behaviour where
an "in limbo" system memory object is lacking the relevant placement
flags etc. before we first allocate the ttm_tt, leading to ttm
performing a move when not
== Series Details ==
Series: drm/i915/display: Extend DP HDR support to hsw+ (rev4)
URL : https://patchwork.freedesktop.org/series/101708/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11401_full -> Patchwork_22670_full
On 3/21/22 23:44, Ramalingam C wrote:
On Xe-HP and later devices, dedicated compression control state (CCS)
stored in local memory is used for each surface, to support the
3D and media compression formats.
The memory required for the CCS of the entire local memory is 1/256 of
the local memory
On 3/21/22 23:44, Ramalingam C wrote:
Handle the src and dst chunk offsets for different instances of the copy
engines.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
On Tue, Feb 01, 2022 at 04:11:30PM +0530, Ramalingam C wrote:
> From: Anshuman Gupta
>
> DG2 onwards discrete gfx has support for new flat CCS mapping,
> which brings in display feature in to avoid Aux walk for compressed
> surface. This support build on top of Flat CCS support added in XEHPSDV.
Hi, Ram
On 3/21/22 23:44, Ramalingam C wrote:
Xe-HP and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated
CCS buffer.
XY_CTRL_SURF_COPY_BLT is a
== Series Details ==
Series: lmem_size modparam
URL : https://patchwork.freedesktop.org/series/101744/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11402 -> Patchwork_22671
Summary
---
**SUCCESS**
No regressions
LGTM Reviewed-by: Nirmoy Das
On 3/24/2022 3:31 PM, Matthew Auld wrote:
From: CQ Tang
lmem_size is used to limit the amount of lmem. Default is to use
hardware available lmem size, when setting this modpraram which is in MB
unit.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
Cc:
== Series Details ==
Series: lmem_size modparam
URL : https://patchwork.freedesktop.org/series/101744/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
found
On 3/21/22 23:44, Ramalingam C wrote:
Move the static calculations out of the loops for copy and clear.
Signed-off-by: Ramalingam C
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 44 -
1 file changed, 21 insertions(+), 23
== Series Details ==
Series: lmem_size modparam
URL : https://patchwork.freedesktop.org/series/101744/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Hi i915 maintainers, this is your Linux kernel regression tracker!
What's up with the following regression?
https://gitlab.freedesktop.org/drm/intel/-/issues/5284
That report it more than two weeks old now, but seems nothing of
substance happened. And the thing is: the report is older, as the
On 24/03/2022 14:26, Matthew Auld wrote:
DG2 seems to have too many physical engines, and during execbuf just hits:
FWIW it's not that DG2 has too many engines but the test was apparently
broken (because considering legacy eb ring selector as consecutive index
namespace within total number
On Thu, Mar 24, 2022 at 01:42:33AM +0200, Chery, Nanley G wrote:
> > -Original Message-
> > From: Deak, Imre
> > Sent: Monday, March 21, 2022 6:20 AM
> > To: Chery, Nanley G ; Juha-Pekka Heikkila
> >
> > Cc: Nanley Chery ; C, Ramalingam
> > ; intel-gfx ;
> > Auld, Matthew ; dri-devel
On 3/24/22 15:26, Matthew Auld wrote:
From: CQ Tang
On some systems lmem can be as large as 16G, which seems to trigger
various CI timeouts, and in the best case just takes a long time. For
the purposes of the test we should be able to limit to 4G, without any
big loss in coverage.
Test-with: 20220324142621.347452-1-matthew.a...@intel.com
--
2.34.1
From: CQ Tang
lmem_size is used to limit the amount of lmem. Default is to use
hardware available lmem size, when setting this modpraram which is in MB
unit.
Signed-off-by: CQ Tang
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
300s is way too much for some BAT test. Drop it down to 45s.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
tests/i915/gem_lmem_swapping.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
From: CQ Tang
On some systems lmem can be as large as 16G, which seems to trigger
various CI timeouts, and in the best case just takes a long time. For
the purposes of the test we should be able to limit to 4G, without any
big loss in coverage.
Signed-off-by: CQ Tang
Signed-off-by: Matthew
DG2 seems to have too many physical engines, and during execbuf just hits:
"execbuf with unknown ring: 5"
Convert the test over to using the non-legacy API where we instead fill
the ctx with all the physical engines and then engine/ring becomes the
index into this.
Closes:
On DG2 the object size might be rounded when allocating lmem. Make sure
we account for any rounding up.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Nirmoy Das
---
tests/i915/gem_lmem_swapping.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git
--
2.34.1
On Thu, Mar 24, 2022 at 01:40:37AM +0200, Chery, Nanley G wrote:
> > [...]
> > Capturing all the above would you be ok with the following?:
> >
> > Intel color control surfaces (CCS) for DG2 render compression.
> >
> > The main surface is Tile 4 and at plane index 0. The CCS data is stored
> >
On 24/03/2022 11:57, Jani Nikula wrote:
On Thu, 24 Mar 2022, Tvrtko Ursulin wrote:
On 24/03/2022 09:31, Jani Nikula wrote:
On Tue, 22 Mar 2022, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
...
Signed-off-by: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Lucas De Marchi
---
Typed up how I see it
== Series Details ==
Series: drm/i915/display: Extend DP HDR support to hsw+ (rev4)
URL : https://patchwork.freedesktop.org/series/101708/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11401 -> Patchwork_22670
Summary
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, March 24, 2022 6:30 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v3] drm/i915/display: Extend DP HDR support to hsw+
>
> On Thu, Mar 24, 2022 at 11:58:15AM +, Shankar, Uma wrote:
> >
> >
>
The previous pull request tag was botched due to my key expiring, updated!
drm-misc-next-fixes-2022-03-24-1:
drm-misc-next-fixes for v5.18-rc1:
- Make audio and color plane support checking only happen
when a CEA extension block is found.
- Fix a small regression from ttm_resource_fini()
-
drm-misc-next-fixes-2022-03-24:
Short summary of fixes pull (less than what git shortlog provides):
- explain anything non-fixes (e.g. cleanups) and why it's appropriate
- highlight regressions
- summarize pull requests contained
This shouldn't be more than a few lines (or it indicates your fixes
On Thu, Mar 24, 2022 at 05:34:38PM +0530, Uma Shankar wrote:
> HSW+ platforms are able to send out HDR Metadata SDP DIP
> packet as GMP. Hence, extending the support for HDR on DP
> encoders for the same.
>
> v2: Limited to non eDP ports on hsw/bdw and removed it for
> lspcon as it is done
On Thu, Mar 24, 2022 at 11:58:15AM +, Shankar, Uma wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Thursday, March 24, 2022 5:12 PM
> > To: Shankar, Uma
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [v3] drm/i915/display: Extend DP HDR support to hsw+
On Thu, 2022-03-24 at 13:30 +0200, Ville Syrjälä wrote:
> On Tue, Mar 22, 2022 at 02:46:15PM -0700, José Roberto de Souza wrote:
> > PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
> > enabled but that could potentially cause issues as it could have
> > mismatching values while
== Series Details ==
Series: drm/i915/display: Extend DP HDR support to hsw+ (rev4)
URL : https://patchwork.freedesktop.org/series/101708/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
== Series Details ==
Series: drm/i915/display: Extend DP HDR support to hsw+ (rev2)
URL : https://patchwork.freedesktop.org/series/101708/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11398_full -> Patchwork_22669_full
HSW+ platforms are able to send out HDR Metadata SDP DIP
packet as GMP. Hence, extending the support for HDR on DP
encoders for the same.
v2: Limited to non eDP ports on hsw/bdw and removed it for
lspcon as it is done separately (suggested by Ville)
v3: Added helper and limited eDP restriction
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, March 24, 2022 5:12 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v3] drm/i915/display: Extend DP HDR support to hsw+
>
> On Thu, Mar 24, 2022 at 04:39:59PM +0530, Uma Shankar wrote:
> > HSW+
On Thu, 24 Mar 2022, Tvrtko Ursulin wrote:
> On 24/03/2022 09:31, Jani Nikula wrote:
>> On Tue, 22 Mar 2022, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin
>>>
>>> ...
>>>
>>> Signed-off-by: Tvrtko Ursulin
>>> Cc: Jani Nikula
>>> Cc: Lucas De Marchi
>>> ---
>>> Typed up how I see it - bash
On 24/03/2022 09:31, Jani Nikula wrote:
On Tue, 22 Mar 2022, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
...
Signed-off-by: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Lucas De Marchi
---
Typed up how I see it - bash away.
So is intel_vtd_active() so performance critical that it needs to be
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare()
URL : https://patchwork.freedesktop.org/series/101723/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11398_full -> Patchwork_22668_full
On Thu, Mar 24, 2022 at 04:39:59PM +0530, Uma Shankar wrote:
> HSW+ platforms are able to send out HDR Metadata SDP DIP
> packet as GMP. Hence, extending the support for HDR on DP
> encoders for the same.
>
> v2: Limited to non eDP ports on hsw/bdw and removed it for
> lspcon as it is done
On Tue, Mar 22, 2022 at 02:46:15PM -0700, José Roberto de Souza wrote:
> PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being
> enabled but that could potentially cause issues as it could have
> mismatching values while pipes are being enabled.
>
> So here moving the
On Tue, Mar 22, 2022 at 02:46:16PM -0700, José Roberto de Souza wrote:
> skl_compute_ddb() will for a modeset in all pipes when MBUS joining
> changes between states, so all pipes will be disabled, have all
> MBUS related registers updated and then each pipe enabled.
> So no vblank syncronization
HSW+ platforms are able to send out HDR Metadata SDP DIP
packet as GMP. Hence, extending the support for HDR on DP
encoders for the same.
v2: Limited to non eDP ports on hsw/bdw and removed it for
lspcon as it is done separately (suggested by Ville)
v3: Added helper and limited eDP restriction
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, March 24, 2022 3:12 PM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [v2] drm/i915/display: Extend DP HDR support to hsw+
>
> On Thu, Mar 24, 2022 at 02:42:15PM +0530, Uma Shankar wrote:
> > HSW+
On Wed, 23 Mar 2022 at 16:32, Christian König wrote:
>
> Am 23.03.22 um 16:24 schrieb Daniel Stone:
> > On Wed, 23 Mar 2022 at 15:14, Alex Deucher wrote:
> >> On Wed, Mar 23, 2022 at 11:04 AM Daniel Stone wrote:
> >>> That's not what anyone's saying here ...
> >>>
> >>> No-one's demanding AMD
On Wed, 23 Mar 2022, Ville Syrjälä wrote:
> On Wed, Mar 23, 2022 at 12:04:38PM +0200, Jani Nikula wrote:
>> Only an EDID CEA extension has byte #3, while the CTA DisplayID Data
>> Block does not. Don't interpret bogus data for color formats.
>
> I think what we might want eventually is a cleaner
On Thu, 24 Mar 2022, Lee Shawn C wrote:
> From: Cooper Chiou
>
> Tag code stored in bit7:5 for CTA block byte[3] is not the same as
> CEA extension block definition. Only check CEA block has
> basic audio support.
>
> v3: update commit message.
>
> Cc: sta...@vger.kernel.org
> Cc: Jani Nikula
>
== Series Details ==
Series: drm/i915/display: Extend DP HDR support to hsw+ (rev2)
URL : https://patchwork.freedesktop.org/series/101708/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11398 -> Patchwork_22669
Summary
On Thu, Mar 24, 2022 at 02:42:15PM +0530, Uma Shankar wrote:
> HSW+ platforms are able to send out HDR Metadata SDP DIP
> packet as GMP. Hence, extending the support for HDR on DP
> encoders for the same.
>
> v2: Limited to non eDP ports on hsw/bdw and removed it for
> lspcon as it is done
Reviewed-by: Nirmoy Das
On 3/24/2022 1:04 AM, Daniele Ceraolo Spurio wrote:
On error the "new" allocation is not freed, so add the required kfree.
Fixes: 247f8071d5893 ("drm/i915/guc: Pre-allocate output nodes for extraction")
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Cc: John
On Thu, 24 Mar 2022, Jani Nikula wrote:
> On Tue, 22 Mar 2022, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin
>>
>> ...
>>
>> Signed-off-by: Tvrtko Ursulin
>> Cc: Jani Nikula
>> Cc: Lucas De Marchi
>> ---
>> Typed up how I see it - bash away.
>
> So is intel_vtd_active() so performance
On Tue, 22 Mar 2022, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> ...
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Jani Nikula
> Cc: Lucas De Marchi
> ---
> Typed up how I see it - bash away.
So is intel_vtd_active() so performance critical that it needs to be
inline?
We're passing struct
== Series Details ==
Series: drm/i915/display: Extend DP HDR support to hsw+ (rev2)
URL : https://patchwork.freedesktop.org/series/101708/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
== Series Details ==
Series: drm/i915/display: Extend DP HDR support to hsw+ (rev2)
URL : https://patchwork.freedesktop.org/series/101708/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a2f43ef1952e drm/i915/display: Extend DP HDR support to hsw+
-:36:
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare()
URL : https://patchwork.freedesktop.org/series/101723/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11398 -> Patchwork_22668
Summary
---
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, March 24, 2022 12:49 AM
> To: Shankar, Uma
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Extend DP HDR support to
> hsw+
>
> On Wed, Mar 23, 2022 at 09:04:36PM +0200, Ville
HSW+ platforms are able to send out HDR Metadata SDP DIP
packet as GMP. Hence, extending the support for HDR on DP
encoders for the same.
v2: Limited to non eDP ports on hsw/bdw and removed it for
lspcon as it is done separately (suggested by Ville)
Closes:
On 3/24/2022 8:43 AM, Animesh Manna wrote:
The request to aqquire gem resources is failing for DSB in rare
scenario where it is busy and the register programming will be done
through mmio fallback path.
DSB has extra advantage of faster register programming which may
go away through mmio
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare()
URL : https://patchwork.freedesktop.org/series/101723/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not
== Series Details ==
Series: drm/i915/dsb: modified to drm_info in dsb_prepare()
URL : https://patchwork.freedesktop.org/series/101723/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d7c0e5b3bf10 drm/i915/dsb: modified to drm_info in dsb_prepare()
-:28: WARNING:OOM_MESSAGE:
Hi Dave, Daniel,
A few fixes for the merge window.
Apart from a uninteresting rename of a field in an unused macro, the rest
are display fixes - two for SAGV and one for TDMS rate calculation on
Icelake and above.
Regards,
Tvrtko
drm-intel-next-fixes-2022-03-24:
- Reject unsupported TMDS
> }
>
> +static unsigned int dg2_max_bw(struct drm_i915_private *i915) {
> + struct intel_bw_info *bi = >max_bw[0];
> +
> + return bi->deratedbw[0];
> +}
Would it look better to have this as a macro rather than a function?
Thanks and Regards,
Arun R Murthy
On Wed, Mar 23, 2022 at 06:51:17PM +, Patchwork wrote:
>Patch Details
>
>Series: Revert "drm/i915/dg2: Add relocation exception" (rev2)
>
>URL: https://patchwork.freedesktop.org/series/101669/
>
>State: failure
Hi Dave and Daniel,
here's the weekly PR for drm-misc-fixes.
Best regards
Thomas
drm-misc-fixes-2022-03-24:
* drm/panel/ili9341: Fix optional regulator handling
The following changes since commit 3c3384050d68570f9de0fec9e58824decfefba7a:
drm: Don't make DRM_PANEL_BRIDGE dependent on
== Series Details ==
Series: drm/edid: filter DisplayID v2.0 CTA block in audio detection (rev4)
URL : https://patchwork.freedesktop.org/series/101565/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11398_full -> Patchwork_22667_full
The request to aqquire gem resources is failing for DSB in rare
scenario where it is busy and the register programming will be done
through mmio fallback path.
DSB has extra advantage of faster register programming which may
go away through mmio path. Adding wait for gem resource also may
not be
== Series Details ==
Series: drm/edid: filter DisplayID v2.0 CTA block in audio detection (rev4)
URL : https://patchwork.freedesktop.org/series/101565/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11398 -> Patchwork_22667
== Series Details ==
Series: drm/edid: filter DisplayID v2.0 CTA block in audio detection (rev4)
URL : https://patchwork.freedesktop.org/series/101565/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning:
From: Cooper Chiou
Tag code stored in bit7:5 for CTA block byte[3] is not the same as
CEA extension block definition. Only check CEA block has
basic audio support.
v3: update commit message.
Cc: sta...@vger.kernel.org
Cc: Jani Nikula
Cc: Shawn C Lee
Cc: intel-gfx
Signed-off-by: Cooper Chiou
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