On 2022-10-26 at 13:43:00 +0200, Peter Zijlstra wrote:
> On Wed, Oct 26, 2022 at 01:32:31PM +0300, Ville Syrjälä wrote:
> > Short form looks to be this:
> > <4>[ 355.437846] 1 lock held by rs:main Q:Reg/359:
> > <4>[ 355.438418] #0: 88844693b758 (>__lock){-.-.}-{2:2}, at:
> >
Re-reported.
-Original Message-
From: Dixit, Ashutosh
Sent: Tuesday, October 25, 2022 10:26 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana
Subject: Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: CAGF and RC6 changes
for MTL (rev11)
On Mon, 24 Oct 2022 18:25:06
On Thu, 27 Oct 2022 at 13:26, Zheng Hacker wrote:
>
> Dave Airlie 于2022年10月27日周四 08:01写道：
> >
> > On Fri, 7 Oct 2022 at 11:38, Zheng Wang wrote:
> > >
> > > If intel_gvt_dma_map_guest_page failed, it will call
> > > ppgtt_invalidate_spt, which will finally free the spt.
> > > But the caller
== Series Details ==
Series: series starting with [1/2] drm/i915/display: Do both crawl and squash
when changing cdclk
URL : https://patchwork.freedesktop.org/series/110199/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12304 -> Patchwork_110199v1
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev11)
URL : https://patchwork.freedesktop.org/series/108156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12288 -> Patchwork_108156v11
Summary
---
== Series Details ==
Series: Add DG2 OA support (rev11)
URL : https://patchwork.freedesktop.org/series/107584/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12304 -> Patchwork_107584v11
Summary
---
**SUCCESS**
No
== Series Details ==
Series: Add DG2 OA support (rev11)
URL : https://patchwork.freedesktop.org/series/107584/
State : warning
== Summary ==
Error: dim checkpatch failed
c780bcbe9c6f drm/i915/perf: Fix OA filtering logic for GuC mode
2401ac2c7fc1 drm/i915/perf: Add 32-bit OAG and OAR formats
Dave Airlie 于2022年10月27日周四 08:01写道：
>
> On Fri, 7 Oct 2022 at 11:38, Zheng Wang wrote:
> >
> > If intel_gvt_dma_map_guest_page failed, it will call
> > ppgtt_invalidate_spt, which will finally free the spt.
> > But the caller does not notice that, it will free spt again in error path.
> >
> >
== Series Details ==
Series: freezer, sched: Rewrite core freezer logic fix (rev3)
URL : https://patchwork.freedesktop.org/series/110173/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12298_full -> Patchwork_110173v3_full
== Series Details ==
Series: drm/i915: Audio stuff (rev2)
URL : https://patchwork.freedesktop.org/series/110188/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12302 -> Patchwork_110188v2
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Audio stuff (rev2)
URL : https://patchwork.freedesktop.org/series/110188/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1:
== Series Details ==
Series: drm/i915: Audio stuff (rev2)
URL : https://patchwork.freedesktop.org/series/110188/
State : warning
== Summary ==
Error: dim checkpatch failed
d5e981d3cb31 drm/i915/audio: s/dev_priv/i915/
-:1033: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written
== Series Details ==
Series: drm/i915: prepare for uC loading on MTL (rev5)
URL : https://patchwork.freedesktop.org/series/108925/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12302 -> Patchwork_108925v5
Summary
---
== Series Details ==
Series: drm/i915: prepare for uC loading on MTL (rev5)
URL : https://patchwork.freedesktop.org/series/108925/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: prepare for uC loading on MTL (rev5)
URL : https://patchwork.freedesktop.org/series/108925/
State : warning
== Summary ==
Error: dim checkpatch failed
0ab6f91e91d1 drm/i915/huc: only load HuC on GTs that have VCS engines
-:44: WARNING:AVOID_BUG: Do not
On Fri, 7 Oct 2022 at 11:38, Zheng Wang wrote:
>
> If intel_gvt_dma_map_guest_page failed, it will call
> ppgtt_invalidate_spt, which will finally free the spt.
> But the caller does not notice that, it will free spt again in error path.
>
> Fix this by spliting invalidate and free in
== Series Details ==
Series: drm/i915: More gamma work
URL : https://patchwork.freedesktop.org/series/110168/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12296_full -> Patchwork_110168v1_full
Summary
---
As per bSpec MTL has 38.4 MHz Reference clock.
MTL does support squasher like DG2 but only for lower
frequencies. Change the has_cdclk_squasher()
helper to reflect this.
v2: Revert to using bxt_get_cdclk()
BSpec: 65243
Cc: Clint Taylor
Signed-off-by: Anusha Srivatsa
---
From: Ville Syrjälä
For MTL, changing cdclk from between certain frequencies has
both squash and crawl. Use the current cdclk config and
the new(desired) cdclk config to construtc a mid cdclk config.
Set the cdclk twice:
- Current cdclk -> mid cdclk
- mid cdclk -> desired cdclk
v2: Add check in
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev11)
URL : https://patchwork.freedesktop.org/series/108156/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12288 -> Patchwork_108156v11
Summary
---
AS per the other rev, below regressions are, once again, unrelated to this
series because this series patch modified code that only get executed if GuC
ADS is being initialized whereas the regressions are on platforms that do not
have GuC enabled (which i further verified in the full dmesg).
Hi Maxime,
I've seen that you've incorporated my PAL60 patch. Thanks!
I still yet need to test your v6 changes, but looking at this code with just my
mental static analysis, it seems to me that the vc4_vec_encoder_atomic_check()
should have the tv_mode validation. I should've added it to the
== Series Details ==
Series: drm/i915: stop abusing swiotlb_max_segment (rev7)
URL : https://patchwork.freedesktop.org/series/109946/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12296_full -> Patchwork_109946v7_full
DG2 introduces OA reports with 64 bit report header fields. Perf OA
would need more information about the OA format in order to process such
reports. Store all OA format info in oa_buffer instead of just the size
and format-id.
v2: Drop format_size variable (Ashutosh)
Signed-off-by: Umesh
Some SKUs of same gen12 platform may have different oactxctrl
offsets. For gen12, determine oactxctrl offsets at runtime.
v2: (Lionel)
- Move MI definitions to intel_gpu_commands.h
- Ensure __find_reg_in_lri does read past context image size
v3: (Ashutosh)
- Drop unnecessary use of double
User passes uabi engine class and instance to the perf OA interface. Use
gt corresponding to the engine to pin the buffers to the right ggtt.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 21 +++--
1 file changed, 19
If a drm client is killed, then hw contexts used by the client are reset
immediately. This reset clears the EU flex counter configuration. If an
OA use case is running in parallel, it would start seeing zeroed eu
counter values following the reset even if the drm client is restarted.
Save/restore
Disable Clock gating in EU when gathering the events so that EU events
are not lost.
v2: Fix checkpatch issues
v3: User MCR helpers to write to MC reg
v4: Indent correctly (checkpatch)
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h
OA was disabled for DG2 as support was missing. Enable it back now.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
XEHPSDV and DG2 provide a way to configure bytes per clock vs commands
per clock reporting. Enable bytes per clock setting on enabling OA.
Bspec: 51762
Bspec: 52201
v2:
- Fix commit msg (Ashutosh)
- Fix checkpatch issues
v3:
- s/commands/bytes/ in code comment and commmit msg
Signed-off-by:
OA reports in the OA buffer contain an OA timestamp field that helps
user calculate delta between 2 OA reports. The calculation relies on the
CS timestamp frequency to convert the timestamp value to nanoseconds.
The CS timestamp frequency is a function of the CTC_SHIFT value in
RPM_CONFIG0.
In
Earlier code used exclusive_stream to check for user passed context.
Simplify this by accessing stream->ctx.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Lionel Landwerlin
We have an additional register to select which slices contribute to
OAG/OAG counter increments.
Signed-off-by: Lionel Landwerlin
Signed-off-by: Matt Roper
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
With GuC mode of submission, GuC is in control of defining the context
id field that is part of the OA reports. To filter reports, UMD and KMD
must know what sw context id was chosen by GuC. There is not interface
between KMD and GuC to determine this, so read the upper-dword of
EXECLIST_STATUS to
Make perf part of gt as the OAG buffer is specific to a gt. The refactor
eventually simplifies programming the right OA buffer and the right HW
registers when supporting multiple gts.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
Reviewed-by: Ashutosh Dixit
---
Predication for batch buffer commands changed in XEHPSDV.
MI_BATCH_BUFFER_START predicates based on MI_SET_PREDICATE_RESULT
register. The MI_SET_PREDICATE_RESULT register can only be modified
with MI_SET_PREDICATE command. When configured, the MI_SET_PREDICATE
command sets MI_SET_PREDICATE_RESULT
With multi-gt, user can access multiple OA buffers concurrently. Use
stream->lock instead of gt->perf.lock to serialize file operations.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 31 --
From: Vinay Belgaumkar
On DG2, a w/a resets RCS/CCS before it goes into RC6. This breaks OA
since OA does not expect engine resets during its use. Fix it by
disabling RC6.
v2: (Ashutosh)
- Bring back slpc_unset_param helper
- Update commit msg
- Use with_intel_runtime_pm helper for set/unset
Add new OA formats for DG2.
MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18893
v2:
- Update commit title (Ashutosh)
- Coding style fixes (Lionel)
- 64 bit OA formats need UMD changes in GPUvis, drop for now and send in a
separate series with UMD changes
v3:
- Update commit
Add OA format support for DG2 and various fixes for DG2.
This series has 2 uapi changes listed below:
1) drm/i915/perf: Add OAG and OAR formats for DG2
DG2 has new OA formats defined that can be selected by the
user. The UMD changes that are consumed by GPUvis are:
Hi Maxime,
First of all, nice idea with the helper function that can be reused by different
drivers. This is neat!
But looking at this function, it feels a bit overcomplicated. You're creating
the two modes, then checking which one is the default, then set the preferred
one and possibly reorder
== Series Details ==
Series: drm/i915/sdvo: Fix LVDS fixed mode setup and clean up output setup
URL : https://patchwork.freedesktop.org/series/110167/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12296_full -> Patchwork_110167v1_full
On Tue, 25 Oct 2022 15:50:45 -0300
Jason Gunthorpe wrote:
> If the VFIO container is compiled out, give a kconfig option for iommufd
> to provide the miscdev node with the same name and permissions as vfio
> uses.
>
> The compatibility node supports the same ioctls as VFIO and automatically
>
Hi Maxime,
+static struct drm_display_mode *drm_named_mode(struct drm_device *dev,
+ struct drm_cmdline_mode *cmd)
+{
+ struct drm_display_mode *mode;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(drm_named_modes); i++) {
+
On Tue, 25 Oct 2022 15:17:10 -0300
Jason Gunthorpe wrote:
> This legacy module knob has become uAPI, when set on the vfio_iommu_type1
> it disables some security protections in the iommu drivers. Move the
> storage for this knob to vfio_main.c so that iommufd can access it too.
I don't really
The issues reported below are unrelated to the patch because:
1. SKL and ICL do not even support PXP and none of the code path of this series
will get executed.
2. RKL supports PXP but the code paths only get executed when PXP is enabled by
the component binding and activated (via IGT PXP)
On Wed, Oct 26, 2022 at 11:59:28AM +0200, Hans de Goede wrote:
> Ok, so this is a local customization to what is already a custom BIOS
> for a custom motherboard. There is a lot of custom in that sentence and
> TBH at some point things might become too custom for them to be expected
> to work
== Series Details ==
Series: drm/i915/userptr: restore probe_range behaviour (rev2)
URL : https://patchwork.freedesktop.org/series/110083/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12296_full -> Patchwork_110083v2_full
== Series Details ==
Series: freezer, sched: Rewrite core freezer logic fix (rev3)
URL : https://patchwork.freedesktop.org/series/110173/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12298 -> Patchwork_110173v3
Summary
== Series Details ==
Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)
URL : https://patchwork.freedesktop.org/series/109963/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full
On 10/26/2022 12:13 PM, Belgaumkar, Vinay wrote:
Project List - Patchwork
*From:* Patchwork
*Sent:* Tuesday, October 25, 2022 7:39 PM
*To:* Belgaumkar, Vinay
*Cc:* intel-gfx@lists.freedesktop.org
*Subject:* ✗ Fi.CI.IGT: failure for drm/i915/slpc: Use platform limits
for min/max frequency
== Series Details ==
Series: freezer, sched: Rewrite core freezer logic fix (rev3)
URL : https://patchwork.freedesktop.org/series/110173/
State : warning
== Summary ==
Error: dim checkpatch failed
c9af43324598 freezer, sched: Rewrite core freezer logic fix
-:12: WARNING:COMMIT_LOG_LONG_LINE:
Filed a new issue and re-reported.
https://gitlab.freedesktop.org/drm/intel/-/issues/7323
igt@i915_selftest@mock@requests - incomplete - GEM_BUG_ON(ce->timeline->seqno
!= ({ do { __attribute__((__noreturn__)) extern void __compiletime_assert,
kernel BUG at
From: Patchwork
Sent: Tuesday, October 25, 2022 7:39 PM
To: Belgaumkar, Vinay
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for drm/i915/slpc: Use platform limits for
min/max frequency (rev5)
Patch Details
Series:
drm/i915/slpc: Use platform limits for min/max frequency
== Series Details ==
Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)
URL : https://patchwork.freedesktop.org/series/109963/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full
On Wed, Oct 26, 2022 at 02:33:50PM +, Patchwork wrote:
Patch Details
Series: Add DG2 OA support (rev10)
URL: [1]https://patchwork.freedesktop.org/series/107584/
State: failure
Details:
[2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107584v10/index.html
CI Bug Log -
I verified that 2 of the 3 the errors reported below are on platforms that
don't support GuC and the dmesgs confirm guc was disabled.
The remaining ICL one, we know ICL doesnt support GuC .. also, additionally,
the error was on a display IGT where CRCs were failing.
That said these errors I
On Wed, Oct 26, 2022 at 06:15:09PM +0100, Matthew Auld wrote:
On 25/10/2022 07:58, Niranjana Vishwanathapura wrote:
Add support for handling out fence for vm_bind call.
v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
of vm_bind call.
v3: Remove vm_unbind out fence uapi which is not
== Series Details ==
Series: Revert "drm/i915/uapi: expose GTT alignment"
URL : https://patchwork.freedesktop.org/series/110041/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12284_full -> Patchwork_110041v1_full
Summary
== Series Details ==
Series: Fix Guc-Err-Capture sizing warning
URL : https://patchwork.freedesktop.org/series/110155/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12295_full -> Patchwork_110155v1_full
Summary
---
On 10/25/2022 23:05, Alan Previn wrote:
During GuC error capture initialization, we estimate the amount of size
we need for the error-capture-region of the shared GuC-log-buffer.
This calculation was incorrect so fix that. With the fixed calculation
we can reduce the allocation of error-capture
== Series Details ==
Series: drm/i915: Audio stuff
URL : https://patchwork.freedesktop.org/series/110188/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12297 -> Patchwork_110188v1
Summary
---
**FAILURE**
Serious
== Series Details ==
Series: Delay disabling GuC scheduling of an idle context (rev2)
URL : https://patchwork.freedesktop.org/series/109466/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12295_full -> Patchwork_109466v2_full
On 26/10/2022 18:53, Vudum, Lakshminarayana wrote:
@Auld, Matthew Can you check if this is related to your patch? Looks new to me.
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-skl9/igt@i915_selftest@m...@requests.html#dmesg-warnings16
For sure unrelated to this series.
On Wed, Oct 26, 2022 at 06:04:08AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/xelp: Add Wa_1806527549 (rev2)
> URL : https://patchwork.freedesktop.org/series/109885/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12261_full ->
From: Patchwork
Sent: Wednesday, October 26, 2022 10:07 AM
To: Srivatsa, Anusha
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for series starting with [CI,1/4]
drm/i915/display: Change terminology for cdclk actions
Patch Details
Series:
series starting with [CI,1/4]
@Auld, Matthew Can you check if this is related to your patch? Looks new to me.
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110041v1/shard-skl9/igt@i915_selftest@m...@requests.html#dmesg-warnings16
Lakshmi.
-Original Message-
From: Auld, Matthew
Sent: Wednesday, October 26, 2022
== Series Details ==
Series: drm/i915: Audio stuff
URL : https://patchwork.freedesktop.org/series/110188/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning:
== Series Details ==
Series: drm/i915: Audio stuff
URL : https://patchwork.freedesktop.org/series/110188/
State : warning
== Summary ==
Error: dim checkpatch failed
89816a330d11 drm/i915/audio: s/dev_priv/i915/
-:1033: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written
== Series Details ==
Series: drm/i915/selftests: add over-fetch padding to store_dw batchbuffer
URL : https://patchwork.freedesktop.org/series/110186/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12297 -> Patchwork_110186v1
> -Original Message-
> From: Jani Nikula
> Sent: Wednesday, October 26, 2022 12:52 AM
> To: Srivatsa, Anusha ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [CI 1/4] drm/i915/display: Change terminology for
> cdclk actions
>
> On Tue, 25 Oct 2022, Anusha Srivatsa
On 25/10/2022 07:59, Niranjana Vishwanathapura wrote:
Update i915 documentation to include VM_BIND changes
and render all VM_BIND related documentation.
Signed-off-by: Niranjana Vishwanathapura
Thanks for adding this,
Reviewed-by: Matthew Auld
On 25/10/2022 07:58, Niranjana Vishwanathapura wrote:
Add support for handling out fence for vm_bind call.
v2: Reset vma->vm_bind_fence.syncobj to NULL at the end
of vm_bind call.
v3: Remove vm_unbind out fence uapi which is not supported yet.
v4: Return error if I915_TIMELINE_FENCE_WAIT
On 25/10/2022 07:59, Niranjana Vishwanathapura wrote:
For persistent (vm_bind) vmas of userptr BOs, handle the user
page pinning by using the i915_gem_object_userptr_submit_init()
/done() functions
v2: Do not double add vma to vm->userptr_invalidated_list
Signed-off-by: Niranjana
== Series Details ==
Series: drm/i915/selftests: add over-fetch padding to store_dw batchbuffer
URL : https://patchwork.freedesktop.org/series/110186/
State : warning
== Summary ==
Error: dim checkpatch failed
9a15ae121ad3 drm/i915/selftests: add over-fetch padding to store_dw batchbuffer
== Series Details ==
Series: drm/i915/tgl+: Fix race conditions during DKL PHY accesses (rev5)
URL : https://patchwork.freedesktop.org/series/109963/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12293_full -> Patchwork_109963v5_full
== Series Details ==
Series: drm/i915: Remove unwanted ghost obj check (rev2)
URL : https://patchwork.freedesktop.org/series/110065/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12297 -> Patchwork_110065v2
Summary
---
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/display: Change terminology for
cdclk actions
URL : https://patchwork.freedesktop.org/series/110145/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12295_full -> Patchwork_110145v1_full
From: Ville Syrjälä
On the "ilk" platforms AUD_CNTL_ST2 is a singleton. Protect
it with the audio mutex in case we ever want to do parallel
RMW access to it.
Currently that should not happen since we only do audio
enable/disable from full modesets, and those are fully
serialized. But we
From: Ville Syrjälä
On the older platforms the audio presence detect bit is in
the port register, so it gets written outside audio codec hooks
and is this separate from the ELD valid toggling. Split the
operations into two steps on hsw+ to be more consistent with
both the other platforms and the
From: Ville Syrjälä
Currently we only write as many dwords into the hardware
ELD buffers as drm_eld_size() tells us. That could mean the
remainder of the hardware buffer is left with whatever
stale garbage it had before, which doesn't seem entirely
great. Let's zero out the remainder of the
From: Ville Syrjälä
We currently read the ELD buffer size from hardware on g4x,
but on ilk+ we just hardcode it to 84 bytes. Let's unify
this and just do the hardware readout on all platforms,
in case the size changes in the future or something.
TODO: should perhaps do the readout during driver
From: Ville Syrjälä
The audio code does a lot of RMW accesses. Utilize
intel_de_rmw() to make that a bit less tedious.
There are still some hand rolled RMW left, but those have
a lot of code in between the read and write to calculate
the new value, so would need some refactoring first.
v2: Add
From: Ville Syrjälä
Make the eld pointer u32* so we don't have to do super
ugly casting in the code itself.
Cc: Chaitanya Kumar Borah
Cc: Kai Vehmanen
Cc: Takashi Iwai
Reviewed-by: Jani Nikula
Reviewed-by: Kai Vehmanen
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
The spec tells us to do a bunch of vblank waits in the audio
enable/disable sequences. Make it so.
The FIXMEs are nonsense since we do the audio disable very
early and enable very late, so vblank interrupts are in fact
enabled when we do this.
TODO not sure we actually want
From: Ville Syrjälä
Pull the SDVO audio state computation into a helper.
This is almost identical to intel_hdmi_has_audio(),
except the sink capabilities are stored under intel_sdvo
rather than intel_hdmi. Might be nice to get rid of
this duplication eventually...
Cc: Chaitanya Kumar Borah
From: Ville Syrjälä
Remove some leftovers I missed in commit
2dd43144e824 ("drm/i915: Streamline the artihmetic")
Cc: Chaitanya Kumar Borah
Cc: Kai Vehmanen
Cc: Takashi Iwai
Reviewed-by: Jani Nikula
Reviewed-by: Kai Vehmanen
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
The "ilk" audio codec codepaths have some duplicated code
to figure out the correct registers to use on each platform.
Extrat that into a single place.
Cc: Chaitanya Kumar Borah
Cc: Kai Vehmanen
Cc: Takashi Iwai
Reviewed-by: Jani Nikula
Reviewed-by: Kai Vehmanen
From: Ville Syrjälä
Switch the audio registers to REG_BIT() & co.
Cc: Chaitanya Kumar Borah
Cc: Kai Vehmanen
Cc: Takashi Iwai
Reviewed-by: Jani Nikula
Reviewed-by: Kai Vehmanen
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_audio.c| 15 ++--
From: Ville Syrjälä
No idea why we do this ELD comparions on g4x before loading
the new ELD. Seems entirely pointless so just get rid of it.
Cc: Chaitanya Kumar Borah
Cc: Kai Vehmanen
Cc: Takashi Iwai
Reviewed-by: Jani Nikula
Reviewed-by: Kai Vehmanen
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
Rename the 'dev_priv' variables to 'i915' in the audio code
to match modern style conventions.
v2: Drop some needless braces in intel_audio_hooks_init()
Cc: Chaitanya Kumar Borah
Cc: Kai Vehmanen
Cc: Takashi Iwai
Reviewed-by: Jani Nikula
Reviewed-by: Kai Vehmanen
From: Ville Syrjälä
Rename a few g4x bits to match the ibx+ bits.
Cc: Chaitanya Kumar Borah
Cc: Kai Vehmanen
Cc: Takashi Iwai
Reviewed-by: Jani Nikula
Reviewed-by: Kai Vehmanen
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_audio.c | 10 +-
From: Ville Syrjälä
We don't use the audio code on crestline (CL) since it doesn't
support native HDMI output, and SDVO has it's own way of doing
audio.
And Bearlake-C (BLC) doesn't even exist in the real world, so
no point it trying to deal with it.
Cc: Chaitanya Kumar Borah
Cc: Kai Vehmanen
From: Ville Syrjälä
All the less controversional cleanups/fixes/etc. from the
earlier ELD precompute+state check series. So no actual
ELD precompute+state check here yet.
Ville Syrjälä (15):
drm/i915/audio: s/dev_priv/i915/
drm/i915/audio: Nuke leftover ROUNDING_FACTOR
drm/i915/audio:
== Series Details ==
Series: drm: Analog TV Improvements (rev6)
URL : https://patchwork.freedesktop.org/series/107892/
State : failure
== Summary ==
Error: patch
https://patchwork.freedesktop.org/api/1.0/series/107892/revisions/6/mbox/ not
applied
Applying: drm/tests: Add Kunit Helpers
== Series Details ==
Series: Revert "drm/i915/uapi: expose GTT alignment"
URL : https://patchwork.freedesktop.org/series/110041/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12284_full -> Patchwork_110041v1_full
Summary
== Series Details ==
Series: freezer, sched: Rewrite core freezer logic fix (rev2)
URL : https://patchwork.freedesktop.org/series/110173/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12297 -> Patchwork_110173v2
Summary
Due to batch buffer over-fetch mechanism up to 4KB beyond the last
command in the buffer can be read by engine executing the buffer.
On the other side if memory is accessed during TLB invalidation proper
TLB invalidation is not guaranteed. Both conditions can occur when two
buffers are bound to
From: Mateusz Kwiatkowski
Add support for the following composite output modes (all of them are
somewhat more obscure than the previously defined ones):
- NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to
4.43361875 MHz (the PAL subcarrier frequency). Never used for
Now that the core can deal fine with analog TV modes, let's convert the vc4
VEC driver to leverage those new features.
We've added some backward compatibility to support the old TV mode property
and translate it into the new TV norm property. We're also making use of
the new analog TV
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