From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent,
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
The first three patches in this series are taken from
https://patchwork.freedesktop.org/series/116868/
These patches are included here because the last patch
has dependency on the pat_index refactor.
This series is focusing on uAPI changes,
1. end support for set caching ioctl
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by
From: Fei Yang
PTE encode is platform dependent. After replacing cache_level with
pat_index, the newly introduced mtl_pte_encode is actually generic
for all gen12 platforms, thus rename it to gen12_pte_encode and
apply it to all gen12 platforms.
Cc: Chris Wilson
Cc: Matt Roper
Signed-off-by:
From: Fei Yang
Currently the KMD is using enum i915_cache_level to set caching policy for
buffer objects. This is flaky because the PAT index which really controls
the caching behavior in PTE has far more levels than what's defined in the
enum. In addition, the PAT index is platform dependent,
From: Fei Yang
This patch is a preparation for replacing enum i915_cache_level with PAT
index. Caching policy for buffer objects is set through the PAT index in
PTE, the old i915_cache_level is not sufficient to represent all caching
modes supported by the hardware.
Preparing the transition by
From: Fei Yang
PTE encode is platform dependent. After replacing cache_level with
pat_index, the newly introduced mtl_pte_encode is actually generic
for all gen12 platforms, thus rename it to gen12_pte_encode and
apply it to all gen12 platforms.
Cc: Chris Wilson
Cc: Matt Roper
Signed-off-by:
From: Fei Yang
This patch set was posted at
https://patchwork.freedesktop.org/series/116868/
Change title since the PTE patch was merged separately.
These patches are extracted from series
https://patchwork.freedesktop.org/series/115980/
This series refactor the cache policy programming so
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev9)
URL : https://patchwork.freedesktop.org/series/112647/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13071_full -> Patchwork_112647v9_full
Summary
Hi,
> -Original Message-
> From: Intel-gfx On Behalf Of Ye,
> Tony
> Sent: perjantai 28. huhtikuuta 2023 6.11
> To: Ceraolo Spurio, Daniele ; intel-
> g...@lists.freedesktop.org
> Cc: Teres Alexis, Alan Previn ; dri-
> de...@lists.freedesktop.org; Zhang, Carl
> Subject: Re:
== Series Details ==
Series: fdinfo: Enable some support for GuC based client busyness (rev2)
URL : https://patchwork.freedesktop.org/series/116120/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13071_full -> Patchwork_116120v2_full
== Series Details ==
Series: series starting with [v6,1/2] drm/i915/guc/slpc: Provide sysfs for
efficient freq (rev3)
URL : https://patchwork.freedesktop.org/series/116957/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13071_full -> Patchwork_116957v3_full
== Series Details ==
Series: drm/i915: HuC loading and authentication for MTL
URL : https://patchwork.freedesktop.org/series/117080/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13071 -> Patchwork_117080v1
Summary
---
Acked-by: Tony Ye
Thanks,
Tony
On 4/27/2023 7:34 PM, Daniele Ceraolo Spurio wrote:
The HuC loading and authentication flow is once again changing and a new
"clear-media only" authentication step is introduced. The flow is as
follows:
1) The HuC is loaded via DMA - same as all non-GSC HuC
== Series Details ==
Series: drm/i915: HuC loading and authentication for MTL
URL : https://patchwork.freedesktop.org/series/117080/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: HuC loading and authentication for MTL
URL : https://patchwork.freedesktop.org/series/117080/
State : warning
== Summary ==
Error: dim checkpatch failed
0ce1e3ea75ee DO NOT REVIEW: drm/i915: Add support for MTL GSC SW Proxy
Traceback (most recent call
On MTL, for obvious reasons, HuC is only available on the media tile.
We already disable SW support for HuC on the root gt due to the
absence of VCS engines, but we also need to update the getparam to point
to the HuC struct in the media GT.
Signed-off-by: Daniele Ceraolo Spurio
Cc: John
The full authentication via the GSC requires an heci packet submission
to the GSC FW via the GSC CS. The GSC has new PXP command for this
(literally called NEW_HUC_AUTH).
The intel_huc_auth fuction is also updated to handle both authentication
types.
Signed-off-by: Daniele Ceraolo Spurio
Cc:
The HuC loading and authentication flow is once again changing and a new
"clear-media only" authentication step is introduced. The flow is as
follows:
1) The HuC is loaded via DMA - same as all non-GSC HuC binaries.
2) The HuC is authenticated by the GuC - this is the same step as
performed for
Follow the same logic as DG2, so just a meu binary with no version number.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
Before we add the second step of the MTL HuC auth (via GSC), we need to
have the ability to differentiate between them. To do so, the huc
authentication check is duplicated for GuC and GSC auth, with meu
binaries being considered fully authenticated only after the GSC auth
step.
To report the
In the previous patch we extracted the offset of the legacy-style HuC
binary located within the GSC-enabled blob, so now we can use that to
load the HuC via DMA if the fuse is set that way.
Note that we now need to differentiate between "GSC-enabled binary" and
"loaded by GSC", so the former case
The new binaries that support the 2-step authentication have contain the
legacy-style binary, which we can use for loading the HuC via DMA. To
find out where this is located in the image, we need to parse the meu
manifest of the GSC binary. The manifest consist of a partition header
followed by
Now that each FW has its own reserved area, we can keep them always
pinned and skip the pin/unpin dance on reset. This will make things
easier for the 2-step HuC authentication, which requires the FW to be
pinned in GGTT after the xfer is completed.
Given that we use dummy vmas for the pinning, we
This is a squash of the GSC proxy series, which is being reviewed
separately [1]. It's being included here because some of the patches in
this series depend on it. This is not a functional dependencies, the
patches just touch the same code and the proxy patches are planned to be
merged first, so
== Series Details ==
Series: drm/i915: Hugepage manager and test for MTL (rev3)
URL : https://patchwork.freedesktop.org/series/116995/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13071_full -> Patchwork_116995v3_full
The following changes since commit fab149657d8d029c06179dd006b59b2f3594f916:
Group all Conexant V4L devices together (2023-04-27 09:15:55 -0400)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware mtl_huc_8.4.5
for you to fetch changes up to
== Series Details ==
Series: mtl: add support for pmdemand (rev4)
URL : https://patchwork.freedesktop.org/series/116949/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13071_full -> Patchwork_116949v4_full
Summary
---
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev9)
URL : https://patchwork.freedesktop.org/series/112647/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13071 -> Patchwork_112647v9
Summary
---
On Thu, 2023-04-27 at 16:48 -0700, Teres Alexis, Alan Previn wrote:
> Add helper functions into a new file for heci-packet-submission.
> The helpers will handle generating the MTL GSC-CS Memory-Header
> and submission of the Heci-Cmd-Packet instructions to the engine.
>
>
alan: I accidentally
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev9)
URL : https://patchwork.freedesktop.org/series/112647/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/pxp: Add MTL PXP Support (rev9)
URL : https://patchwork.freedesktop.org/series/112647/
State : warning
== Summary ==
Error: dim checkpatch failed
e93c6f73e145 drm/i915/pxp: Add GSC-CS back-end resource init and cleanup
Traceback (most recent call last):
== Series Details ==
Series: fdinfo: Enable some support for GuC based client busyness (rev2)
URL : https://patchwork.freedesktop.org/series/116120/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13071 -> Patchwork_116120v2
Add MTL's function for ARB session creation using PXP firmware
version 4.3 ABI structure format.
While relooking at the ARB session creation flow in intel_pxp_start,
let's address missing UAPI documentation. Without actually changing
backward compatible behavior, update i915's drm-uapi comments
Enable PXP with MTL-GSC-CS: add the has_pxp into device info
and increase the debugfs teardown timeouts to align with
new GSC-CS + firmware specs.
Now that we have 3 places that are selecting pxp timeouts
based on tee vs gsccs back-end, let's add a helper.
Signed-off-by: Alan Previn
On legacy platforms, KCR HW enabling is done at the time the mei
component interface is bound. It's also disabled during unbind.
However, for MTL onwards, we don't depend on a tee component
to start sending GSC-CS firmware messages.
Thus, immediately enable (or disable) KCR HW on PXP's init,
fini
Add MTL hw-plumbing enabling for KCR operation under PXP
which includes:
1. Updating 'pick-gt' to get the media tile for
KCR interrupt handling
2. Adding MTL's KCR registers for PXP operation
(init, status-checking, etc.).
While doing #2, lets create a separate registers header file for
For MTL, the PXP back-end transport uses the GSC engine to submit
HECI packets through the HW to the GSC firmware for PXP arb
session management. This submission uses a non-priveleged
batch buffer, a buffer for the command packet and of course
a context targeting the GSC-CS.
Thus for MTL, we need
Add helper functions into a new file for heci-packet-submission.
The helpers will handle generating the MTL GSC-CS Memory-Header
and submission of the Heci-Cmd-Packet instructions to the engine.
NOTE1: These common functions for heci-packet-submission will be used
by different i915 callers:
Because of the additional firmware, component-driver and
initialization depedencies required on MTL platform before a
PXP context can be created, UMD calling for PXP creation as a
way to get-caps can take a long time. An actual real world
customer stack has seen this happen in the 4-to-8 second
This series enables PXP on MTL. On ADL/TGL platforms, we rely on
the mei driver via the i915-mei PXP component interface to establish
a connection to the security firmware via the HECI device interface.
That interface is used to create and teardown the PXP ARB session.
PXP ARB session is created
Add GSC engine based method for sending PXP firmware packets
to the GSC firmware for MTL (and future) products.
Use the newly added helpers to populate the GSC-CS memory
header and send the message packet to the FW by dispatching
the GSC_HECI_CMD_PKT instruction on the GSC engine.
We use
== Series Details ==
Series: fdinfo: Enable some support for GuC based client busyness (rev2)
URL : https://patchwork.freedesktop.org/series/116120/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: series starting with [v6,1/2] drm/i915/guc/slpc: Provide sysfs for
efficient freq (rev3)
URL : https://patchwork.freedesktop.org/series/116957/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13071 -> Patchwork_116957v3
== Series Details ==
Series: series starting with [v6,1/2] drm/i915/guc/slpc: Provide sysfs for
efficient freq (rev3)
URL : https://patchwork.freedesktop.org/series/116957/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: drm/i915/dsi: Use unconditional msleep() instead of intel_dsi_msleep()
(rev2)
URL : https://patchwork.freedesktop.org/series/116947/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13071_full -> Patchwork_116947v2_full
Export context runtime into the fdinfo framework to enable per client
busyness for GuC back-end.
v2: Fix zeroed busyness values
v3: Include review comments from Ashutosh
Signed-off-by: Umesh Nerlige Ramappa
Umesh Nerlige Ramappa (2):
i915/pmu: Add support for total context runtime for GuC
GPU accumulates the context runtime in a 32 bit counter - CTX_TIMESTAMP
in the context image. This value is saved/restored on context switches.
KMD accumulates these values into a 64 bit counter taking care of any
overflows as needed. This count provides the basis for client specific
busyness in
Enable fdinfo for GuC based platforms with the exception that long
running contexts will not provide reliable busyness data unless they
switch out at some reasonable point in time.
Link: https://gitlab.freedesktop.org/drm/intel/issues/8303
Signed-off-by: Umesh Nerlige Ramappa
---
On Wed, 26 Apr 2023 07:54:19 -0700
Yi Liu wrote:
> This is the way user to invoke hot-reset for the devices opened by cdev
> interface. User should check the flag VFIO_PCI_HOT_RESET_FLAG_RESETTABLE
> in the output of VFIO_DEVICE_GET_PCI_HOT_RESET_INFO ioctl before doing
> hot-reset for cdev
Quoting Vinod Govindapillai (2023-04-27 12:00:15)
>From: Mika Kahola
>
>Display14 introduces a new way to instruct the PUnit with
>power and bandwidth requirements of DE. Add the functionality
>to program the registers and handle waits using interrupts.
>The current wait time for timeouts is
On Thu, 27 Apr 2023 14:04:05 -0600
Alex Williamson wrote:
> On Wed, 26 Apr 2023 07:54:18 -0700
> Yi Liu wrote:
>
> > This makes VFIO_DEVICE_GET_PCI_HOT_RESET_INFO ioctl to use the bound
> > iommufd of the cdev device to check the ownership of the other affected
> > devices and set a flag to
On Wed, 26 Apr 2023 07:54:18 -0700
Yi Liu wrote:
> This makes VFIO_DEVICE_GET_PCI_HOT_RESET_INFO ioctl to use the bound
> iommufd of the cdev device to check the ownership of the other affected
> devices and set a flag to tell user if the cdev device is resettable
> with a zero-length fd array.
== Series Details ==
Series: drm/i915: Hugepage manager and test for MTL (rev3)
URL : https://patchwork.freedesktop.org/series/116995/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13071 -> Patchwork_116995v3
Summary
On Wed, Apr 26, 2023 at 05:51:24PM -0700, Dixit, Ashutosh wrote:
On Wed, 26 Apr 2023 17:11:27 -0700, Umesh Nerlige Ramappa wrote:
Hi Umesh,
On Mon, Apr 24, 2023 at 10:41:41AM -0700, Dixit, Ashutosh wrote:
> On Tue, 04 Apr 2023 17:14:32 -0700, Umesh Nerlige Ramappa wrote:
>
>> GPU
On Wed, 26 Apr 2023 07:54:15 -0700
Yi Liu wrote:
> Use it to differentiate whether to report group_id or dev_id in revised
> VFIO_DEVICE_GET_PCI_HOT_RESET_INFO ioctl. Though it is not set at this
> moment introducing it now allows us to get hot reset ready for cdev.
>
> Signed-off-by: Yi Liu
>
On Thu, 27 Apr 2023 07:05:37 +
"Liu, Yi L" wrote:
> > From: Tian, Kevin
> > Sent: Thursday, April 27, 2023 2:36 PM
> >
> > > From: Liu, Yi L
> > > Sent: Wednesday, April 26, 2023 10:54 PM
> > >
> > > -static inline bool vfio_device_is_noiommu(struct vfio_device *vdev)
> > > +static
On Thu, 27 Apr 2023 06:59:17 +
"Liu, Yi L" wrote:
> > From: Tian, Kevin
> > Sent: Thursday, April 27, 2023 2:39 PM
> >
> > > From: Liu, Yi L
> > > Sent: Wednesday, April 26, 2023 10:54 PM
> > > @@ -121,7 +128,8 @@ static void vfio_emulated_unmap(void *data,
> > > unsigned long iova,
> >
On 27/04/2023 21:19, Teres Alexis, Alan Previn wrote:
(fixed email addresses again - why is my Evolution client deteorating??)
On Thu, 2023-04-27 at 17:18 +, Teres Alexis, Alan Previn wrote:
On Wed, 2023-04-26 at 15:35 -0700, Justen, Jordan L wrote:
On 2023-04-26 11:17:16, Teres Alexis,
== Series Details ==
Series: mtl: add support for pmdemand (rev4)
URL : https://patchwork.freedesktop.org/series/116949/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13071 -> Patchwork_116949v4
Summary
---
(fixed email addresses again - why is my Evolution client deteorating??)
On Thu, 2023-04-27 at 17:18 +, Teres Alexis, Alan Previn wrote:
> On Wed, 2023-04-26 at 15:35 -0700, Justen, Jordan L wrote:
> > On 2023-04-26 11:17:16, Teres Alexis, Alan Previn wrote:
> alan:snip
> > Can you tell that
== Series Details ==
Series: mtl: add support for pmdemand (rev4)
URL : https://patchwork.freedesktop.org/series/116949/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: mtl: add support for pmdemand (rev4)
URL : https://patchwork.freedesktop.org/series/116949/
State : warning
== Summary ==
Error: dim checkpatch failed
874300201d54 drm/i915: fix the derating percentage for MTL
0351498e12a8 drm/i915: update the QGV point frequency
== Series Details ==
Series: Introduce sink_format and other fixes
URL : https://patchwork.freedesktop.org/series/117056/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13071 -> Patchwork_117056v1
Summary
---
== Series Details ==
Series: Introduce sink_format and other fixes
URL : https://patchwork.freedesktop.org/series/117056/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Wed, 2023-04-26 at 15:35 -0700, Justen, Jordan L wrote:
> On 2023-04-26 11:17:16, Teres Alexis, Alan Previn wrote:
alan:snip
>
> > - Jordan still wants the extension query
> Yes, I do, but so far it doesn't appear that any kernel devs think
> it's a reasonable request.
>
> As I read through
On Fri, 2023-04-14 at 17:27 -0700, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> GuC based register dumps in error capture logs were basically broken
> for virtual engines. This can be seen in igt@gem_exec_balancer@hang:
> [IGT] gem_exec_balancer: starting subtest hang
> [drm]
== Series Details ==
Series: drm/i915/dsi: Use unconditional msleep() instead of intel_dsi_msleep()
(rev2)
URL : https://patchwork.freedesktop.org/series/116947/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13071 -> Patchwork_116947v2
> -Original Message-
> From: Kahola, Mika
> Sent: Wednesday, April 26, 2023 4:43 AM
> To: Sripada, Radhakrishna
> Cc: intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [PATCH 02/13] drm/i915/mtl: C20 HW readout
>
> > -Original Message-
> > From: Sripada, Radhakrishna
On Thu, 27 Apr 2023 09:24:58 -0700, Kamil Konieczny wrote:
>
> Hi Ashutosh,
>
> On 2023-04-26 at 13:40:28 -0700, Dixit, Ashutosh wrote:
> > On Tue, 25 Apr 2023 09:24:04 -0700, Vinay Belgaumkar wrote:
> > >
> > > diff --git a/tests/i915/i915_pm_freq_api.c b/tests/i915/i915_pm_freq_api.c
> > > new
Hi Ashutosh,
On 2023-04-26 at 13:40:28 -0700, Dixit, Ashutosh wrote:
> On Tue, 25 Apr 2023 09:24:04 -0700, Vinay Belgaumkar wrote:
> >
> > diff --git a/tests/i915/i915_pm_freq_api.c b/tests/i915/i915_pm_freq_api.c
> > new file mode 100644
> > index ..17adacbc
> > --- /dev/null
> > +++
On Thu, Apr 20, 2023 at 03:40:49PM +0300, Mika Kahola wrote:
> From: Anusha Srivatsa
>
> Unlike previous platforms that used PORT_TX_DFLEXDPSP
> for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
> from which the max_lanes has to be calculated.
>
> Bspec: 50235, 65380
>
Reviewed-by: Matt
== Series Details ==
Series: Expose RPS thresholds in sysfs
URL : https://patchwork.freedesktop.org/series/117054/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
CC [M] drivers/gpu/drm/i915/gt/intel_rps.o
In
On Thu, Apr 20, 2023 at 03:40:48PM +0300, Mika Kahola wrote:
> From: Imre Deak
>
> The HPD live status for MTL has to be read from different set of
> registers. MTL deserves a new function for this purpose
> and cannot reuse the existing HPD live status detection
>
Reviewed-by: Matt Atwood
>
On Thu, Apr 20, 2023 at 03:40:47PM +0300, Mika Kahola wrote:
> Add register writes to enable powering up Type-C subsystem i.e. TCSS.
> For MeteorLake we need to request TCSS to power up and check the TCSS
> power state after 500 us.
>
> In addition, for PICA we need to set/clear the Type-C PHY
> On 26/04/2023 16:41, Yang, Fei wrote:
>>> On 26/04/2023 07:24, fei.y...@intel.com wrote:
From: Fei Yang
The first three patches in this series are taken from
https://patchwork.freedesktop.org/series/116868/
These patches are included here because the last patch
has
On 26/04/2023 19:29, Doug Anderson wrote:
Hi,
On Wed, Apr 19, 2023 at 8:43 AM Mark Yacoub wrote:
Hi all,
This is v10 of the HDCP patches. The patches are authored by Sean Paul.
I rebased and addressed the review comments in v6-v10.
Main change in v10 is handling the kernel test bot
On 4/20/23 05:40, Mika Kahola wrote:
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
On Thu, Apr 27, 2023 at 06:00:10PM +0300, Vinod Govindapillai wrote:
> >From MTL onwwards, pcode locks the QGV point based on peak BW of
> the intended QGV point passed by the driver. So the peak BW
> calculation must match the value expected by the pcode. Update
> the calculations as per the
From: Mika Kahola
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case
While configuring pmdemand parameters, there could be
intel_get_crtc_new_encoder call where encoders could be 0. To avoid
invoking drm_warn in such cases, use a parameter to indicate drm_warn
should be suppressed.
v2: checkpatch warning fixes
Signed-off-by: Vinod Govindapillai
---
>From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 87 -
MTL uses the peak BW of a QGV point to lock the required QGV
point instead of the QGV index. Instead of passing the deratedbw
of the selected bw_info, return the index to the selected
bw_info so that either deratedbw or peakbw can be used based on
the platform.
v2: use idx to store index returned
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file changed, 130 insertions(+), 105
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 7 +--
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
>From MTL onwwards, pcode locks the QGV point based on peak BW of
the intended QGV point passed by the driver. So the peak BW
calculation must match the value expected by the pcode. Update
the calculations as per the Bspec.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
pmdemand support patches for MTL
SAGV configuration support for MTL
v2: added one missing patch in the previous version
v3: chekcpatch warning fixes
update index handling for the icl/tgl QGV point handling
program pmdemand code simplified
v4: update to debufs and pipe values pmdemand
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 26/04/2023 16:41, Yang, Fei wrote:
> On 26/04/2023 07:24, fei.y...@intel.com wrote:
>> From: Fei Yang
>>
>> The first three patches in this series are taken from
>> https://patchwork.freedesktop.org/series/116868/
>> These patches are included here because the last patch
>> has
>From MTL onwards, we need to find the best QGV point based on
the required data rate and pass the peak BW of that point to
the punit to lock the corresponding QGV point.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 87 -
While configuring pmdemand parameters, there could be
intel_get_crtc_new_encoder call where encoders could be 0. To avoid
invoking drm_warn in such cases, use a parameter to indicate drm_warn
should be suppressed.
v2: checkpatch warning fixes
Signed-off-by: Vinod Govindapillai
---
From: Mika Kahola
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case
Extract intel_bw_check_qgv_points() from intel_bw_atomic_check
to facilitate future platform variations in handling SAGV
configurations.
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 235 +---
1 file changed, 130 insertions(+), 105
MTL uses the peak BW of a QGV point to lock the required QGV
point instead of the QGV index. Instead of passing the deratedbw
of the selected bw_info, return the index to the selected
bw_info so that either deratedbw or peakbw can be used based on
the platform.
v2: use idx to store index returned
In MTL onwards, pcode locks the GV point based on the peak BW
of a QGV point. So store the peak BW of all the QGV points.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 7 +--
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
>From MTL onwwards, pcode locks the QGV point based on peak BW of
the intended QGV point passed by the driver. So the peak BW
calculation must match the value expected by the pcode. Update
the calculations as per the Bspec.
Bspec: 64636
Signed-off-by: Vinod Govindapillai
---
Follow the values from bspec for the percentage overhead for
efficiency in MTL BW calculations.
Bspec: 64631
Signed-off-by: Vinod Govindapillai
---
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
pmdemand support patches for MTL
SAGV configuration support for MTL
v2: added one missing patch in the previous version
v3: chekcpatch warning fixes
update index handling for the icl/tgl QGV point handling
program pmdemand code simplified
v4: update to debufs and pipe values pmdemand
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