Hi Mitul,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/Mitul-Golani/drm-display-dp-Add-helper-function-to-get-DSC-bpp-precision/20230929-162949
base: git://anongit.freedesktop.org/drm
== Series Details ==
Series: drm/i915/dp_mst: Make sure pbn_div is up-to-date after sink reconnect
URL : https://patchwork.freedesktop.org/series/124462/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13693_full -> Patchwork_124462v1_full
== Series Details ==
Series: Test MTL DMC v2.17 (rev3)
URL : https://patchwork.freedesktop.org/series/124083/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13693_full -> Patchwork_124083v3_full
Summary
---
== Series Details ==
Series: series starting with [1/5] drm/i915/fbc: Remove ancient 16k plane
stride limit (rev2)
URL : https://patchwork.freedesktop.org/series/123687/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13693_full -> Patchwork_123687v2_full
== Series Details ==
Series: drm/i915/display: Include i915_active header in frontbuffer tracking
code
URL : https://patchwork.freedesktop.org/series/124449/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13693_full -> Patchwork_124449v1_full
== Series Details ==
Series: drm/i915: Abstract display info away during probe
URL : https://patchwork.freedesktop.org/series/124474/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13693 -> Patchwork_124474v1
Summary
== Series Details ==
Series: series starting with [v2,1/4] drm/i915: Define and use GuC and CTB TLB
invalidation routines
URL : https://patchwork.freedesktop.org/series/124472/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13693 -> Patchwork_124472v1
== Series Details ==
Series: drm/i915/display: Created exclusive version of vga decode setup (rev2)
URL : https://patchwork.freedesktop.org/series/124296/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13693_full -> Patchwork_124296v2_full
== Series Details ==
Series: series starting with [v2,1/4] drm/i915: Define and use GuC and CTB TLB
invalidation routines
URL : https://patchwork.freedesktop.org/series/124472/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: series starting with [v2,1/4] drm/i915: Define and use GuC and CTB TLB
invalidation routines
URL : https://patchwork.freedesktop.org/series/124472/
State : warning
== Summary ==
Error: dim checkpatch failed
11e3929526f1 drm/i915: Define and use GuC and CTB TLB
== Series Details ==
Series: drm/i915/gem: Make i915_gem_shrinker multi-gt aware (rev7)
URL : https://patchwork.freedesktop.org/series/124112/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13693_full -> Patchwork_124112v7_full
The goal is to have this function ready for Xe to use
directly. So, let's use the available macro.
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Chris Wilson
With multi-GT devices, the object may have been bound on each GT and so
we need to invalidate the TLBs across all GT before releasing the pages
back to the system.
Signed-off-by: Chris Wilson
Signed-off-by: Jonathan Cavitt
CC: Matt Roper
CC: Andi Shyti
---
From: Fei Yang
Add a new header file for GT related Macros.
Move I915_MAX_GT to this new header file because it doesn't
belong to the i915 level.
Suggested-by: Andi Shyti
Signed-off-by: Fei Yang
Signed-off-by: Jonathan Cavitt
CC: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tlb, invalidating
the GuC TLBs and falling back
From: Fei Yang
In case of GT is suspended or wedged, don't allow submission of new TLB
invalidation request and cancel all pending requests. The TLB entries
will be invalidated either during GuC reload or on system resume.
Signed-off-by: Fei Yang
Signed-off-by: Jonathan Cavitt
CC: John
Definitely a TODO there that I no longer can remember why I didn't just do
this in the first place, lol. Thank you for the fix
Reviewed-by: Lyude Paul
On Fri, 2023-09-29 at 18:49 +0300, Imre Deak wrote:
> Atm the MST encoder config computation may use an out-of-date pbn_div
> value, if the sink
On Fri, 22 Sep 2023 10:32:05 -0700, Kees Cook wrote:
> This is a batch of patches touching drm for preparing for the coming
> implementation by GCC and Clang of the __counted_by attribute. Flexible
> array members annotated with __counted_by can have their accesses
> bounds-checked at run-time
== Series Details ==
Series: drm/i915/dp_mst: Make sure pbn_div is up-to-date after sink reconnect
URL : https://patchwork.freedesktop.org/series/124462/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13693 -> Patchwork_124462v1
== Series Details ==
Series: series starting with [1/2] drm/i915: Define and use GuC and CTB TLB
invalidation routines
URL : https://patchwork.freedesktop.org/series/124460/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13693 -> Patchwork_124460v1
== Series Details ==
Series: series starting with [1/2] drm/i915: Define and use GuC and CTB TLB
invalidation routines
URL : https://patchwork.freedesktop.org/series/124460/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be
== Series Details ==
Series: series starting with [1/2] drm/i915: Define and use GuC and CTB TLB
invalidation routines
URL : https://patchwork.freedesktop.org/series/124460/
State : warning
== Summary ==
Error: dim checkpatch failed
5a3f4a8e69fc drm/i915: Define and use GuC and CTB TLB
== Series Details ==
Series: Test MTL DMC v2.17 (rev3)
URL : https://patchwork.freedesktop.org/series/124083/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13693 -> Patchwork_124083v3
Summary
---
**SUCCESS**
No
== Series Details ==
Series: series starting with [1/5] drm/i915/fbc: Remove ancient 16k plane
stride limit (rev2)
URL : https://patchwork.freedesktop.org/series/123687/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13693 -> Patchwork_123687v2
== Series Details ==
Series: drm/i915/display: Include i915_active header in frontbuffer tracking
code
URL : https://patchwork.freedesktop.org/series/124449/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13693 -> Patchwork_124449v1
Atm the MST encoder config computation may use an out-of-date pbn_div
value, if the sink is unplugged and a sink is replugged with different
link rate/lane count capabilities. The current way of reinitializing
pbn_div depends on pbn_div getting cleared via intel_atomic_check() ->
On Fri, Sep 29, 2023 at 12:09:49PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We have a nice error message displayed when an user with insufficient
permissions tries to run the tool, but that got lost while Meteorlake
support was added. Bring it back in.
v2:
* Propagate unexpected
From: Prathap Kumar Valsan
The GuC firmware had defined the interface for Translation Look-Aside
Buffer (TLB) invalidation. We should use this interface when
invalidating the engine and GuC TLBs.
Add additional functionality to intel_gt_invalidate_tlb, invalidating
the GuC TLBs and falling back
From: Fei Yang
In case of GT is suspended or wedged, don't allow submission of new TLB
invalidation request and cancel all pending requests. The TLB entries
will be invalidated either during GuC reload or on system resume.
Signed-off-by: Fei Yang
Signed-off-by: Jonathan Cavitt
CC: John
== Series Details ==
Series: drm/i915/display: Created exclusive version of vga decode setup (rev2)
URL : https://patchwork.freedesktop.org/series/124296/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13693 -> Patchwork_124296v2
== Series Details ==
Series: drm/i915: i915_drv.h and i915_gpu_error.h include diet (rev2)
URL : https://patchwork.freedesktop.org/series/124418/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
CC [M]
== Series Details ==
Series: drm/i915/gem: Make i915_gem_shrinker multi-gt aware (rev7)
URL : https://patchwork.freedesktop.org/series/124112/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13693 -> Patchwork_124112v7
== Series Details ==
Series: Add DSC fractional bpp support (rev9)
URL : https://patchwork.freedesktop.org/series/111391/
State : failure
== Summary ==
Error: make failed
CALLscripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
CC [M]
On Thu, Sep 28, 2023 at 03:26:16PM +, Wei Liu wrote:
> Please change the prefix to "Drivers: hv:" in the subject line in the
> two patches.
I'll change the commit message for the 14/15 patch from "hyper-v/azure"
to "Drivers: hv:". But I only see one patch that needs this. Which is
the other
On Thu, Sep 28, 2023 at 03:36:55PM +0200, Greg Kroah-Hartman wrote:
> On Thu, Sep 28, 2023 at 03:21:26PM +0200, Joel Granados via B4 Relay wrote:
> > From: Joel Granados
> >
> > This commit comes at the tail end of a greater effort to remove the
> > empty elements at the end of the ctl_table
On Thu, Sep 28, 2023 at 03:26:16PM +, Wei Liu wrote:
> Please change the prefix to "Drivers: hv:" in the subject line in the
> two patches.
>
> On Thu, Sep 28, 2023 at 03:21:39PM +0200, Joel Granados via B4 Relay wrote:
> > From: Joel Granados
> >
> > This commit comes at the tail end of a
On Thu, Sep 28, 2023 at 12:51:15PM -0500, Steve Wahl wrote:
> On Thu, Sep 28, 2023 at 03:21:36PM +0200, Joel Granados via B4 Relay wrote:
> > From: Joel Granados
> >
> > This commit comes at the tail end of a greater effort to remove the
> > empty elements at the end of the ctl_table arrays
On 19.09.23 16:08, Bagas Sanjaya wrote:
> On Sat, Sep 02, 2023 at 06:14:12PM +0200, Oleksandr Natalenko wrote:
>>
>> Since v6.5 kernel the following HW:
>>
>> * Lenovo T460s laptop with Skylake GT2 [HD Graphics 520] (rev 07)
>> * Lenovo T490s laptop with WhiskeyLake-U GT2 [UHD Graphics 620] (rev
== Series Details ==
Series: Update GGTT with MI_UPDATE_GTT on MTL (rev11)
URL : https://patchwork.freedesktop.org/series/123329/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13693 -> Patchwork_123329v11
Summary
---
== Series Details ==
Series: Update GGTT with MI_UPDATE_GTT on MTL (rev11)
URL : https://patchwork.freedesktop.org/series/123329/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Update GGTT with MI_UPDATE_GTT on MTL (rev11)
URL : https://patchwork.freedesktop.org/series/123329/
State : warning
== Summary ==
Error: dim checkpatch failed
515de5f4d67c drm/i915: Lift runtime-pm acquire callbacks out of
intel_wakeref.mutex
-:66:
Quoting Jani Nikula (2023-09-28 04:43:13-03:00)
>On Thu, 28 Sep 2023, Jouni Högander wrote:
>> i915_gem_object_set_frontbuffer returns set frontbuffer pointer. When we
>> are releasing frontbuffer we are clearing the pointer from the object. Warn
>> on if return value is not null.
>>
>> v2:
All 5 patches look ok to me, I didn't spot anything to comment about.
Reviewed-by: Juha-Pekka Heikkila
On 14.9.2023 14.38, Ville Syrjala wrote:
From: Ville Syrjälä
The 16k max plane stride limit seems to be originally from
i965gm, and no limit explicit limit has been specified since (g4x+).
== Series Details ==
Series: drm/i915: fix rb-tree/llist/list confusion (rev3)
URL : https://patchwork.freedesktop.org/series/123282/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13691_full -> Patchwork_123282v3_full
From: Tvrtko Ursulin
Igt_drm_fdinfo defines it as an unsigned long so it is best that it
matches here as well.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 2 +-
lib/igt_drm_clients.h | 2 +-
tools/intel_gpu_top.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff
From: Tvrtko Ursulin
JSON output has the full breakdown but for now the interactive mode only
shows total and resident aggregated for all memory regions.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 114 +-
1 file changed, 112
From: Tvrtko Ursulin
Similar as we can toggle between aggregated engines and clients, add the
capability to toggle between aggregated and per memory region stats.
It starts in aggregated mode by default and interactive command 'm' and
command line switch '-m' can be used to toggle that.
Both
From: Tvrtko Ursulin
Same concept as with the engine map, allowing callers to pass in fixed
map of names to indices, simplifying their implementation and avoiding
auto-detection while parsing.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_clients.c | 5 +++--
lib/igt_drm_clients.h | 3 ++-
From: Tvrtko Ursulin
Wrap all operations on clients via the Intel specific wrappers in order to
simplify upcoming work.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 42 ++
1 file changed, 22 insertions(+), 20 deletions(-)
diff --git
From: Tvrtko Ursulin
I will need some record of which regions were found for intel_gpu_top so
lets just copy over the region name from the map on the first match.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_fdinfo.c | 4
1 file changed, 4 insertions(+)
diff --git
From: Tvrtko Ursulin
When I moved the client name to be last, I did not account for the fact
current code skips showing engine utilisation until at least two sampling
periods have passed. Consequence of this is that client name gets printed
as the second field and not under the "NAME" column
From: Tvrtko Ursulin
Padding the percentage bars and table columns with spaces happens quite a
lot so lets do better than putchar at a time. Have a table of visually
empty strings and build the required length out of those chunks.
While at it, also move the percentage bar table into its
From: Tvrtko Ursulin
Recent refactoring broke the clients header in cases when there are no
clients displayed. To fix it we need to account the width of the "NAME"
label.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff
From: Tvrtko Ursulin
A few basic smoke tests to check per client memory info looks legit.
Signed-off-by: Tvrtko Ursulin
---
tests/intel/drm_fdinfo.c | 217 +++
1 file changed, 217 insertions(+)
diff --git a/tests/intel/drm_fdinfo.c
From: Tvrtko Ursulin
On top of checking that parsing works, check that there are some engines
present. This will be needed once the memory stats are added and so return
value from __igt_parse_drm_fdinfo() will then be possible to be greater
than zero even when engine stats are not supported.
From: Tvrtko Ursulin
A short smoke tests to exercise fdinfo reads in parallel to contexts
getting created and destroyed.
Signed-off-by: Tvrtko Ursulin
---
tests/intel/drm_fdinfo.c | 68
1 file changed, 68 insertions(+)
diff --git
From: Tvrtko Ursulin
Some basic testst for fdinfo memory stats, intel_gpu_top memory stats support
(first draft) and a couple fixlets.
Tvrtko Ursulin (12):
tests/i915/drm_fdinfo: Check engine info is supported
tests/i915/drm_fdinfo: Stress test context close versus fdinfo reads
On Fri, 29 Sep 2023, Jouni Högander wrote:
> Intel frontbuffer tracking code is using i915_active functions -> include
> i915_active.h directly instead of relying getting indirectly included.
>
> Cc: Jani Nikula
>
> Signed-off-by: Jouni Högander
Reviewed-by: Jani Nikula
> ---
>
Intel frontbuffer tracking code is using i915_active functions -> include
i915_active.h directly instead of relying getting indirectly included.
Cc: Jani Nikula
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_frontbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On 28/09/2023 22:31, Umesh Nerlige Ramappa wrote:
On Thu, Sep 28, 2023 at 09:16:23AM +0100, Tvrtko Ursulin wrote:
On 27/09/2023 21:13, Umesh Nerlige Ramappa wrote:
On Fri, Sep 22, 2023 at 02:44:28PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We have a nice error message displayed
From: Tvrtko Ursulin
We have a nice error message displayed when an user with insufficient
permissions tries to run the tool, but that got lost while Meteorlake
support was added. Bring it back in.
v2:
* Propagate unexpected errno on multi-tile systems too. (Umesh)
Signed-off-by: Tvrtko
On Thu, 14 Sep 2023, Rodrigo Vivi wrote:
> On Tue, Sep 12, 2023 at 02:06:27PM +0300, Jani Nikula wrote:
>> The upcoming drm/xe driver [1][2] will reuse the drm/i915 display code,
>> initially by compiling the relevant compilation units separately as part
>> of the xe driver. This series prepares
On 28/09/2023 19:20, Mathias Krause wrote:
Chaining user engines happens in multiple passes during driver
initialization, mutating its type along the way. It starts off with a
simple lock-less linked list (struct llist_node/head) populated by
intel_engine_add_user() which later gets sorted and
On 28/09/2023 19:20, Mathias Krause wrote:
Commit 1ec23ed7126e ("drm/i915: Use uabi engines for the default engine
map") switched from using for_each_engine() to for_each_uabi_engine() to
iterate over the user engines. While this seems to be a sensible change,
it's only safe to do when the
el tags/drm-intel-next-2023-09-29
for you to fetch changes up to 3570bd989acc66add5726785058cceffa06b1f54:
drm/i915: Update DRIVER_DATE to 20230929 (2023-09-29 12:43:23 +0300)
drm/i915 feature pull for v6.7:
Features and functi
On Thu, 21 Sep 2023, Ville Syrjälä wrote:
> On Thu, Sep 21, 2023 at 11:40:22AM -0300, Gustavo Sousa wrote:
>> Quoting Ville Syrjälä (2023-09-20 17:29:42-03:00)
>> >On Wed, Sep 20, 2023 at 05:13:36PM -0300, Gustavo Sousa wrote:
>> >> Quoting Ville Syrjälä (2023-09-20 17:00:07-03:00)
>> >> >On Wed,
On Thu, Sep 28, 2023 at 03:21:36PM +0200, Joel Granados via B4 Relay wrote:
> From: Joel Granados
>
> This commit comes at the tail end of a greater effort to remove the
> empty elements at the end of the ctl_table arrays (sentinels) which
> will reduce the overall build time size of the kernel
On 9/28/2023 11:42 PM, Andrzej Hajda wrote:
On 28.09.2023 15:00, Nirmoy Das wrote:
Implement intel_gt_mcr_lock_sanitize() to provide a mechanism
for cleaning the steer semaphore when absolutely necessary.
v2: remove unnecessary lock(Andi, Matt)
improve the kernel doc(Matt)
Thanks reviewing this series. Merged it in gt-next so hopefully we have
bit greener CI for MTL now.
Regards,
Nirmoy
On 9/28/2023 3:00 PM, Nirmoy Das wrote:
Implement intel_gt_mcr_lock_sanitize() to provide a mechanism
for cleaning the steer semaphore when absolutely necessary.
v2: remove
On Thu, 2023-09-28 at 11:56 +0300, Jani Nikula wrote:
> On Thu, 28 Sep 2023, Jouni Högander wrote:
> > i915_gem_object_set_frontbuffer returns set frontbuffer pointer.
> > When we
> > are releasing frontbuffer we are clearing the pointer from the
> > object. Warn
> > on if return value is not
Current vga arbiter implementation in i915 needs a re-design.
The current approach would cause real problems if anyone actually
needs to talk another GPU using legacy VGA resources.
The main issue is that X becomes a slideshow if it thinks there
are multiple GPUs that have VGA decoding enabled as
Reduce gpu error interface further by doing more in
i915_gpu_coredump_alloc().
v2: Fix build for CONFIG_DRM_I915_CAPTURE_ERROR=n
Signed-off-by: Jani Nikula
---
.../drm/i915/gt/intel_execlists_submission.c | 16 +---
drivers/gpu/drm/i915/i915_gpu_error.c | 38 +--
From: Swati Sharma
If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if the computed compressed bpp
turns out to be a integer.
v2:
-Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
-Fix comment (Suraj)
Signed-off-by:
From: Swati Sharma
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if
From: Ankit Nautiyal
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
v1:
Replace the computation of 'data_clock' with 'data_clock =
DIV_ROUND_UP(data_clock, 16).'
From: Vandita Kulkarni
Consider the fractional bpp while reading the qp values.
v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
Signed-off-by: Vandita Kulkarni
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
Reviewed-by: Sui Jingfeng
---
From: Ankit Nautiyal
DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the
From: Ankit Nautiyal
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.
v2:
-Fixed tu_data calculation while dealing with U6.4
From: Ankit Nautiyal
This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
Reviewed-by: Sui Jingfeng
---
From: Ankit Nautiyal
Add helper to get the DSC bits_per_pixel precision for the DP sink.
Signed-off-by: Ankit Nautiyal
Reviewed-by: Suraj Kandpal
Reviewed-by: Sui Jingfeng
Acked-by: Maxime Ripard
---
drivers/gpu/drm/display/drm_dp_helper.c | 27 +
This patch series adds support for DSC fractional compressed bpp
for MTL+. The series starts with some fixes, followed by patches that
lay groundwork to iterate over valid compressed bpps to select the
'best' compressed bpp with optimal link configuration (taken from
upstream series:
== Series Details ==
Series: drm/i915: fix rb-tree/llist/list confusion (rev3)
URL : https://patchwork.freedesktop.org/series/123282/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13691 -> Patchwork_123282v3
Summary
== Series Details ==
Series: drm/i915: fix rb-tree/llist/list confusion (rev3)
URL : https://patchwork.freedesktop.org/series/123282/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: fix rb-tree/llist/list confusion (rev3)
URL : https://patchwork.freedesktop.org/series/123282/
State : warning
== Summary ==
Error: dim checkpatch failed
c3b39f18415f drm/i915: Register engines early to avoid type confusion
-:40: ERROR:BAD_SIGN_OFF:
== Series Details ==
Series: fbc on any planes (rev3)
URL : https://patchwork.freedesktop.org/series/123180/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13671 -> Patchwork_123180v3
Summary
---
**SUCCESS**
No
Hi Jani,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-tip/drm-tip]
url:
https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-i915-stop-including-i915_utils-h-from-intel_runtime_pm-h/20230929-021205
base: git://anongit.freedesktop.org
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