[Intel-gfx] Regression on linux-next (next-20231016)

2023-10-19 Thread Borah, Chaitanya Kumar
Hello Lorenzo, Hope you are doing well. I am Chaitanya from the linux graphics team in Intel. This mail is regarding a regression we are seeing in our CI runs[1] on linux-next repository. Since the version next-20231016 [2], we are seeing the following error

[Intel-gfx] [PATCH v2 5/9] drm/ci: clean up xfails (specially flakes list)

2023-10-19 Thread Helen Koike
Since the script that collected the list of the expectation files was bogus and placing test to the flakes list incorrectly, restart the expectation files with the correct script. This reduces a lot the number of tests in the flakes list. Signed-off-by: Helen Koike Reviewed-by: David Heidelberg

Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree

2023-10-19 Thread Stephen Rothwell
Hi all, On Thu, 12 Oct 2023 12:27:49 +1100 Stephen Rothwell wrote: > > On Thu, 12 Oct 2023 12:22:09 +1100 Stephen Rothwell > wrote: > > > > After merging the drm-misc tree, today's linux-next build (x86_64 > > allmodconfig) failed like this: > > > > drivers/usb/typec/altmodes/displayport.c:

Re: [Intel-gfx] [PATCH 3/3] drm/i915/mtl: Add counters for engine busyness ticks

2023-10-19 Thread John Harrison
On 10/19/2023 09:21, Dong, Zhanjun wrote: See comments inline below. Zhanjun On 2023-09-22 6:25 p.m., john.c.harri...@intel.com wrote: From: Umesh Nerlige Ramappa In new version of GuC engine busyness, GuC provides engine busyness ticks as a 64 bit counter. Add a new counter to relay this

[Intel-gfx] [PATCH] drm/i915/pmu: Check if pmu is closed before stopping event

2023-10-19 Thread Umesh Nerlige Ramappa
When the driver unbinds, pmu is unregistered and i915->uabi_engines is set to RB_ROOT. Due to this, when i915 PMU tries to stop the engine events, it issues a warn_on because engine lookup fails. All perf hooks are taking care of this using a pmu->closed flag that is set when PMU unregisters. The

[Intel-gfx] [PATCH] drm/i915/pmu: Check is pmu is closed before stopping event

2023-10-19 Thread Umesh Nerlige Ramappa
When the driver unbinds, pmu is unregistered and i915->uabi_engines is set to RB_ROOT. Due to this, when i915 PMU tries to stop the engine events, it issues a warn_on because engine lookup fails. All perf hooks are taking care of this using a pmu->closed flag that is set when PMU unregisters. The

[Intel-gfx] [PATCH] drm/i915/pmu: Check is pmu is closed before stopping event

2023-10-19 Thread Umesh Nerlige Ramappa
When the driver unbinds, pmu is unregistered and i915->uabi_engines is set to RB_ROOT. Due to this, when i915 PMU tries to stop the engine events, it issues a warn_on because engine lookup fails. All perf hooks are taking care of this using a pmu->closed flag that is set when PMU unregisters. The

[Intel-gfx] [PATCH v2] drm/i915/mcr: Hold GT forcewake during steering operations

2023-10-19 Thread Matt Roper
The steering control and semaphore registers are inside an "always on" power domain with respect to RC6. However there are some issues if higher-level platform sleep states are entering/exiting at the same time these registers are accessed. Grabbing GT forcewake and holding it over the entire

Re: [Intel-gfx] [PATCH 2/2] drm/i915/display: Abstract C10/C20 pll calculation

2023-10-19 Thread Gustavo Sousa
Quoting Lucas De Marchi (2023-10-18 19:28:31-03:00) >As done with the hw readout, properly abstract the C10/C20 phy details >inside intel_cx0_phy.c. > >Signed-off-by: Lucas De Marchi Reviewed-by: Gustavo Sousa >--- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 >

Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: Abstract C10/C20 pll hw readout

2023-10-19 Thread Gustavo Sousa
Quoting Lucas De Marchi (2023-10-18 19:28:30-03:00) >intel_cx0_phy.[ch] should contain the details about C10/C20, not leaking >it to the rest of the driver. Start abstracting this by exporting a >single PLL hw readout that handles the differences between C20 and C10 >internally to that compilation

[Intel-gfx] [PATCH] drm/i915/mcr: Hold GT forcewake during steering operations

2023-10-19 Thread Matt Roper
The steering control and semaphore registers are inside an "always on" power domain with respect to RC6. However there are some issues if higher-level platform sleep states are entering/exiting at the same time these registers are accessed. Grabbing GT forcewake and holding it over the entire

Re: [Intel-gfx] [PATCH 3/3] drm/i915/mtl: Add counters for engine busyness ticks

2023-10-19 Thread Dong, Zhanjun
See comments inline below. Zhanjun On 2023-09-22 6:25 p.m., john.c.harri...@intel.com wrote: From: Umesh Nerlige Ramappa In new version of GuC engine busyness, GuC provides engine busyness ticks as a 64 bit counter. Add a new counter to relay this value to the user as is. Signed-off-by:

[Intel-gfx] [PULL] drm-intel-fixes

2023-10-19 Thread Rodrigo Vivi
Hi Dave and Daniel, Here goes drm-intel-fixes-2023-10-19: - Fix display issue that was blocking S0ix (Khaled) - Retry gtt fault when out of fence registers (Ville) Thanks, Rodrigo. The following changes since commit 58720809f52779dc0f08e53e54b014209d13eebb: Linux 6.6-rc6 (2023-10-15

[Intel-gfx] [PULL] drm-intel-next

2023-10-19 Thread Rodrigo Vivi
Hi Dave and Daniel, This is our last pull request towards 6.7. I'm sending this on behalf of Jani, who was covering this round. The main reason for this extra PR is to ensure that we get MTL force_probe removed on 6.7. The platform has a good green picture in our BAT CI currently and is stable.

Re: [Intel-gfx] [PATCH 2/2] drm/i915/lnl: Fix check for TC phy

2023-10-19 Thread Gustavo Sousa
Quoting Lucas De Marchi (2023-10-18 19:24:41-03:00) >With MTL adding PICA between the port and the real phy, the path >add for DG2 stopped being followed and newer platforms are simply using >the older path for TC phys. LNL is no different than MTL in this aspect, >so just add it to the mess. In

Re: [Intel-gfx] [PATCH 1/2] drm/i915/lnl: Extend C10/C20 phy

2023-10-19 Thread Gustavo Sousa
Quoting Lucas De Marchi (2023-10-18 19:24:40-03:00) >For Lunar Lake, DDI-A is connected to C10 PHY, while TC1-TC3 are connected >to C20 phy, like in Meteor Lake. Update the check in intel_is_c10phy() >accordingly. > >This reverts the change in commit e388ae97e225 ("drm/i915/display: >Eliminate

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3 (rev5)

2023-10-19 Thread Andi Shyti
Hi Nirmoy, > > > > Possible regressions > > > > > > > >    • igt@gem_exec_nop@basic-series: > > > > > > > >    □ shard-glk: PASS -> INCOMPLETE +1 other test incomplete > > > >    • > > > > igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: > > > > > > > >    □

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3 (rev5)

2023-10-19 Thread Nirmoy Das
On 10/19/2023 10:14 AM, Tvrtko Ursulin wrote: On 18/10/2023 17:43, Andi Shyti wrote: Hi Vinay, Possible regressions    • igt@gem_exec_nop@basic-series:    □ shard-glk: PASS -> INCOMPLETE +1 other test incomplete    •

[Intel-gfx] [PULL] drm-intel-gt-next

2023-10-19 Thread Tvrtko Ursulin
Hi Dave, Daniel, Here is the final pull request for 6.7. As indicated that it may happen in the last pull, the remaining missing functionality for Meteorlake, enabling the GuC based TLB invalidation, has since been merged and platform thought to be ready for lifting out of force probe status.

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3 (rev5)

2023-10-19 Thread Andi Shyti
On Thu, Oct 19, 2023 at 09:14:13AM +0100, Tvrtko Ursulin wrote: > > On 18/10/2023 17:43, Andi Shyti wrote: > > Hi Vinay, > > > > > Possible regressions > > > > > >• igt@gem_exec_nop@basic-series: > > > > > >□ shard-glk: PASS -> INCOMPLETE +1 other test incomplete > > >•

[Intel-gfx] [PATCH v3 1/3] pwm: make it possible to apply pwm changes in atomic context

2023-10-19 Thread Sean Young
Some drivers require sleeping, for example if the pwm device is connected over i2c. The pwm-ir-tx requires precise timing, and sleeping causes havoc with the generated IR signal when sleeping occurs. This patch makes it possible to use pwm when the driver does not sleep, by introducing the

[Intel-gfx] [PULL] drm-misc-fixes

2023-10-19 Thread Thomas Zimmermann
Hi Dave and Daniel, this is the PR for drm-misc-fixes. Best regards Thomas drm-misc-fixes-2023-10-19: Short summary of fixes pull: amdgpu: - Disable AMD_CTX_PRIORITY_UNSET bridge: - ti-sn65dsi86: Fix device lifetime edid: - Add quirk for BenQ GW2765 ivpu: - Extend address range for MMU mmap

[Intel-gfx] [PULL] drm-misc-next

2023-10-19 Thread Maarten Lankhorst
drm-misc-next-2023-10-19: drm-misc-next for v6.7-rc1: UAPI Changes: Cross-subsystem Changes: - Update maintainers entry for megachips STDPx-GE-B850V3-FW. Core Changes: - Add VM_BIND async document. - Dual-license drm_gpuvm to GPL-2.0 OR MIT. Driver Changes: - Assorted small fixes in ivpu,

Re: [Intel-gfx] [CI] PR for new GuC v70.13.1

2023-10-19 Thread Josh Boyer
Already merged. josh On Wed, Oct 18, 2023 at 3:11 PM John Harrison wrote: > > Apologies, I sent this with the wrong subject. Please ignore. Will > resend with the correct subject. > > John. > > > On 10/18/2023 12:07, john.c.harri...@intel.com wrote: > > The following changes since commit

Re: [Intel-gfx] [PATCH v3 1/3] pwm: make it possible to apply pwm changes in atomic context

2023-10-19 Thread Uwe Kleine-König
On Wed, Oct 18, 2023 at 03:57:48PM +0200, Hans de Goede wrote: > Hi Sean, > > On 10/17/23 11:17, Sean Young wrote: > > Some drivers require sleeping, for example if the pwm device is connected > > over i2c. The pwm-ir-tx requires precise timing, and sleeping causes havoc > > with the generated IR

Re: [Intel-gfx] [PATCH v2] debugobjects: stop accessing objects after releasing spinlock

2023-10-19 Thread Andrzej Hajda
On 13.10.2023 15:15, Thomas Gleixner wrote: On Mon, Sep 25 2023 at 15:13, Andrzej Hajda wrote: After spinlock release object can be modified/freed by concurrent thread. Using it in such case is error prone, even for printing object state. It cannot be freed. If that happens then the calling

Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: remove display device info from i915 capabilities

2023-10-19 Thread Borah, Chaitanya Kumar
> -Original Message- > From: Govindapillai, Vinod > Sent: Wednesday, October 18, 2023 3:57 PM > To: intel-gfx@lists.freedesktop.org > Cc: Govindapillai, Vinod ; Sharma, Swati2 > ; Borah, Chaitanya Kumar > > Subject: [PATCH v4 2/2] drm/i915: remove display device info from i915 >

Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/display: debugfs entry to list display capabilities

2023-10-19 Thread Borah, Chaitanya Kumar
> -Original Message- > From: Govindapillai, Vinod > Sent: Wednesday, October 18, 2023 3:57 PM > To: intel-gfx@lists.freedesktop.org > Cc: Govindapillai, Vinod ; Sharma, Swati2 > ; Borah, Chaitanya Kumar > > Subject: [PATCH v4 1/2] drm/i915/display: debugfs entry to list display >

Re: [Intel-gfx] [PATCH v2 9/9] drm/i915: Use kmap_local_page() in gem/i915_gem_execbuffer.c

2023-10-19 Thread Tvrtko Ursulin
Hi, On 18/10/2023 17:19, Zhao Liu wrote: Hi Rodrigo and Tvrtko, It seems this series is missed in v6.5. This work should not be forgotten. Let me rebase and refresh the version. Right it seems we did not manage to social engineer any reviews. Please do respin and we will try again.

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3 (rev5)

2023-10-19 Thread Tvrtko Ursulin
On 18/10/2023 17:43, Andi Shyti wrote: Hi Vinay, Possible regressions • igt@gem_exec_nop@basic-series: □ shard-glk: PASS -> INCOMPLETE +1 other test incomplete • igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: □ shard-dg2: PASS -> TIMEOUT •