== Series Details ==
Series: drm/i915/dsi: Use devm_gpiod_get() for all GPIOs
URL : https://patchwork.freedesktop.org/series/127206/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13962 -> Patchwork_127206v1
Summary
---
== Series Details ==
Series: drm/i915/gt: Reduce log severity on reset prepare.
URL : https://patchwork.freedesktop.org/series/127204/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13962 -> Patchwork_127204v1
Summary
== Series Details ==
Series: QGV/SAGV related fixes (rev3)
URL : https://patchwork.freedesktop.org/series/126962/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13962 -> Patchwork_126962v3
Summary
---
**FAILURE**
== Series Details ==
Series: QGV/SAGV related fixes (rev3)
URL : https://patchwork.freedesktop.org/series/126962/
State : warning
== Summary ==
Error: dim checkpatch failed
f1e1dd9cee4b drm/i915: Add meaningful traces for QGV point info error handling
e838d5faf383 drm/i915: Extract code
== Series Details ==
Series: drm/i915/hwmon: Fix issues found by static analysis tool in i915 hwmon
URL : https://patchwork.freedesktop.org/series/127199/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13962 -> Patchwork_127199v1
On Fri, Dec 01, 2023 at 02:41:33PM +0530, Melanie Lobo wrote:
> Supports FP16 format which is a binary floating-point computer
> number format that occupies 16 bits in computer memory.Platform shall
> render compression in display engine to receive FP16 compressed formats.
The explanation here is
== Series Details ==
Series: drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
URL : https://patchwork.freedesktop.org/series/127194/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13961 -> Patchwork_127194v1
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Fix engine reset count
storage for multi-tile
URL : https://patchwork.freedesktop.org/series/127186/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13961 -> Patchwork_127186v1
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Fix engine reset count
storage for multi-tile
URL : https://patchwork.freedesktop.org/series/127186/
State : warning
== Summary ==
Error: dim checkpatch failed
a15c9e77c642 drm/i915/selftests: Fix engine reset count
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Fix engine reset count
storage for multi-tile
URL : https://patchwork.freedesktop.org/series/127186/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be
On Tue, Nov 28, 2023 at 11:51:43AM +0200, Ville Syrjälä wrote:
> On Tue, Nov 28, 2023 at 10:43:36AM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 27, 2023 at 08:21:46AM -0800, Matt Roper wrote:
> > > On Fri, Nov 24, 2023 at 05:55:23PM -0300, Gustavo Sousa wrote:
> > > > The cdclk tables were
== Series Details ==
Series: drm/i915: handle uncore spinlock when not available (rev4)
URL : https://patchwork.freedesktop.org/series/125442/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13961 -> Patchwork_125442v4
On Thu, Nov 30, 2023 at 03:00:59PM -0500, Rodrigo Vivi wrote:
> On Wed, Nov 29, 2023 at 12:51:21PM -0800, Matt Atwood wrote:
> > Function reg_in_range_table is useful in more places, move function to
> > intel_uncore.h to make available to more places.
> >
> > Signed-off-by: Matt Atwood
> > ---
You're missing a digit in the patch subject.
On Wed, Nov 29, 2023 at 12:51:22PM -0800, Matt Atwood wrote:
> Wa_14011274333 applies to gen 12.0->12.55. There are regions of
> registers that restore to default values on resume from rc6. The
It would be more clear to write this sentence as "The TDL
Quoting Ville Syrjala (2023-11-28 08:51:38-03:00)
>From: Ville Syrjälä
>
>Drop the redundant dev_priv parameters from
>intel_ddi_compute_min_voltage_level() to make life easier.
>
>Signed-off-by: Ville Syrjälä
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/display/intel_ddi.c| 9
Quoting Ville Syrjala (2023-11-28 08:51:37-03:00)
>From: Ville Syrjälä
>
>On MTL we need to bump the voltage level to only 1 (not 2)
>when port clock exceeds 594MHz. Make it so.
>
>Signed-off-by: Ville Syrjälä
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
Quoting Ville Syrjala (2023-11-28 08:51:36-03:00)
>From: Ville Syrjälä
>
>The mess inside intel_ddi_compute_min_voltage_level() is illegible.
>Clean it up a bit by splitting the internals into per-platform
>functions.
>
>TODO: make it a vfunc?
>
>Signed-off-by: Ville Syrjälä
Reviewed-by:
== Series Details ==
Series: series starting with [v1,1/1] drm/i915/display: Don't use "proxy"
headers (rev3)
URL : https://patchwork.freedesktop.org/series/127051/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13961 -> Patchwork_127051v3
Quoting Ville Syrjala (2023-11-28 08:51:35-03:00)
>From: Ville Syrjälä
>
>Allow MTL to use voltage level 1 for 480MHz cdclk,
>instead of the voltage level 2 that it's currently using.
>
>Signed-off-by: Ville Syrjälä
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c
On Fri, 2023-12-01 at 02:37 +, zhuweixi wrote:
> From your argument on KVM I can see that the biggest miscommunication
> between us is that you believed that GMEM wanted to share the whole
> address space. No, it is not the case. GMEM is only providing
> coordination via certain mmap() calls.
Quoting Ville Syrjala (2023-11-28 08:51:34-03:00)
>From: Ville Syrjälä
>
>The cdclk->voltage_level if ladders are hard to read, especially as
>they're written the other way around compared to how bspec lists
>the limits. Let's rewrite them to use simple arrays that gives us
>the max cdclk for
== Series Details ==
Series: drm/i915/syncmap: squelch a sparse warning (rev3)
URL : https://patchwork.freedesktop.org/series/117802/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13961 -> Patchwork_117802v3
Summary
Quoting Ville Syrjala (2023-11-28 08:51:33-03:00)
>From: Ville Syrjälä
>
>Currently we have a hardcoded assumption that the cd2x divider
>is always 2 when squahsing is used.
It seems the code was actually making the assumption that the
divider is always 1. With the current code, when squashing
Quoting Ville Syrjala (2023-11-28 08:51:32-03:00)
>From: Ville Syrjälä
>
>Replace the slightly magic 'size = 16' with a bit more descriptive
>name. We'll have another user for this value later on.
>
>Signed-off-by: Ville Syrjälä
Reviewed-by: Gustavo Sousa
>---
>
Quoting Ville Syrjala (2023-11-28 08:51:31-03:00)
>From: Ville Syrjälä
>
>cdclk_pll_is_unknown() used ~0 when checking for the "VCO is
>unknown" value, but the assignment uses -1. They are the same
>in the end, but let's use the same ~0 form on both sides for
>consistency.
>
>Signed-off-by: Ville
On Fri, 2023-12-01 at 03:34 +, Patchwork wrote:
> Patch Details
> Series: drm/display/dp: Add the remaining Square PHY patterns
> DPCD register definitions (rev2)
> URL: https://patchwork.freedesktop.org/series/123149/
> State:failure
> Details:
>
On Fri, 2023-12-01 at 02:53 +, Patchwork wrote:
> Patch Details
> Series: series starting with [v2,1/2] drm/i915/dp: Use
> LINK_QUAL_PATTERN_* Phy test pattern names
> URL: https://patchwork.freedesktop.org/series/127146/
> State:failure
> Details:
>
== Series Details ==
Series: drm/i915/syncmap: squelch a sparse warning (rev3)
URL : https://patchwork.freedesktop.org/series/117802/
State : warning
== Summary ==
Error: dim checkpatch failed
4b5dd6e81799 drm/i915/syncmap: squelch a sparse warning
-:4: WARNING:EMAIL_SUBJECT: A patch subject
== Series Details ==
Series: drm/i915: Support FP16 compressed formats on MTL (rev5)
URL : https://patchwork.freedesktop.org/series/124957/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13961 -> Patchwork_124957v5
Summary
== Series Details ==
Series: drm/i915: Support FP16 compressed formats on MTL (rev5)
URL : https://patchwork.freedesktop.org/series/124957/
State : warning
== Summary ==
Error: dim checkpatch failed
a0a2a994cd92 drm/i915: Support FP16 compressed formats on MTL
-:19:
On Thu, Nov 30, 2023 at 10:52:17AM +0200, Jani Nikula wrote:
> On Wed, 29 Nov 2023, Hamza Mahfooz wrote:
> > Cc: Nathan Chancellor
> >
> > On 11/29/23 13:12, Jani Nikula wrote:
> >> At least the i915 and amd drivers enable a bunch more compiler warnings
> >> than the kernel defaults.
> >>
> >>
soc_gpio_set_value() already uses devm_gpiod_get(), lets be consistent
and use devm_gpiod_get() for all GPIOs.
This allows removing the intel_dsi_vbt_gpio_cleanup() function,
which only function was to put the GPIO-descriptors.
Signed-off-by: Hans de Goede
---
Note this applies on top of Andy's
gen8_engine_reset_prepare() can fail when HW fails to set
RESET_CTL_READY_TO_RESET bit. In some cases this is not fatal
error as driver will retry.
Let the caller of gen8_engine_reset_prepare() decide if a
failure in gen8_engine_reset_prepare is an error or not.
Cc: Tvrtko Ursulin
Cc: John
On Thu, Nov 30, 2023 at 04:43:38PM +0200, Jouni Högander wrote:
> We are preparing for Xe driver. Backing object implementation is differing
> between i915 and Xe. Split i915 specific code into separate source file
> built only for i915.
>
> v8:
> - return original error code from
On Fri, 2023-12-01 at 13:55 +, Govindapillai, Vinod wrote:
> On Wed, 2023-11-15 at 11:07 +0200, Jouni Högander wrote:
> > We are preparing for Xe driver. I915 and Xe object implementation
> > are
> > differing. Do not use i915_gem_object->base directly. Instead use
> > intel_bo_to_drm_bo.
> >
On Fri, 2023-12-01 at 13:53 +, Govindapillai, Vinod wrote:
> On Wed, 2023-11-15 at 11:07 +0200, Jouni Högander wrote:
> > Split out code from intel_fbdev that can not be share between i915
> > and
> > xe. Create new i915 specific source/header file intel_fbdev_fb.[ch]
> > which
> > contains
On Fri, Dec 01, 2023 at 03:41:41PM +0200, Jani Nikula wrote:
> The eDP 1.5 spec adds a clarification for eDP 1.4x:
>
> > For eDP v1.4x, if the Source device chooses the Main-Link rate by way
> > of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
>
> We write 0 to DP_LINK_BW_SET (DPCD
Problem is that on some platforms, we do get QGV point mask in wrong
state on boot. However driver assumes it is set to 0
(i.e all points allowed), however in reality we might get them all restricted,
causing issues.
Lets disable SAGV initially to force proper QGV point state.
If more QGV points
Updated i915 hwmon with fixes for issues reported by static analysis tool.
Fixed unintentional buffer overflow (OVERFLOW_BEFORE_WIDEN) with upcasting.
Fixes: 4c2572fe0ae7 ("drm/i915/hwmon: Expose power1_max_interval")
Signed-off-by: Karthik Poosa
---
drivers/gpu/drm/i915/i915_hwmon.c | 4 ++--
Friendly ping. I think this patch was forgotten.
主 题：[PATCH v2] drm/i915: correct the input parameter on _intel_dsb_commit() 日 期：2023-11-14 10:43 发件人：何敏红 收件人：何敏红;
Current, the dewake_scanline variable is defined as unsigned int,an unsigned int variable that is always greater than or
On Wed, 2023-11-15 at 11:07 +0200, Jouni Högander wrote:
> We are preparing for Xe driver. I915 and Xe object implementation are
> differing. Do not use i915_gem_object->base directly. Instead use
> intel_bo_to_drm_bo.
>
> Signed-off-by: Jouni Högander
> Signed-off-by: Maarten Lankhorst
> ---
On Wed, 2023-11-15 at 11:07 +0200, Jouni Högander wrote:
> Split out code from intel_fbdev that can not be share between i915 and
> xe. Create new i915 specific source/header file intel_fbdev_fb.[ch] which
> contains this code.
>
> Signed-off-by: Jouni Högander
> ---
>
Hi Karthik,
On 01-12-2023 10:28, Karthik Poosa wrote:
Updated i915 hwmon with fixes for issues reported by static analysis tool.
Fixed unintentional buffer overflow (OVERFLOW_BEFORE_WIDEN) with upcasting.
v2: Updated commit message with details of issue [Jani].
Please add fixes tag.
Fixes:
The eDP 1.5 spec adds a clarification for eDP 1.4x:
> For eDP v1.4x, if the Source device chooses the Main-Link rate by way
> of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using
DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as
> -Original Message-
> From: Poosa, Karthik
> Sent: Friday, December 1, 2023 10:28 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Gupta, Anshuman ; Nilawar, Badal
> ; Poosa, Karthik
> Subject: [PATCH] drm/i915/hwmon: Fix static analysis tool errors in i915
> hwmon
>
> Updated i915
Am 01.12.23 um 06:48 schrieb Zeng, Oak:
[SNIP]
3. MMU notifiers register hooks at certain core MM events, while GMEM
declares basic functions and internally invokes them. GMEM requires less from
the driver side -- no need to understand what core MM behaves at certain MMU
events. GMEM also
From: Tvrtko Ursulin
Commit 503579448db9 ("drm/i915/gsc: Mark internal GSC engine with reserved uabi
class")
made the GSC0 engine not have a valid uabi class and so broke the engine
reset counting, which in turn was made class based in cb823ed9915b
("drm/i915/gt: Use intel_gt as the primary
From: Tvrtko Ursulin
Engine->id namespace is per-tile so struct igt_live_test->reset_engine[]
needs to be two-dimensional so engine reset counts from all tiles can be
stored with no aliasing. With aliasing, if we had a real multi-tile
platform, the reset counts would be incorrect for same engine
== Series Details ==
Series: Prepare intel_fb for Xe (rev9)
URL : https://patchwork.freedesktop.org/series/126507/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13955 -> Patchwork_126507v9
Summary
---
**SUCCESS**
Hello,
Regression suspected here have nothing to do with my patch. Same failure is
already hit earlier:
http://gfx-ci.igk.intel.com/cibuglog-ng/results/all?query_key=fa6201fe80daa725cd0a1c7f21dfb248db8b5a96
Please re-report so we will get results from shards as well.
Thank you in advance,
The uncore code may not always be available (e.g. when we build the
display code with Xe), so we can't always rely on having the uncore's
spinlock.
To handle this, split the spin_lock/unlock_irqsave/restore() into
spin_lock/unlock() followed by a call to local_irq_save/restore() and
create
On 01.12.23 03:44, zhuweixi wrote:
Thanks!
I hope you understood that that was a joke :)
I am planning to present GMEM in Linux MM Alignment Sessions so I can collect
more input from the mm developers.
Sounds good. But please try inviting key HMM/driver developer as well.
Most of the
On 28.11.23 13:50, Weixi Zhu wrote:
This patch adds an abstraction layer, struct vm_object, that maintains
per-process virtual-to-physical mapping status stored in struct gm_mapping.
For example, a virtual page may be mapped to a CPU physical page or to a
device physical page. Struct vm_object
Supports FP16 format which is a binary floating-point computer
number format that occupies 16 bits in computer memory.Platform shall
render compression in display engine to receive FP16 compressed formats.
This kernel change was tested with IGT patch,
On Wed, 29 Nov 2023, Rodrigo Vivi wrote:
> On Wed, Nov 29, 2023 at 07:33:16PM +0200, Jani Nikula wrote:
>> Don't treat bools as integers.
>>
>> v2: Rebase
>>
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Rodrigo Vivi
Thanks for the reviews, pushed to din.
BR,
Jani.
>
>> ---
>>
Hi Dave & Sima -
As Ville observed in [1], yesterday's fixes pull depends on a commit
that wasn't included, and VRR might suffer without it. Here's the
missing one.
I see that Dave already sent the drm fixes pull on to Linus, but here
goes nothing.
BR,
Jani.
[1]
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